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Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_91 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_253 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_254 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_91( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_97 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_97( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[1]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of SystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst xbar of IntXbar_i1_o1_1 inst xbar_1 of IntXbar_i1_o1_2 inst xbar_2 of IntXbar_i1_o1_3 inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1 inst broadcast of BundleBridgeNexus_UInt32_1 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_5 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_1 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[1] invalidate tileHaltSinkNodeIn[0] wire tileWFISinkNodeIn : UInt<1>[1] invalidate tileWFISinkNodeIn[0] wire tileCeaseSinkNodeIn : UInt<1>[1] invalidate tileCeaseSinkNodeIn[0] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out connect tile_prci_domain.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell
module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_tval; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_0_cause; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_exception; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_0_priv; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_0_insn; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_valid; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_tval; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_0_cause; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_exception; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_0_priv; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_0_insn; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_valid; // @[BundleBridgeNexus.scala:20:9] wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [3:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_intsink_out_1_0; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [10:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7] wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7] wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7] wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7] wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7] wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7] wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7] wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7] wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7] wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7] wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7] wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17] wire ioNodeIn_txd; // @[MixedNode.scala:551:17] wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17] wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7] wire debug_ndreset; // @[DigitalTop.scala:47:7] wire debug_dmactive_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] wire uart_0_txd_0; // @[DigitalTop.scala:47:7] wire clockTapIn_clock; // @[MixedNode.scala:551:17] wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9] wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9] wire ibus_childClock; // @[LazyModuleImp.scala:155:31] wire ibus_childReset; // @[LazyModuleImp.scala:158:31] assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_valid = nexus_auto_in_insns_0_valid; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_iaddr = nexus_auto_in_insns_0_iaddr; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_0_insn = nexus_auto_in_insns_0_insn; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_0_priv = nexus_auto_in_insns_0_priv; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_exception = nexus_auto_in_insns_0_exception; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_interrupt = nexus_auto_in_insns_0_interrupt; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_0_cause = nexus_auto_in_insns_0_cause; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_tval = nexus_auto_in_insns_0_tval; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_valid = nexus_auto_out_insns_0_valid; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_iaddr = nexus_auto_out_insns_0_iaddr; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire [31:0] traceNodesIn_insns_0_insn = nexus_auto_out_insns_0_insn; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire [2:0] traceNodesIn_insns_0_priv = nexus_auto_out_insns_0_priv; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_exception = nexus_auto_out_insns_0_exception; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_interrupt = nexus_auto_out_insns_0_interrupt; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_insns_0_cause = nexus_auto_out_insns_0_cause; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_tval = nexus_auto_out_insns_0_tval; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17] assign nexus_nodeOut_insns_0_valid = nexus_nodeIn_insns_0_valid; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_iaddr = nexus_nodeIn_insns_0_iaddr; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_insn = nexus_nodeIn_insns_0_insn; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_priv = nexus_nodeIn_insns_0_priv; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_exception = nexus_nodeIn_insns_0_exception; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_interrupt = nexus_nodeIn_insns_0_interrupt; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_cause = nexus_nodeIn_insns_0_cause; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_tval = nexus_nodeIn_insns_0_tval; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17] assign nexus_auto_out_insns_0_valid = nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_iaddr = nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_insn = nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_priv = nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_exception = nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_interrupt = nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_cause = nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_tval = nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17] assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17] wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17] assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire tileWFISinkNodeIn_0; // @[MixedNode.scala:551:17] wire domainIn_clock; // @[MixedNode.scala:551:17] wire domainIn_reset; // @[MixedNode.scala:551:17] wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17] wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17] assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24] wire int_rtc_tick; // @[Counter.scala:117:24] assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24] wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24] wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge) IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27] .auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9] .auto_anon_out_0 (ibus_auto_int_bus_anon_out_0) ); // @[InterruptBus.scala:19:27] SystemBus sbus ( // @[SystemBus.scala:31:26] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address), .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), // @[HasTiles.scala:163:38] .auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), .auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset), .auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock), .auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset), .auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), .auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) ); // @[SystemBus.scala:31:26] PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44] .auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset), .auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17] .auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt) ); // @[PeripheryBus.scala:37:26] FrontBus fbus ( // @[FrontBus.scala:23:26] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset), .auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17] .auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26] ); // @[FrontBus.scala:23:26] PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), .auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), .auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26] .auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), .auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), .auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), .auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), .auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), .auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset), .auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), .auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset), .auto_fixedClockNode_anon_out_2_clock (domainIn_clock), .auto_fixedClockNode_anon_out_2_reset (domainIn_reset), .auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), .auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17] .auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), .custom_boot (custom_boot) ); // @[PeripheryBus.scala:37:26] MemoryBus mbus ( // @[MemoryBus.scala:30:26] .auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28] .auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17] .auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset), .auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17] .auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt) ); // @[MemoryBus.scala:30:26] CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), .auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), .auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), .auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), .auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), .auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), .auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), .auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), .auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), .auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), .auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), .auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), .auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), .auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), .auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26] .auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), .auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), .auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), .auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), .auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), .auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), .auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26] .auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26] ); // @[BankedCoherenceParams.scala:56:31] TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38] .auto_intsink_out_1_0 (_tile_prci_domain_auto_intsink_out_1_0), .auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17] .auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid (nexus_auto_in_insns_0_valid), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr (nexus_auto_in_insns_0_iaddr), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn (nexus_auto_in_insns_0_insn), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv (nexus_auto_in_insns_0_priv), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception (nexus_auto_in_insns_0_exception), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt (nexus_auto_in_insns_0_interrupt), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause (nexus_auto_in_insns_0_cause), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval (nexus_auto_in_insns_0_tval), .auto_element_reset_domain_rockettile_trace_source_out_time (nexus_auto_in_time), .auto_element_reset_domain_rockettile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39] .auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28] .auto_tl_master_clock_xing_out_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), .auto_tl_master_clock_xing_out_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), .auto_tl_master_clock_xing_out_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), .auto_tl_master_clock_xing_out_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), .auto_tl_master_clock_xing_out_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), .auto_tl_master_clock_xing_out_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), .auto_tl_master_clock_xing_out_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), .auto_tl_master_clock_xing_out_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), .auto_tl_master_clock_xing_out_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), .auto_tl_master_clock_xing_out_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), .auto_tl_master_clock_xing_out_b_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_address (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), .auto_tl_master_clock_xing_out_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), .auto_tl_master_clock_xing_out_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), .auto_tl_master_clock_xing_out_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), .auto_tl_master_clock_xing_out_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), .auto_tl_master_clock_xing_out_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), .auto_tl_master_clock_xing_out_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), .auto_tl_master_clock_xing_out_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), .auto_tl_master_clock_xing_out_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), .auto_tl_master_clock_xing_out_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), .auto_tl_master_clock_xing_out_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), .auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26] .auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26] ); // @[HasTiles.scala:163:38] IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26] IntXbar_i1_o1_2 xbar_1 ( // @[Xbar.scala:52:26] .auto_anon_in_0 (_tile_prci_domain_auto_intsink_out_1_0), // @[HasTiles.scala:163:38] .auto_anon_out_0 (tileWFISinkNodeIn_0) ); // @[Xbar.scala:52:26] IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26] BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39] .auto_out (_tileHartIdNexusNode_auto_out) ); // @[HasTiles.scala:75:39] CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28] .auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready), .auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid), .auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), .auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), .auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), .auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), .auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), .auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26] .tick (int_rtc_tick), // @[Counter.scala:117:24] .clock (_clint_domain_clock), .reset (_clint_domain_reset) ); // @[BusWrapper.scala:89:28] PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28] .auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9] .auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready), .auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid), .auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), .auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), .auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), .auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), .auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), .auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] TLDebugModule tlDM ( // @[Periphery.scala:88:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), .auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), .auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), .auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), .auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), .auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), .auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), .auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), .auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0), .io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7] .io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7] .io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17] .io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17] .io_ctrl_ndreset (debug_ndreset), .io_ctrl_dmactive (debug_dmactive_0), .io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7] .io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), .io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), .io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), .io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), .io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:88:26] DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75] BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28] .auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), .auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), .auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), .auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), .auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ScratchpadBank bank ( // @[Scratchpad.scala:65:28] .auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), .auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), .auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), .auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), .auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), .auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26] .auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26] ); // @[Scratchpad.scala:65:28] SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38] .auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), .auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), .auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), .auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), .auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), .auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), .auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), .auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), .auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), .auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), .auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26] .auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26] .serial_tl_0_in_ready (serial_tl_0_in_ready_0), .serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7] .serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_valid (serial_tl_0_out_valid_0), .serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0), .serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7] .serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy), .serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy) ); // @[PeripheryTLSerial.scala:116:38] TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44] .auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0), .auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), .auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), .auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), .auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), .auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), .auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), .auto_uart_0_io_out_txd (ioNodeIn_txd), .auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17] .auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26] ); // @[UART.scala:270:44] IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (ibus_auto_int_bus_anon_in_0) ); // @[Crossing.scala:109:29] ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28] .auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7] .auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7] .auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), .auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), .auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30] .auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock), .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset), .auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock), .auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset), .auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock), .auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset), .auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock), .auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset), .auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock), .auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset), .auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock), .auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset), .auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock), .auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset) ); // @[HasChipyardPRCI.scala:51:30] ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15] .auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock), .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset), .auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset) ); // @[ClockGroupCombiner.scala:19:15] ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40] .auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26] .auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26] ); // @[GlobalNoC.scala:45:40] BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44] DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21] .io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26] .io_dmi_req_valid (_dtm_io_dmi_req_valid), .io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), .io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), .io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), .io_dmi_resp_ready (_dtm_io_dmi_resp_ready), .io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26] .io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26] .io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26] .io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7] .io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7] .io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0), .io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven), .rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:166:21] assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7] assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_81 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, flip out_credit_available : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} inst input_buffer of InputBuffer_81 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) inst route_arbiter of Arbiter5_RouteComputerReq_9 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_9 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_9 : connect states[4].g, UInt<3>(0h2) node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}[5] wire vcalloc_vals : UInt<1>[5] node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0)) node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23) node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_20 = and(io.router_req.ready, io.router_req.valid) when _T_20 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_22 = or(_T_21, vcalloc_vals[2]) node _T_23 = or(_T_22, vcalloc_vals[3]) node _T_24 = or(_T_23, vcalloc_vals[4]) when _T_24 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = bits(vcalloc_sel, 0, 0) node _mask_T_9 = bits(vcalloc_sel, 1, 1) node _mask_T_10 = bits(vcalloc_sel, 2, 2) node _mask_T_11 = bits(vcalloc_sel, 3, 3) node _mask_T_12 = bits(vcalloc_sel, 4, 4) node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0)) node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0)) node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0)) node _mask_T_18 = or(_mask_T_13, _mask_T_14) node _mask_T_19 = or(_mask_T_18, _mask_T_15) node _mask_T_20 = or(_mask_T_19, _mask_T_16) node _mask_T_21 = or(_mask_T_20, _mask_T_17) wire _mask_WIRE : UInt<5> connect _mask_WIRE, _mask_T_21 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}} wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5] node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[5] node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_76 connect _io_vcalloc_req_bits_WIRE_8[2], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_8[3], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_94 connect _io_vcalloc_req_bits_WIRE_8[4], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_14 : UInt<3> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_103 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_15 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_15.egress_node_id, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117) wire _io_vcalloc_req_bits_WIRE_17 : UInt<5> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_121 connect _io_vcalloc_req_bits_WIRE_15.egress_node, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123) node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124) node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_130 connect _io_vcalloc_req_bits_WIRE_15.ingress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_131, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_19 : UInt<5> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_139 connect _io_vcalloc_req_bits_WIRE_15.ingress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_143) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_144) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_15.vnet_id, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_15 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[3] invalidate vcalloc_reqs[1].vc_sel.`1`[4] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].flow, states[4].flow node _T_25 = bits(vcalloc_sel, 4, 4) node _T_26 = and(vcalloc_vals[4], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[4].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready) node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1) connect io.debug.va_stall, _io_debug_va_stall_T_9 node _T_28 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_28 : node _T_29 = bits(vcalloc_sel, 0, 0) when _T_29 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].g, UInt<3>(0h3) node _T_30 = eq(states[0].g, UInt<3>(0h2)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].g, UInt<3>(0h3) node _T_35 = eq(states[1].g, UInt<3>(0h2)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_35, UInt<1>(0h1), "") : assert_4 node _T_39 = bits(vcalloc_sel, 2, 2) when _T_39 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].g, UInt<3>(0h3) node _T_40 = eq(states[2].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = bits(vcalloc_sel, 3, 3) when _T_44 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].g, UInt<3>(0h3) node _T_45 = eq(states[3].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_45, UInt<1>(0h1), "") : assert_6 node _T_49 = bits(vcalloc_sel, 4, 4) when _T_49 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].g, UInt<3>(0h3) node _T_50 = eq(states[4].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_50, UInt<1>(0h1), "") : assert_7 inst salloc_arb of SwitchArbiter_221 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] node credit_available_lo = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_hi = cat(credit_available_hi_hi, states[4].vc_sel.`0`[2]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_hi_hi_1 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[4].vc_sel.`1`[2]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_2 = cat(_credit_available_T_1, _credit_available_T) node credit_available_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_hi_hi_2 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, io.out_credit_available.`0`[2]) node _credit_available_T_3 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_3 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`1`[2]) node _credit_available_T_4 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_5 = cat(_credit_available_T_4, _credit_available_T_3) node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5) node credit_available = neq(_credit_available_T_6, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_54 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_55 = and(_T_54, input_buffer.io.deq[4].bits.tail) when _T_55 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_17 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7) node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14 node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_16 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _vc_sel_WIRE : UInt<1>[5] node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6) node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_13 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_22 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25) node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26) node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_31 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34) node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_40 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_49 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_6 : UInt<1>[5] node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_58 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_67 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70) node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71) node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_76 connect _vc_sel_WIRE_6[2], _vc_sel_WIRE_9 node _vc_sel_T_77 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_78 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_79 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_80 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_81 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_82 = or(_vc_sel_T_77, _vc_sel_T_78) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_79) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_80) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_81) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_85 connect _vc_sel_WIRE_6[3], _vc_sel_WIRE_10 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_88) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_89) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_90) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_94 connect _vc_sel_WIRE_6[4], _vc_sel_WIRE_11 connect vc_sel.`1`, _vc_sel_WIRE_6 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_3 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`1`[2]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`1`[3]) node channel_oh_1 = or(_channel_oh_T_5, vc_sel.`1`[4]) node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_3 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, vc_sel.`1`[2]) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 4, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node _virt_channel_T_16 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_18 = or(_virt_channel_T_16, _virt_channel_T_17) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_18 node _T_56 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_56 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6) node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6) node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6) node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`1`[3] invalidate states[1].vc_sel.`1`[4] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].g connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) node _T_57 = asUInt(reset) when _T_57 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0)
module InputUnit_81( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_488 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_488( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_QueuedRequest_q36_e28_7 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}}}, valid : UInt<36>, flip pop : { valid : UInt<1>, bits : UInt<6>}, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}} regreset valid : UInt<36>, clock, reset, UInt<36>(0h0) cmem head : UInt<5> [36] cmem tail : UInt<5> [36] regreset used : UInt<28>, clock, reset, UInt<28>(0h0) cmem next : UInt<5> [28] cmem data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} [28] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 27, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 27, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 27, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = shl(_freeOH_T_9, 8) node _freeOH_T_11 = bits(_freeOH_T_10, 27, 0) node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) node _freeOH_T_13 = shl(_freeOH_T_12, 16) node _freeOH_T_14 = bits(_freeOH_T_13, 27, 0) node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) node _freeOH_T_16 = bits(_freeOH_T_15, 27, 0) node _freeOH_T_17 = shl(_freeOH_T_16, 1) node _freeOH_T_18 = not(_freeOH_T_17) node _freeOH_T_19 = not(used) node freeOH = and(_freeOH_T_18, _freeOH_T_19) node freeIdx_hi = bits(freeOH, 28, 16) node freeIdx_lo = bits(freeOH, 15, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 15, 8) node freeIdx_lo_1 = bits(_freeIdx_T_1, 7, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 7, 4) node freeIdx_lo_2 = bits(_freeIdx_T_3, 3, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node freeIdx_hi_3 = bits(_freeIdx_T_5, 3, 2) node freeIdx_lo_3 = bits(_freeIdx_T_5, 1, 0) node _freeIdx_T_6 = orr(freeIdx_hi_3) node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) node _freeIdx_T_8 = bits(_freeIdx_T_7, 1, 1) node _freeIdx_T_9 = cat(_freeIdx_T_6, _freeIdx_T_8) node _freeIdx_T_10 = cat(_freeIdx_T_4, _freeIdx_T_9) node _freeIdx_T_11 = cat(_freeIdx_T_2, _freeIdx_T_10) node freeIdx = cat(_freeIdx_T, _freeIdx_T_11) wire valid_set : UInt<36> connect valid_set, UInt<36>(0h0) wire valid_clr : UInt<36> connect valid_clr, UInt<36>(0h0) wire used_set : UInt<28> connect used_set, UInt<28>(0h0) wire used_clr : UInt<28> connect used_clr, UInt<28>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 5, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 35, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH write mport MPORT = data[freeIdx], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_1 = eq(io.pop.valid, UInt<1>(0h0)) node _T_2 = dshr(io.valid, io.pop.bits) node _T_3 = bits(_T_2, 0, 0) node _T_4 = or(_T_1, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 4, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 27, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_8 = eq(pop_head, MPORT_4) when _T_8 : node valid_clr_shiftAmount = bits(io.pop.bits, 5, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 35, 0) connect valid_clr, _valid_clr_T_1 node _T_9 = and(io.push.ready, io.push.valid) node _T_10 = and(_T_9, push_valid) node _T_11 = eq(push_tail, pop_head) node _T_12 = and(_T_10, _T_11) read mport MPORT_5 = next[pop_head], clock node _T_13 = mux(_T_12, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_13 node _T_14 = eq(io.pop.valid, UInt<1>(0h0)) node _T_15 = or(UInt<1>(0h1), _T_14) node _T_16 = or(_T_15, pop_valid) when _T_16 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2
module ListBuffer_QueuedRequest_q36_e28_7( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14] input io_push_bits_data_control, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14] input [8:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14] output [35:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output io_data_prio_0, // @[ListBuffer.scala:39:14] output io_data_prio_1, // @[ListBuffer.scala:39:14] output io_data_prio_2, // @[ListBuffer.scala:39:14] output io_data_control, // @[ListBuffer.scala:39:14] output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14] output [2:0] io_data_param, // @[ListBuffer.scala:39:14] output [2:0] io_data_size, // @[ListBuffer.scala:39:14] output [5:0] io_data_source, // @[ListBuffer.scala:39:14] output [8:0] io_data_tag, // @[ListBuffer.scala:39:14] output [5:0] io_data_offset, // @[ListBuffer.scala:39:14] output [5:0] io_data_put // @[ListBuffer.scala:39:14] ); wire [39:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [4:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [4:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [4:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [4:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_0_0 = io_push_bits_data_prio_0; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_2_0 = io_push_bits_data_prio_2; // @[ListBuffer.scala:36:7] wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7] wire [8:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire io_data_prio_0_0; // @[ListBuffer.scala:36:7] wire io_data_prio_1_0; // @[ListBuffer.scala:36:7] wire io_data_prio_2_0; // @[ListBuffer.scala:36:7] wire io_data_control_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_source_0; // @[ListBuffer.scala:36:7] wire [8:0] io_data_tag_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7] wire [35:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [35:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [27:0] used; // @[ListBuffer.scala:50:22] assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_source_0 = _data_ext_R0_data[18:13]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_tag_0 = _data_ext_R0_data[27:19]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_offset_0 = _data_ext_R0_data[33:28]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_put_0 = _data_ext_R0_data[39:34]; // @[ListBuffer.scala:36:7, :52:18] wire [27:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [28:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [27:0] _freeOH_T_2 = _freeOH_T_1[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [29:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_5 = _freeOH_T_4[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [31:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_8 = _freeOH_T_7[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [35:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_11 = _freeOH_T_10[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_14 = _freeOH_T_13[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [27:0] _freeOH_T_16 = _freeOH_T_15; // @[package.scala:253:43, :254:17] wire [28:0] _freeOH_T_17 = {_freeOH_T_16, 1'h0}; // @[package.scala:254:17] wire [28:0] _freeOH_T_18 = ~_freeOH_T_17; // @[ListBuffer.scala:54:{16,32}] wire [27:0] _freeOH_T_19 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [28:0] freeOH = {1'h0, _freeOH_T_18[27:0] & _freeOH_T_19}; // @[ListBuffer.scala:54:{16,38,40}] wire [12:0] freeIdx_hi = freeOH[28:16]; // @[OneHot.scala:30:18] wire [15:0] freeIdx_lo = freeOH[15:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_1 = {3'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_1 = _freeIdx_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_1 = _freeIdx_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_2 = _freeIdx_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_2 = _freeIdx_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_3 = _freeIdx_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_3 = _freeIdx_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_8 = _freeIdx_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_9 = {_freeIdx_T_6, _freeIdx_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_10 = {_freeIdx_T_4, _freeIdx_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_11 = {_freeIdx_T_2, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [4:0] freeIdx = {_freeIdx_T, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [35:0] valid_set; // @[ListBuffer.scala:57:30] wire [35:0] valid_clr; // @[ListBuffer.scala:58:30] wire [27:0] used_set; // @[ListBuffer.scala:59:30] wire [27:0] used_clr; // @[ListBuffer.scala:60:30] wire [35:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [35:0] _valid_set_T_1 = _valid_set_T[35:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 36'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[27:0] : 28'h0; // @[Decoupled.scala:51:35] wire [35:0] _GEN = {30'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [35:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_175 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_175( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveToNoC_1 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} inst a of TLAFromNoC_1 connect a.clock, clock connect a.reset, reset inst b of TLBToNoC_1 connect b.clock, clock connect b.reset, reset inst c of TLCFromNoC_1 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_1 connect d.clock, clock connect d.reset, reset inst e of TLEFromNoC_1 connect e.clock, clock connect e.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready connect b.io.protocol, io.tilelink.b connect io.tilelink.c.bits, c.io.protocol.bits connect io.tilelink.c.valid, c.io.protocol.valid connect c.io.protocol.ready, io.tilelink.c.ready connect d.io.protocol, io.tilelink.d connect io.tilelink.e.bits, e.io.protocol.bits connect io.tilelink.e.valid, e.io.protocol.valid connect e.io.protocol.ready, io.tilelink.e.ready connect a.io.flit, io.flits.a connect io.flits.b.bits, b.io.flit.bits connect io.flits.b.valid, b.io.flit.valid connect b.io.flit.ready, io.flits.b.ready connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready connect e.io.flit, io.flits.e
module TLSlaveToNoC_1( // @[Tilelink.scala:125:7] input clock, // @[Tilelink.scala:125:7] input reset, // @[Tilelink.scala:125:7] input io_tilelink_a_ready, // @[Tilelink.scala:132:14] output io_tilelink_a_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14] output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_b_ready, // @[Tilelink.scala:132:14] input io_tilelink_b_valid, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:132:14] input [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:132:14] input io_tilelink_c_ready, // @[Tilelink.scala:132:14] output io_tilelink_c_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_d_ready, // @[Tilelink.scala:132:14] input io_tilelink_d_valid, // @[Tilelink.scala:132:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14] input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14] input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_e_valid, // @[Tilelink.scala:132:14] output [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:132:14] output io_flits_a_ready, // @[Tilelink.scala:132:14] input io_flits_a_valid, // @[Tilelink.scala:132:14] input io_flits_a_bits_head, // @[Tilelink.scala:132:14] input io_flits_a_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14] input io_flits_b_ready, // @[Tilelink.scala:132:14] output io_flits_b_valid, // @[Tilelink.scala:132:14] output io_flits_b_bits_head, // @[Tilelink.scala:132:14] output io_flits_b_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:132:14] output [3:0] io_flits_b_bits_egress_id, // @[Tilelink.scala:132:14] output io_flits_c_ready, // @[Tilelink.scala:132:14] input io_flits_c_valid, // @[Tilelink.scala:132:14] input io_flits_c_bits_head, // @[Tilelink.scala:132:14] input io_flits_c_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:132:14] input io_flits_d_ready, // @[Tilelink.scala:132:14] output io_flits_d_valid, // @[Tilelink.scala:132:14] output io_flits_d_bits_head, // @[Tilelink.scala:132:14] output io_flits_d_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14] output [3:0] io_flits_d_bits_egress_id, // @[Tilelink.scala:132:14] input io_flits_e_valid, // @[Tilelink.scala:132:14] input io_flits_e_bits_head, // @[Tilelink.scala:132:14] input io_flits_e_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_e_bits_payload // @[Tilelink.scala:132:14] ); wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17] TLAFromNoC a ( // @[Tilelink.scala:143:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:143:17] TLBToNoC_1 b ( // @[Tilelink.scala:144:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload), .io_flit_bits_egress_id (io_flits_b_bits_egress_id) ); // @[Tilelink.scala:144:17] TLCFromNoC_1 c ( // @[Tilelink.scala:145:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[64:0]) // @[Tilelink.scala:156:14] ); // @[Tilelink.scala:145:17] TLDToNoC_1 d ( // @[Tilelink.scala:146:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:146:17] TLEFromNoC_1 e ( // @[Tilelink.scala:147:17] .clock (clock), .reset (reset), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_tail (io_flits_e_bits_tail), .io_flit_bits_payload (io_flits_e_bits_payload[4:0]) // @[Tilelink.scala:158:14] ); // @[Tilelink.scala:147:17] assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_10 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock inst q of Queue3_EgressFlit_10 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h0), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h9), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0hc), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h3), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h6), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_10( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_201 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_201( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_104 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_104( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SystemBus : output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, coupler_to_bus_named_coh_widget_anon_out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, coupler_to_bus_named_coh_widget_anon_out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, coupler_to_bus_named_coh_widget_anon_out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, coupler_to_bus_named_coh_widget_anon_out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, coupler_to_bus_named_coh_widget_anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, coupler_to_bus_named_coh_widget_anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, coupler_to_bus_named_coh_widget_anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, coupler_to_bus_named_coh_widget_anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst sbus_clock_groups of ClockGroupAggregator_sbus inst clockGroup of ClockGroup inst fixedClockNode of FixedClockBroadcast_4 inst broadcast of BundleBridgeNexus_NoOutput inst system_bus_xbar of TLXbar_sbus_i3_o9_a32d128s6k7z4c connect system_bus_xbar.clock, childClock connect system_bus_xbar.reset, childReset inst fixer of TLFIFOFixer connect fixer.clock, childClock connect fixer.reset, childReset inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus connect coupler_to_bus_named_cbus.clock, childClock connect coupler_to_bus_named_cbus.reset, childReset inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus connect coupler_from_bus_named_fbus.clock, childClock connect coupler_from_bus_named_fbus.reset, childReset inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh connect coupler_to_bus_named_coh.clock, childClock connect coupler_to_bus_named_coh.reset, childReset inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile connect coupler_from_rockettile.clock, childClock connect coupler_from_rockettile.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, sbus_clock_groups.auto.out_0 connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_xbar.auto.anon_out_0 connect coupler_to_bus_named_coh.auto.widget_anon_in_0, system_bus_xbar.auto.anon_out_1 connect coupler_to_bus_named_coh.auto.widget_anon_in_1, system_bus_xbar.auto.anon_out_2 connect coupler_to_bus_named_coh.auto.widget_anon_in_2, system_bus_xbar.auto.anon_out_3 connect coupler_to_bus_named_coh.auto.widget_anon_in_3, system_bus_xbar.auto.anon_out_4 connect coupler_to_bus_named_coh.auto.widget_anon_in_4, system_bus_xbar.auto.anon_out_5 connect coupler_to_bus_named_coh.auto.widget_anon_in_5, system_bus_xbar.auto.anon_out_6 connect coupler_to_bus_named_coh.auto.widget_anon_in_6, system_bus_xbar.auto.anon_out_7 connect coupler_to_bus_named_coh.auto.widget_anon_in_7, system_bus_xbar.auto.anon_out_8 connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_2, fixer.auto.anon_out_2 connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out_0 connect fixer.auto.anon_in_2, coupler_from_rockettile.auto.tl_out_1 connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1 connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_0.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_0.d, auto.coupler_to_bus_named_coh_widget_anon_out_0.d connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_0.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_0.b, auto.coupler_to_bus_named_coh_widget_anon_out_0.b connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_0.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.a.ready connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_1.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_1.d, auto.coupler_to_bus_named_coh_widget_anon_out_1.d connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_1.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_1.b, auto.coupler_to_bus_named_coh_widget_anon_out_1.b connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_1.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.a.ready connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_2.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_2.d, auto.coupler_to_bus_named_coh_widget_anon_out_2.d connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_2.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_2.b, auto.coupler_to_bus_named_coh_widget_anon_out_2.b connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_2.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.a.ready connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_3.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_3.d, auto.coupler_to_bus_named_coh_widget_anon_out_3.d connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_3.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_3.b, auto.coupler_to_bus_named_coh_widget_anon_out_3.b connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_3.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.a.ready connect auto.coupler_to_bus_named_coh_widget_anon_out_4.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_4.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_4.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_4.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_4.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_4.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_4.d, auto.coupler_to_bus_named_coh_widget_anon_out_4.d connect auto.coupler_to_bus_named_coh_widget_anon_out_4.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_4.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_4.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_4.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_4.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_4.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_4.b, auto.coupler_to_bus_named_coh_widget_anon_out_4.b connect auto.coupler_to_bus_named_coh_widget_anon_out_4.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_4.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_4.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_4.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_4.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_4.a.ready connect auto.coupler_to_bus_named_coh_widget_anon_out_5.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_5.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_5.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_5.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_5.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_5.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_5.d, auto.coupler_to_bus_named_coh_widget_anon_out_5.d connect auto.coupler_to_bus_named_coh_widget_anon_out_5.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_5.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_5.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_5.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_5.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_5.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_5.b, auto.coupler_to_bus_named_coh_widget_anon_out_5.b connect auto.coupler_to_bus_named_coh_widget_anon_out_5.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_5.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_5.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_5.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_5.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_5.a.ready connect auto.coupler_to_bus_named_coh_widget_anon_out_6.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_6.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_6.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_6.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_6.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_6.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_6.d, auto.coupler_to_bus_named_coh_widget_anon_out_6.d connect auto.coupler_to_bus_named_coh_widget_anon_out_6.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_6.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_6.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_6.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_6.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_6.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_6.b, auto.coupler_to_bus_named_coh_widget_anon_out_6.b connect auto.coupler_to_bus_named_coh_widget_anon_out_6.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_6.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_6.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_6.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_6.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_6.a.ready connect auto.coupler_to_bus_named_coh_widget_anon_out_7.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_7.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_7.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_7.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_7.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_7.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_7.d, auto.coupler_to_bus_named_coh_widget_anon_out_7.d connect auto.coupler_to_bus_named_coh_widget_anon_out_7.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_7.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_7.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_7.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_7.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_7.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out_7.b, auto.coupler_to_bus_named_coh_widget_anon_out_7.b connect auto.coupler_to_bus_named_coh_widget_anon_out_7.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_7.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out_7.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_7.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out_7.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_7.a.ready connect coupler_from_rockettile.auto.tl_master_clock_xing_in_0, auto.coupler_from_rockettile_tl_master_clock_xing_in_0 connect coupler_from_rockettile.auto.tl_master_clock_xing_in_1, auto.coupler_from_rockettile_tl_master_clock_xing_in_1 connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset
module SystemBus( // @[ClockDomain.scala:14:9] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_7_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_7_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_7_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_7_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_7_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_6_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_6_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_6_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_6_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_6_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_5_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_5_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_5_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_5_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_5_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_4_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_4_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_4_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_4_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_4_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire coupler_to_bus_named_coh_auto_widget_anon_in_0_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [5:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [127:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _system_bus_xbar_auto_anon_out_0_a_valid; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_out_0_a_bits_opcode; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_out_0_a_bits_param; // @[SystemBus.scala:47:43] wire [3:0] _system_bus_xbar_auto_anon_out_0_a_bits_size; // @[SystemBus.scala:47:43] wire [5:0] _system_bus_xbar_auto_anon_out_0_a_bits_source; // @[SystemBus.scala:47:43] wire [28:0] _system_bus_xbar_auto_anon_out_0_a_bits_address; // @[SystemBus.scala:47:43] wire [15:0] _system_bus_xbar_auto_anon_out_0_a_bits_mask; // @[SystemBus.scala:47:43] wire [127:0] _system_bus_xbar_auto_anon_out_0_a_bits_data; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_out_0_a_bits_corrupt; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_out_0_d_ready; // @[SystemBus.scala:47:43] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_1_clock_0 = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_1_reset_0 = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_0_clock_0 = auto_sbus_clock_groups_in_member_sbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_0_reset_0 = auto_sbus_clock_groups_in_member_sbus_0_reset; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] fixer_auto_anon_in_2_b_bits_data = 128'h0; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_2_b_bits_data = 128'h0; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_x1_anonOut_1_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] fixer_x1_anonIn_1_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_from_rockettile_auto_tl_out_1_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_from_rockettile_x1_tlOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_x1_tlIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire sbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire sbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire sbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_2_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_x1_anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__a_notFIFO_T_22 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_47 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_72 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_2 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_2_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_out_1_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_x1_tlOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_no_bufferOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_no_bufferIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_source = 6'h28; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_source = 6'h28; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_source = 6'h28; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_source = 6'h28; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_source = 6'h28; // @[MixedNode.scala:551:17] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_14 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_6 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_7 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_6 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_7 = 1'h1; // @[FIFOFixer.scala:96:47] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire [2:0] fixer__allIDs_FIFOed_T_2 = 3'h7; // @[FIFOFixer.scala:127:48] wire [7:0] fixer__allIDs_FIFOed_T_1 = 8'hFF; // @[FIFOFixer.scala:127:48] wire [16:0] fixer__allIDs_FIFOed_T = 17'h1FFFF; // @[FIFOFixer.scala:127:48] wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_13 = 33'h0; // @[Parameters.scala:137:46] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0; // @[ClockDomain.scala:14:9] wire [6:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_7_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_7_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_7_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_7_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_6_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_6_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_6_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_6_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_5_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_5_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_5_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_5_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_4_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_4_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_4_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_4_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_3_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_3_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_2_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_2_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_1_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_1_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_0_e_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_0_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire sbus_clock_groups_auto_in_member_sbus_1_clock = auto_sbus_clock_groups_in_member_sbus_1_clock_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_in_member_sbus_1_reset = auto_sbus_clock_groups_in_member_sbus_1_reset_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_in_member_sbus_0_clock = auto_sbus_clock_groups_in_member_sbus_0_clock_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_in_member_sbus_0_reset = auto_sbus_clock_groups_in_member_sbus_0_reset_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_7_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_7_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_6_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_6_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_5_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_5_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_4_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_4_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire sbus_clock_groups_nodeIn_member_sbus_1_clock = sbus_clock_groups_auto_in_member_sbus_1_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeIn_member_sbus_1_reset = sbus_clock_groups_auto_in_member_sbus_1_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeIn_member_sbus_0_clock = sbus_clock_groups_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeIn_member_sbus_0_reset = sbus_clock_groups_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17] assign auto_sbus_clock_groups_out_member_coh_0_clock_0 = sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17] assign auto_sbus_clock_groups_out_member_coh_0_reset_0 = sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_sbus_0_clock = sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_sbus_0_reset = sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign sbus_clock_groups_x1_nodeOut_member_coh_0_clock = sbus_clock_groups_nodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_x1_nodeOut_member_coh_0_reset = sbus_clock_groups_nodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_nodeOut_member_sbus_0_clock = sbus_clock_groups_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_nodeOut_member_sbus_0_reset = sbus_clock_groups_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_auto_out_0_member_sbus_0_clock = sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[ClockGroup.scala:53:9] assign sbus_clock_groups_auto_out_0_member_sbus_0_reset = sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[ClockGroup.scala:53:9] assign sbus_clock_groups_auto_out_1_member_coh_0_clock = sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9] assign sbus_clock_groups_auto_out_1_member_coh_0_reset = sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire clockGroup_nodeIn_member_sbus_0_clock = clockGroup_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_sbus_0_reset = clockGroup_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_x1_anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_1_a_ready = fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_valid = fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_1_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_a_bits_opcode = fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_1_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_a_bits_param = fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_auto_tl_out_1_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_1_a_bits_size = fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_auto_tl_out_1_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_1_a_bits_source = fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_auto_tl_out_1_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_1_a_bits_address = fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] coupler_from_rockettile_auto_tl_out_1_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [15:0] fixer_x1_anonIn_1_a_bits_mask = fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] coupler_from_rockettile_auto_tl_out_1_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [127:0] fixer_x1_anonIn_1_a_bits_data = fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_bits_corrupt = fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_b_ready = fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_1_b_valid = fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_1_b_bits_opcode = fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_1_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_1_b_bits_param = fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_auto_tl_out_1_b_bits_size = fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_1_b_bits_source = fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_x1_anonIn_1_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_auto_tl_out_1_b_bits_address = fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] coupler_from_rockettile_auto_tl_out_1_b_bits_mask = fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_1_c_ready = fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_c_valid = fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_1_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_c_bits_opcode = fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_1_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_c_bits_param = fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_auto_tl_out_1_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_1_c_bits_size = fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_auto_tl_out_1_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_1_c_bits_source = fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_auto_tl_out_1_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_1_c_bits_address = fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [127:0] coupler_from_rockettile_auto_tl_out_1_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [127:0] fixer_x1_anonIn_1_c_bits_data = fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_c_bits_corrupt = fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_d_ready = fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_1_d_valid = fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_1_d_bits_opcode = fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_1_d_bits_param = fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_auto_tl_out_1_d_bits_size = fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_x1_anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_1_d_bits_source = fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [6:0] coupler_from_rockettile_auto_tl_out_1_d_bits_sink = fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_x1_anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_1_d_bits_denied = fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_auto_tl_out_1_d_bits_data = fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_1_d_bits_corrupt = fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_e_ready = fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_1_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_e_valid = fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9] wire [6:0] coupler_from_rockettile_auto_tl_out_1_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [6:0] fixer_x1_anonIn_1_e_bits_sink = fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_0_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_0_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_0_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_0_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_auto_tl_out_0_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_0_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_auto_tl_out_0_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] coupler_from_rockettile_auto_tl_out_0_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [15:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] coupler_from_rockettile_auto_tl_out_0_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [127:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_0_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_0_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_0_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_0_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_0_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_auto_tl_out_0_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_0_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [6:0] coupler_from_rockettile_auto_tl_out_0_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_0_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_auto_tl_out_0_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_0_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [6:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire fixer_x1_anonOut_1_a_ready = fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] fixer_x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] fixer_x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_b_valid = fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_b_bits_opcode = fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_b_bits_param = fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_1_b_bits_size = fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_b_bits_source = fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_1_b_bits_address = fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_x1_anonOut_1_b_bits_mask = fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_c_ready = fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_1_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_1_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_1_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] fixer_x1_anonOut_1_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_d_valid = fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_d_bits_opcode = fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_d_bits_param = fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_1_d_bits_size = fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_d_bits_source = fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_x1_anonOut_1_d_bits_sink = fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_d_bits_denied = fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_x1_anonOut_1_d_bits_data = fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_d_bits_corrupt = fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_e_ready = fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_e_valid; // @[MixedNode.scala:542:17] wire [6:0] fixer_x1_anonOut_1_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_out_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_ready; // @[FIFOFixer.scala:50:9] wire [6:0] fixer_auto_anon_out_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_8 = fixer_x1_anonOut_1_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_2_a_valid = fixer_x1_anonOut_1_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_opcode = fixer_x1_anonOut_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_param = fixer_x1_anonOut_1_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_size = fixer_x1_anonOut_1_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_source = fixer_x1_anonOut_1_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_address = fixer_x1_anonOut_1_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_mask = fixer_x1_anonOut_1_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_data = fixer_x1_anonOut_1_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_corrupt = fixer_x1_anonOut_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_b_ready = fixer_x1_anonOut_1_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_1_b_valid = fixer_x1_anonOut_1_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_opcode = fixer_x1_anonOut_1_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_param = fixer_x1_anonOut_1_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_size = fixer_x1_anonOut_1_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_source = fixer_x1_anonOut_1_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_address = fixer_x1_anonOut_1_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_mask = fixer_x1_anonOut_1_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_c_ready = fixer_x1_anonOut_1_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_2_c_valid = fixer_x1_anonOut_1_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_opcode = fixer_x1_anonOut_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_param = fixer_x1_anonOut_1_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_size = fixer_x1_anonOut_1_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_source = fixer_x1_anonOut_1_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_address = fixer_x1_anonOut_1_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_data = fixer_x1_anonOut_1_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_corrupt = fixer_x1_anonOut_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_d_ready = fixer_x1_anonOut_1_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_1_d_valid = fixer_x1_anonOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_opcode = fixer_x1_anonOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_param = fixer_x1_anonOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_size = fixer_x1_anonOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_source = fixer_x1_anonOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_sink = fixer_x1_anonOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_denied = fixer_x1_anonOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_data = fixer_x1_anonOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_corrupt = fixer_x1_anonOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_e_ready = fixer_x1_anonOut_1_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_2_e_valid = fixer_x1_anonOut_1_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_e_bits_sink = fixer_x1_anonOut_1_e_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_25 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_a_ready = fixer_x1_anonIn_1_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_8 = fixer_x1_anonIn_1_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_1_a_bits_opcode = fixer_x1_anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_param = fixer_x1_anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_size = fixer_x1_anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_source = fixer_x1_anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_address = fixer_x1_anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_50 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_10 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_1_a_bits_mask = fixer_x1_anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_data = fixer_x1_anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_corrupt = fixer_x1_anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_b_ready = fixer_x1_anonIn_1_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_b_valid = fixer_x1_anonIn_1_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_opcode = fixer_x1_anonIn_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_param = fixer_x1_anonIn_1_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_size = fixer_x1_anonIn_1_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_source = fixer_x1_anonIn_1_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_address = fixer_x1_anonIn_1_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_mask = fixer_x1_anonIn_1_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_c_ready = fixer_x1_anonIn_1_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_1_c_valid = fixer_x1_anonIn_1_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_opcode = fixer_x1_anonIn_1_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_param = fixer_x1_anonIn_1_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_size = fixer_x1_anonIn_1_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_source = fixer_x1_anonIn_1_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_address = fixer_x1_anonIn_1_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_data = fixer_x1_anonIn_1_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_corrupt = fixer_x1_anonIn_1_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_d_ready = fixer_x1_anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_d_valid = fixer_x1_anonIn_1_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_opcode = fixer_x1_anonIn_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_param = fixer_x1_anonIn_1_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_size = fixer_x1_anonIn_1_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_source = fixer_x1_anonIn_1_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_sink = fixer_x1_anonIn_1_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_denied = fixer_x1_anonIn_1_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_data = fixer_x1_anonIn_1_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_corrupt = fixer_x1_anonIn_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_e_ready = fixer_x1_anonIn_1_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_1_e_valid = fixer_x1_anonIn_1_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_e_bits_sink = fixer_x1_anonIn_1_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_10 = fixer__a_notFIFO_T_4 | fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_11 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_12 = {1'h0, fixer__a_notFIFO_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_15 = fixer__a_notFIFO_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_16 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_17 = {1'h0, fixer__a_notFIFO_T_16}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_18 = fixer__a_notFIFO_T_17 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_20 = fixer__a_notFIFO_T_19 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_21 = fixer__a_notFIFO_T_15 | fixer__a_notFIFO_T_20; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_23 = fixer__a_notFIFO_T_21; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23; // @[Mux.scala:30:73] wire fixer_a_notFIFO = fixer__a_notFIFO_T_24; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [8:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [7:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [7:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [8:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [7:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [16:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [16:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [16:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [31:0] fixer__SourceIdSet_T = 32'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [31:0] fixer__SourceIdClear_T = 32'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [16:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_26 = {1'h0, fixer__a_notFIFO_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_26 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_28 = fixer__a_notFIFO_T_27; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_29 = fixer__a_notFIFO_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_30 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_31 = {1'h0, fixer__a_notFIFO_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_32 = fixer__a_notFIFO_T_31 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_34 = fixer__a_notFIFO_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_35 = fixer__a_notFIFO_T_29 | fixer__a_notFIFO_T_34; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_36 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_37 = {1'h0, fixer__a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_38; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_40 = fixer__a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_41 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_42 = {1'h0, fixer__a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_43 = fixer__a_notFIFO_T_42 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_44 = fixer__a_notFIFO_T_43; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_40 | fixer__a_notFIFO_T_45; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_48 = fixer__a_notFIFO_T_46; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_49 = fixer__a_notFIFO_T_48; // @[Mux.scala:30:73] wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_49; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] fixer_a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire fixer_a_first_1 = fixer_a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_1 = fixer__a_first_last_T_2 | fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [7:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] fixer_d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_1 = fixer__d_first_last_T_2 | fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_7; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73] wire fixer__T_32 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33] reg [7:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35] wire [7:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36] wire [7:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38] wire [7:0] fixer__SourceIdSet_T_1 = 8'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1 : 8'h0; // @[OneHot.scala:58:35] wire [7:0] fixer__SourceIdClear_T_1 = 8'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_32 ? fixer__SourceIdClear_T_1 : 8'h0; // @[OneHot.scala:58:35] wire [7:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 | fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_51 = {1'h0, fixer__a_notFIFO_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_53 = fixer__a_notFIFO_T_52; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_54 = fixer__a_notFIFO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_55 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_56 = {1'h0, fixer__a_notFIFO_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_58 = fixer__a_notFIFO_T_57; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_59 = fixer__a_notFIFO_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_54 | fixer__a_notFIFO_T_59; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_61 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_62 = {1'h0, fixer__a_notFIFO_T_61}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_63 = fixer__a_notFIFO_T_62 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_64 = fixer__a_notFIFO_T_63; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_65 = fixer__a_notFIFO_T_64 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_66 = fixer_x1_anonIn_1_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_67 = {1'h0, fixer__a_notFIFO_T_66}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_68 = fixer__a_notFIFO_T_67 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_69 = fixer__a_notFIFO_T_68; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_70 = fixer__a_notFIFO_T_69 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_71 = fixer__a_notFIFO_T_65 | fixer__a_notFIFO_T_70; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_73 = fixer__a_notFIFO_T_71; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_74 = fixer__a_notFIFO_T_73; // @[Mux.scala:30:73] wire fixer_a_notFIFO_2 = fixer__a_notFIFO_T_74; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_2 = fixer_x1_anonIn_1_a_ready & fixer_x1_anonIn_1_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonIn_1_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_7 = fixer__a_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_8 = ~fixer__a_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] fixer_a_first_beats1_decode_2 = fixer__a_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_2 = fixer_x1_anonIn_1_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_2 = ~fixer__a_first_beats1_opdata_T_2; // @[Edges.scala:92:{28,37}] wire [7:0] fixer_a_first_beats1_2 = fixer_a_first_beats1_opdata_2 ? fixer_a_first_beats1_decode_2 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] fixer_a_first_counter_2; // @[Edges.scala:229:27] wire [8:0] fixer__a_first_counter1_T_2 = {1'h0, fixer_a_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] fixer_a_first_counter1_2 = fixer__a_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire fixer_a_first_2 = fixer_a_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_4 = fixer_a_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_5 = fixer_a_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_2 = fixer__a_first_last_T_4 | fixer__a_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_2 = fixer_a_first_last_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] fixer__a_first_count_T_2 = ~fixer_a_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] fixer_a_first_count_2 = fixer_a_first_beats1_2 & fixer__a_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] fixer__a_first_counter_T_2 = fixer_a_first_2 ? fixer_a_first_beats1_2 : fixer_a_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_4 = fixer_x1_anonOut_1_d_ready & fixer_x1_anonOut_1_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonOut_1_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_7 = fixer__d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_8 = ~fixer__d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] fixer_d_first_beats1_decode_2 = fixer__d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_2 = fixer_x1_anonOut_1_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [7:0] fixer_d_first_beats1_2 = fixer_d_first_beats1_opdata_2 ? fixer_d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] fixer_d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] fixer__d_first_counter1_T_2 = {1'h0, fixer_d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] fixer_d_first_counter1_2 = fixer__d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_2 = fixer_d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_4 = fixer_d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_5 = fixer_d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_2 = fixer__d_first_last_T_4 | fixer__d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_2 = fixer_d_first_last_2 & fixer__d_first_T_4; // @[Decoupled.scala:51:35] wire [7:0] fixer__d_first_count_T_2 = ~fixer_d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] fixer_d_first_count_2 = fixer_d_first_beats1_2 & fixer__d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] fixer__d_first_counter_T_2 = fixer_d_first_first_2 ? fixer_d_first_beats1_2 : fixer_d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_5 = fixer_x1_anonOut_1_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_2 = fixer_d_first_first_2 & fixer__d_first_T_5; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_2_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_2_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_2 = ~fixer_a_notFIFO_2; // @[Mux.scala:30:73] wire fixer__T_53 = fixer_x1_anonIn_1_d_ready & fixer_x1_anonIn_1_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_1_a_valid = fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_1_a_ready = fixer__anonIn_a_ready_T_8; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_2; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_2; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_2 = 4'h1 << fixer_x1_anonIn_1_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_2 = fixer_a_first_2 & fixer__a_first_T_2 & ~fixer_a_notFIFO_2 ? fixer__SourceIdSet_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_2 = 4'h1 << fixer_x1_anonIn_1_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_2 = fixer_d_first_2 & fixer__T_53 ? fixer__SourceIdClear_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_2 = fixer_SourceIdFIFOed_2 | fixer_SourceIdSet_2; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_2 = &fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35, :127:41] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_7_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_7_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_7_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_7_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_7_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_7_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_6_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_6_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_6_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_6_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_6_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_6_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_5_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_5_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_5_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_5_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_5_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_5_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_4_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_4_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_4_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_4_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_4_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_4_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_3_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_3_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_3_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_3_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_3_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_3_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_2_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_2_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_2_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_2_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_2_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_2_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_1_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_1_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_1_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_1_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_1_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_1_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_0_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_0_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_0_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_0_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_0_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_0_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_7_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_7_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_7_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_7_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_7_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_7_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_6_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_6_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_6_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_6_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_6_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_6_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_5_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_5_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_5_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_5_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_5_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_5_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_4_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_4_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_4_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_4_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_4_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_4_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_3_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_3_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_3_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_3_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_3_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_3_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_2_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_2_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_2_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_2_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_2_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_2_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_1_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_1_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_1_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_1_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_1_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_1_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_0_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_0_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_0_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_0_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_0_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_0_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_7_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_6_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_5_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_4_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_3_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_2_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_1_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_0_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_7_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_7_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_7_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_7_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_6_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_7_e_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_a_ready; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_6_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_7_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_6_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_6_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_6_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_6_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_5_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_6_e_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_a_ready; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_5_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_6_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_5_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_5_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_5_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_5_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_4_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_5_e_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_a_ready; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_4_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_5_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_4_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_4_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_4_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_4_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_3_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_4_e_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_a_ready; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_3_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_4_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_3_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_3_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_3_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_3_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_2_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_3_e_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_2_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_3_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_2_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_2_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_2_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_2_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_1_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_2_e_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_1_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_2_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_1_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_1_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_1_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_1_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonIn_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_1_e_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonIn_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_1_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_0_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_0_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_0_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_0_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_0_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_anonIn_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_0_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_7_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_7_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_7_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_7_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_6_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_7_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_6_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_7_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_7_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_6_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_6_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_6_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_6_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_5_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_6_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_5_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_6_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_6_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_5_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_5_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_5_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_5_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_4_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_5_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_4_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_5_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_5_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_4_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_4_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_4_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_4_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_3_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_4_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_3_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_4_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_4_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_3_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_3_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_3_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_3_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_2_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_3_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_2_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_3_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_3_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_2_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_2_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_2_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_2_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_1_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_2_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_1_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_2_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_2_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_1_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_1_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_1_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_1_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_x1_anonOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_1_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_1_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_1_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_0_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_0_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_0_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_address; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_0_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_0_e_valid; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_0_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_0_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonIn_a_ready = coupler_to_bus_named_coh_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_valid = coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_param = coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_size = coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_source = coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_address = coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_mask = coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_data = coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_b_ready = coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonIn_b_valid = coupler_to_bus_named_coh_widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_b_bits_param = coupler_to_bus_named_coh_widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_b_bits_address = coupler_to_bus_named_coh_widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_c_ready = coupler_to_bus_named_coh_widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_valid = coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_param = coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_size = coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_source = coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_address = coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_data = coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_d_ready = coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonIn_d_valid = coupler_to_bus_named_coh_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_param = coupler_to_bus_named_coh_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_size = coupler_to_bus_named_coh_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_source = coupler_to_bus_named_coh_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_sink = coupler_to_bus_named_coh_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_denied = coupler_to_bus_named_coh_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_data = coupler_to_bus_named_coh_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_e_valid = coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_0_e_bits_sink = coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_a_ready = coupler_to_bus_named_coh_widget_x1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_valid = coupler_to_bus_named_coh_widget_x1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_b_ready = coupler_to_bus_named_coh_widget_x1_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_b_valid = coupler_to_bus_named_coh_widget_x1_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_c_ready = coupler_to_bus_named_coh_widget_x1_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_valid = coupler_to_bus_named_coh_widget_x1_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_d_ready = coupler_to_bus_named_coh_widget_x1_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_valid = coupler_to_bus_named_coh_widget_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_e_valid = coupler_to_bus_named_coh_widget_x1_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_1_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_a_ready = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_valid = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_b_ready = coupler_to_bus_named_coh_widget_x1_anonOut_1_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_b_valid = coupler_to_bus_named_coh_widget_x1_anonOut_1_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_1_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_c_ready = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_valid = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_d_ready = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_valid = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_e_valid = coupler_to_bus_named_coh_widget_x1_anonOut_1_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_2_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_1_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_a_ready = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_valid = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_b_ready = coupler_to_bus_named_coh_widget_x1_anonOut_2_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_b_valid = coupler_to_bus_named_coh_widget_x1_anonOut_2_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_2_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_c_ready = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_valid = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_d_ready = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_valid = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_e_valid = coupler_to_bus_named_coh_widget_x1_anonOut_2_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_3_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_2_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_a_ready = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_valid = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_b_ready = coupler_to_bus_named_coh_widget_x1_anonOut_3_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_b_valid = coupler_to_bus_named_coh_widget_x1_anonOut_3_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_3_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_c_ready = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_valid = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_d_ready = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_valid = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_e_valid = coupler_to_bus_named_coh_widget_x1_anonOut_3_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_4_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_3_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_a_ready = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_valid = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_b_ready = coupler_to_bus_named_coh_widget_x1_anonOut_4_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_b_valid = coupler_to_bus_named_coh_widget_x1_anonOut_4_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_4_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_c_ready = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_valid = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_d_ready = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_valid = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_4_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_e_valid = coupler_to_bus_named_coh_widget_x1_anonOut_4_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_5_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_4_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_a_ready = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_valid = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_b_ready = coupler_to_bus_named_coh_widget_x1_anonOut_5_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_b_valid = coupler_to_bus_named_coh_widget_x1_anonOut_5_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_5_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_c_ready = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_valid = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_d_ready = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_valid = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_5_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_e_valid = coupler_to_bus_named_coh_widget_x1_anonOut_5_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_6_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_5_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_a_ready = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_valid = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_b_ready = coupler_to_bus_named_coh_widget_x1_anonOut_6_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_b_valid = coupler_to_bus_named_coh_widget_x1_anonOut_6_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_6_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_c_ready = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_valid = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_d_ready = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_valid = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonOut_6_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_e_valid = coupler_to_bus_named_coh_widget_x1_anonOut_6_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_7_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonOut_6_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_a_ready = coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonOut_a_valid = coupler_to_bus_named_coh_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_param = coupler_to_bus_named_coh_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_size = coupler_to_bus_named_coh_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_source = coupler_to_bus_named_coh_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_address = coupler_to_bus_named_coh_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_mask = coupler_to_bus_named_coh_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_data = coupler_to_bus_named_coh_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_b_ready = coupler_to_bus_named_coh_widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_b_valid = coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_param = coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_b_bits_address = coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_c_ready = coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonOut_c_valid = coupler_to_bus_named_coh_widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_param = coupler_to_bus_named_coh_widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_size = coupler_to_bus_named_coh_widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_source = coupler_to_bus_named_coh_widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_address = coupler_to_bus_named_coh_widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_data = coupler_to_bus_named_coh_widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_d_ready = coupler_to_bus_named_coh_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_valid = coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_param = coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_size = coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_source = coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_sink = coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_denied = coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_data = coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_0_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonOut_e_valid = coupler_to_bus_named_coh_widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_e_bits_sink = coupler_to_bus_named_coh_widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_a_ready = coupler_to_bus_named_coh_widget_x1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_valid = coupler_to_bus_named_coh_widget_x1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_b_ready = coupler_to_bus_named_coh_widget_x1_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_b_valid = coupler_to_bus_named_coh_widget_x1_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_c_ready = coupler_to_bus_named_coh_widget_x1_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_valid = coupler_to_bus_named_coh_widget_x1_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_d_ready = coupler_to_bus_named_coh_widget_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_valid = coupler_to_bus_named_coh_widget_x1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_1_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_e_valid = coupler_to_bus_named_coh_widget_x1_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_a_ready = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_valid = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_b_ready = coupler_to_bus_named_coh_widget_x1_anonIn_1_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_b_valid = coupler_to_bus_named_coh_widget_x1_anonIn_1_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_1_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_c_ready = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_valid = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_1_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_d_ready = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_valid = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_2_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_1_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_e_valid = coupler_to_bus_named_coh_widget_x1_anonIn_1_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_1_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_1_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_a_ready = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_valid = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_b_ready = coupler_to_bus_named_coh_widget_x1_anonIn_2_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_b_valid = coupler_to_bus_named_coh_widget_x1_anonIn_2_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_2_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_c_ready = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_valid = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_2_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_d_ready = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_valid = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_3_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_2_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_e_valid = coupler_to_bus_named_coh_widget_x1_anonIn_2_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_2_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_2_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_a_ready = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_valid = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_b_ready = coupler_to_bus_named_coh_widget_x1_anonIn_3_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_b_valid = coupler_to_bus_named_coh_widget_x1_anonIn_3_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_3_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_c_ready = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_valid = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_3_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_d_ready = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_valid = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_4_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_3_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_e_valid = coupler_to_bus_named_coh_widget_x1_anonIn_3_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_3_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_3_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_a_ready = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_valid = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_b_ready = coupler_to_bus_named_coh_widget_x1_anonIn_4_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_b_valid = coupler_to_bus_named_coh_widget_x1_anonIn_4_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_4_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_c_ready = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_valid = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_4_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_d_ready = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_valid = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_5_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_4_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_e_valid = coupler_to_bus_named_coh_widget_x1_anonIn_4_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_4_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_4_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_a_ready = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_valid = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_5_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_b_ready = coupler_to_bus_named_coh_widget_x1_anonIn_5_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_b_valid = coupler_to_bus_named_coh_widget_x1_anonIn_5_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_5_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_c_ready = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_valid = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_5_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_d_ready = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_valid = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_6_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_5_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_e_valid = coupler_to_bus_named_coh_widget_x1_anonIn_5_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_5_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_5_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_a_ready = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_valid = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_mask = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_a_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_6_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_b_ready = coupler_to_bus_named_coh_widget_x1_anonIn_6_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_b_valid = coupler_to_bus_named_coh_widget_x1_anonIn_6_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_b_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_6_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_c_ready = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_valid = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_address = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_c_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_6_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_d_ready = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_valid = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_opcode = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_param = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_size = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_source = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_denied = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_data = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_7_d_bits_corrupt = coupler_to_bus_named_coh_widget_x1_anonIn_6_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_e_valid = coupler_to_bus_named_coh_widget_x1_anonIn_6_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_x1_anonOut_6_e_bits_sink = coupler_to_bus_named_coh_widget_x1_anonIn_6_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_address; // @[MixedNode.scala:551:17] wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_b_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_mask; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlMasterClockXingIn_c_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_address; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_source; // @[ClockDomain.scala:14:9] wire [6:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlMasterClockXingIn_e_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_valid; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] wire [6:0] coupler_from_rockettile_x1_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_address; // @[MixedNode.scala:551:17] wire [15:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_size; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_source; // @[ClockDomain.scala:14:9] wire [6:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_denied; // @[ClockDomain.scala:14:9] wire [127:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_x1_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_1_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_valid = coupler_from_rockettile_auto_tl_out_1_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_x1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_opcode = coupler_from_rockettile_auto_tl_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_x1_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_param = coupler_from_rockettile_auto_tl_out_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_x1_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_size = coupler_from_rockettile_auto_tl_out_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_x1_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_source = coupler_from_rockettile_auto_tl_out_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_x1_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_address = coupler_from_rockettile_auto_tl_out_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] coupler_from_rockettile_x1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_mask = coupler_from_rockettile_auto_tl_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] coupler_from_rockettile_x1_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_data = coupler_from_rockettile_auto_tl_out_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_x1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_x1_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_b_ready = coupler_from_rockettile_auto_tl_out_1_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_x1_tlOut_b_valid = coupler_from_rockettile_auto_tl_out_1_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_x1_tlOut_b_bits_opcode = coupler_from_rockettile_auto_tl_out_1_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_x1_tlOut_b_bits_param = coupler_from_rockettile_auto_tl_out_1_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_x1_tlOut_b_bits_size = coupler_from_rockettile_auto_tl_out_1_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_x1_tlOut_b_bits_source = coupler_from_rockettile_auto_tl_out_1_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_x1_tlOut_b_bits_address = coupler_from_rockettile_auto_tl_out_1_b_bits_address; // @[MixedNode.scala:542:17] wire [15:0] coupler_from_rockettile_x1_tlOut_b_bits_mask = coupler_from_rockettile_auto_tl_out_1_b_bits_mask; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlOut_c_ready = coupler_from_rockettile_auto_tl_out_1_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_valid = coupler_from_rockettile_auto_tl_out_1_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_x1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_opcode = coupler_from_rockettile_auto_tl_out_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_x1_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_param = coupler_from_rockettile_auto_tl_out_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_x1_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_size = coupler_from_rockettile_auto_tl_out_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_x1_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_source = coupler_from_rockettile_auto_tl_out_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_x1_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_address = coupler_from_rockettile_auto_tl_out_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [127:0] coupler_from_rockettile_x1_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_data = coupler_from_rockettile_auto_tl_out_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_x1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_corrupt = coupler_from_rockettile_auto_tl_out_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_x1_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_d_ready = coupler_from_rockettile_auto_tl_out_1_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_x1_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_1_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_x1_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_1_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_x1_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_1_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_x1_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_1_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_x1_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_1_d_bits_source; // @[MixedNode.scala:542:17] wire [6:0] coupler_from_rockettile_x1_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_1_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_1_d_bits_denied; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_x1_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_1_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_1_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlOut_e_ready = coupler_from_rockettile_auto_tl_out_1_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_e_valid = coupler_from_rockettile_auto_tl_out_1_e_valid; // @[FIFOFixer.scala:50:9] wire [6:0] coupler_from_rockettile_x1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_e_bits_sink = coupler_from_rockettile_auto_tl_out_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_0_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_valid = coupler_from_rockettile_auto_tl_out_0_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_rockettile_auto_tl_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_param = coupler_from_rockettile_auto_tl_out_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_size = coupler_from_rockettile_auto_tl_out_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_source = coupler_from_rockettile_auto_tl_out_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_address = coupler_from_rockettile_auto_tl_out_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [15:0] coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_rockettile_auto_tl_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [127:0] coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_data = coupler_from_rockettile_auto_tl_out_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_d_ready = coupler_from_rockettile_auto_tl_out_0_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_0_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_0_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_0_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_0_d_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_0_d_bits_source; // @[MixedNode.scala:542:17] wire [6:0] coupler_from_rockettile_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_0_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_0_d_bits_denied; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_0_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_0_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_a_ready = coupler_from_rockettile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_valid = coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_opcode = coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_param = coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_size = coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_source = coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_address = coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_mask = coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_data = coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_a_bits_corrupt = coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_0_d_ready = coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_d_valid = coupler_from_rockettile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_d_bits_opcode = coupler_from_rockettile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_d_bits_param = coupler_from_rockettile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlIn_d_bits_size = coupler_from_rockettile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_d_bits_source = coupler_from_rockettile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_tlIn_d_bits_sink = coupler_from_rockettile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_d_bits_denied = coupler_from_rockettile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_tlIn_d_bits_data = coupler_from_rockettile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_d_bits_corrupt = coupler_from_rockettile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_a_ready = coupler_from_rockettile_x1_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_valid = coupler_from_rockettile_x1_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_x1_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_opcode = coupler_from_rockettile_x1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_x1_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_param = coupler_from_rockettile_x1_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_x1_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_size = coupler_from_rockettile_x1_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_x1_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_source = coupler_from_rockettile_x1_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_x1_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_address = coupler_from_rockettile_x1_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] coupler_from_rockettile_x1_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_mask = coupler_from_rockettile_x1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_x1_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_data = coupler_from_rockettile_x1_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_a_bits_corrupt = coupler_from_rockettile_x1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_b_ready = coupler_from_rockettile_x1_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlIn_b_valid = coupler_from_rockettile_x1_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlIn_b_bits_opcode = coupler_from_rockettile_x1_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlIn_b_bits_param = coupler_from_rockettile_x1_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_tlIn_b_bits_size = coupler_from_rockettile_x1_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlIn_b_bits_source = coupler_from_rockettile_x1_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_tlIn_b_bits_address = coupler_from_rockettile_x1_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_x1_tlIn_b_bits_mask = coupler_from_rockettile_x1_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_c_ready = coupler_from_rockettile_x1_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_valid = coupler_from_rockettile_x1_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_x1_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_bits_opcode = coupler_from_rockettile_x1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_x1_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_bits_param = coupler_from_rockettile_x1_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_x1_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_bits_size = coupler_from_rockettile_x1_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_x1_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_bits_source = coupler_from_rockettile_x1_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_x1_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_bits_address = coupler_from_rockettile_x1_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] coupler_from_rockettile_x1_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_bits_data = coupler_from_rockettile_x1_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_c_bits_corrupt = coupler_from_rockettile_x1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_d_ready = coupler_from_rockettile_x1_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_x1_tlIn_d_valid = coupler_from_rockettile_x1_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlIn_d_bits_opcode = coupler_from_rockettile_x1_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlIn_d_bits_param = coupler_from_rockettile_x1_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_tlIn_d_bits_size = coupler_from_rockettile_x1_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlIn_d_bits_source = coupler_from_rockettile_x1_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_x1_tlIn_d_bits_sink = coupler_from_rockettile_x1_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_d_bits_denied = coupler_from_rockettile_x1_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_tlIn_d_bits_data = coupler_from_rockettile_x1_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_d_bits_corrupt = coupler_from_rockettile_x1_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_e_ready = coupler_from_rockettile_x1_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_e_valid = coupler_from_rockettile_x1_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [6:0] coupler_from_rockettile_x1_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_1_e_bits_sink = coupler_from_rockettile_x1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_no_bufferOut_a_ready = coupler_from_rockettile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_valid = coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_opcode = coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_param = coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_size = coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_source = coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_address = coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_mask = coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_data = coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_corrupt = coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_d_ready = coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_valid = coupler_from_rockettile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_opcode = coupler_from_rockettile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_param = coupler_from_rockettile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_d_bits_size = coupler_from_rockettile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_source = coupler_from_rockettile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_no_bufferOut_d_bits_sink = coupler_from_rockettile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_bits_denied = coupler_from_rockettile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_no_bufferOut_d_bits_data = coupler_from_rockettile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_a_ready = coupler_from_rockettile_x1_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_valid = coupler_from_rockettile_x1_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_opcode = coupler_from_rockettile_x1_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_param = coupler_from_rockettile_x1_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_size = coupler_from_rockettile_x1_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_source = coupler_from_rockettile_x1_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_address = coupler_from_rockettile_x1_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_mask = coupler_from_rockettile_x1_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_data = coupler_from_rockettile_x1_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_a_bits_corrupt = coupler_from_rockettile_x1_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_b_ready = coupler_from_rockettile_x1_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_b_valid = coupler_from_rockettile_x1_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_opcode = coupler_from_rockettile_x1_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_param = coupler_from_rockettile_x1_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_size = coupler_from_rockettile_x1_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_source = coupler_from_rockettile_x1_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_address = coupler_from_rockettile_x1_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_mask = coupler_from_rockettile_x1_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_c_ready = coupler_from_rockettile_x1_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_valid = coupler_from_rockettile_x1_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_bits_opcode = coupler_from_rockettile_x1_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_bits_param = coupler_from_rockettile_x1_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_bits_size = coupler_from_rockettile_x1_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_bits_source = coupler_from_rockettile_x1_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_bits_address = coupler_from_rockettile_x1_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_bits_data = coupler_from_rockettile_x1_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_c_bits_corrupt = coupler_from_rockettile_x1_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_d_ready = coupler_from_rockettile_x1_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_d_valid = coupler_from_rockettile_x1_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_opcode = coupler_from_rockettile_x1_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_param = coupler_from_rockettile_x1_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_size = coupler_from_rockettile_x1_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_source = coupler_from_rockettile_x1_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_sink = coupler_from_rockettile_x1_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_d_bits_denied = coupler_from_rockettile_x1_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_data = coupler_from_rockettile_x1_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_x1_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_e_ready = coupler_from_rockettile_x1_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_e_valid = coupler_from_rockettile_x1_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_x1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_tlOut_e_bits_sink = coupler_from_rockettile_x1_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_ready = coupler_from_rockettile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_valid = coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_opcode = coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_param = coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_size = coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_source = coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_address = coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_mask = coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_data = coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_corrupt = coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_d_ready = coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_valid = coupler_from_rockettile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_opcode = coupler_from_rockettile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_param = coupler_from_rockettile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_d_bits_size = coupler_from_rockettile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_source = coupler_from_rockettile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_no_bufferIn_d_bits_sink = coupler_from_rockettile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_bits_denied = coupler_from_rockettile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_no_bufferIn_d_bits_data = coupler_from_rockettile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_a_ready = coupler_from_rockettile_x1_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_valid = coupler_from_rockettile_x1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_opcode = coupler_from_rockettile_x1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_param = coupler_from_rockettile_x1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_size = coupler_from_rockettile_x1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_source = coupler_from_rockettile_x1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_address = coupler_from_rockettile_x1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_mask = coupler_from_rockettile_x1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_data = coupler_from_rockettile_x1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_a_bits_corrupt = coupler_from_rockettile_x1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_b_ready = coupler_from_rockettile_x1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_b_valid = coupler_from_rockettile_x1_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_opcode = coupler_from_rockettile_x1_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_param = coupler_from_rockettile_x1_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_size = coupler_from_rockettile_x1_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_source = coupler_from_rockettile_x1_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_address = coupler_from_rockettile_x1_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_mask = coupler_from_rockettile_x1_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_c_ready = coupler_from_rockettile_x1_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_valid = coupler_from_rockettile_x1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_bits_opcode = coupler_from_rockettile_x1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_bits_param = coupler_from_rockettile_x1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_bits_size = coupler_from_rockettile_x1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_bits_source = coupler_from_rockettile_x1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_bits_address = coupler_from_rockettile_x1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_bits_data = coupler_from_rockettile_x1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_c_bits_corrupt = coupler_from_rockettile_x1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_d_ready = coupler_from_rockettile_x1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_d_valid = coupler_from_rockettile_x1_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_opcode = coupler_from_rockettile_x1_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_param = coupler_from_rockettile_x1_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_size = coupler_from_rockettile_x1_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_source = coupler_from_rockettile_x1_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_sink = coupler_from_rockettile_x1_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_d_bits_denied = coupler_from_rockettile_x1_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_data = coupler_from_rockettile_x1_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_x1_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_e_ready = coupler_from_rockettile_x1_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_e_valid = coupler_from_rockettile_x1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_x1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlIn_e_bits_sink = coupler_from_rockettile_x1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_ready = coupler_from_rockettile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_valid = coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_opcode = coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_param = coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_size = coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_source = coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_address = coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_mask = coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_data = coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_d_ready = coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_valid = coupler_from_rockettile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_a_ready = coupler_from_rockettile_x1_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_valid = coupler_from_rockettile_x1_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_opcode = coupler_from_rockettile_x1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_param = coupler_from_rockettile_x1_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_size = coupler_from_rockettile_x1_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_source = coupler_from_rockettile_x1_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_address = coupler_from_rockettile_x1_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_mask = coupler_from_rockettile_x1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_data = coupler_from_rockettile_x1_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_x1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_b_ready = coupler_from_rockettile_x1_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_b_valid = coupler_from_rockettile_x1_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_x1_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_x1_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_x1_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_x1_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_x1_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_x1_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_c_ready = coupler_from_rockettile_x1_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_valid = coupler_from_rockettile_x1_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_bits_opcode = coupler_from_rockettile_x1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_bits_param = coupler_from_rockettile_x1_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_bits_size = coupler_from_rockettile_x1_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_bits_source = coupler_from_rockettile_x1_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_bits_address = coupler_from_rockettile_x1_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_bits_data = coupler_from_rockettile_x1_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_x1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_d_ready = coupler_from_rockettile_x1_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_valid = coupler_from_rockettile_x1_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_x1_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_x1_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_x1_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_x1_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_x1_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_x1_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_x1_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_x1_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_e_ready = coupler_from_rockettile_x1_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_x1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_e_valid = coupler_from_rockettile_x1_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [6:0] coupler_from_rockettile_x1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_x1_no_bufferOut_e_bits_sink = coupler_from_rockettile_x1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_a_ready = coupler_from_rockettile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_valid = coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_param = coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_size = coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_source = coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_address = coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_data = coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_d_ready = coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_valid = coupler_from_rockettile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_a_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_size = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_source = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_address = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_mask = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_data = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_b_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_c_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_bits_size = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_bits_source = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_bits_address = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_bits_data = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_d_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingIn_e_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_e_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_no_bufferIn_e_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_ready = coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_valid = coupler_from_rockettile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_d_ready = coupler_from_rockettile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_valid = coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_param = coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_size = coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_source = coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_denied = coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_data = coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_b_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_size = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_source = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_address = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_mask = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_d_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_size = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_source = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_denied = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_data = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_e_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_x1_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] wire fixer__T_31 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire fixer__T_33 = fixer_d_first_1 & fixer__T_32; // @[Decoupled.scala:51:35] wire fixer__T_52 = fixer_a_first_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35] wire fixer__T_54 = fixer_d_first_2 & fixer__T_53; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 8'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 8'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 17'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_1 <= 8'h0; // @[Edges.scala:229:27] fixer_d_first_counter_1 <= 8'h0; // @[Edges.scala:229:27] fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_1 <= 8'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_2 <= 8'h0; // @[Edges.scala:229:27] fixer_d_first_counter_2 <= 8'h0; // @[Edges.scala:229:27] fixer_flight_2_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_2 <= 3'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h3 ? fixer__flight_T : fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h4 ? fixer__flight_T : fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h5 ? fixer__flight_T : fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h6 ? fixer__flight_T : fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h7 ? fixer__flight_T : fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h8 ? fixer__flight_T : fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h9 ? fixer__flight_T : fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hA ? fixer__flight_T : fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hB ? fixer__flight_T : fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hC ? fixer__flight_T : fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hD ? fixer__flight_T : fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hE ? fixer__flight_T : fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hF ? fixer__flight_T : fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h10 ? fixer__flight_T : fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_1) // @[Decoupled.scala:51:35] fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_2) // @[Decoupled.scala:51:35] fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21] fixer_flight_1_0 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 3'h0) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 3'h0 ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_1 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 3'h1) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 3'h1 ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_2 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 3'h2) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 3'h2 ? fixer__flight_T_1 : fixer_flight_1_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_3 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 3'h3) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 3'h3 ? fixer__flight_T_1 : fixer_flight_1_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_4 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 3'h4) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 3'h4 ? fixer__flight_T_1 : fixer_flight_1_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_5 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 3'h5) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 3'h5 ? fixer__flight_T_1 : fixer_flight_1_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_6 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 3'h6) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 3'h6 ? fixer__flight_T_1 : fixer_flight_1_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_7 <= ~(fixer__T_33 & (&fixer_x1_anonIn_d_bits_source)) & (fixer__T_31 & (&fixer_x1_anonIn_a_bits_source) ? fixer__flight_T_1 : fixer_flight_1_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_2) // @[Decoupled.scala:51:35] fixer_a_first_counter_2 <= fixer__a_first_counter_T_2; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_4) // @[Decoupled.scala:51:35] fixer_d_first_counter_2 <= fixer__d_first_counter_T_2; // @[Edges.scala:229:27, :236:21] fixer_flight_2_0 <= ~(fixer__T_54 & fixer_x1_anonIn_1_d_bits_source == 2'h0) & (fixer__T_52 & fixer_x1_anonIn_1_a_bits_source == 2'h0 ? fixer__flight_T_2 : fixer_flight_2_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2_1 <= ~(fixer__T_54 & fixer_x1_anonIn_1_d_bits_source == 2'h1) & (fixer__T_52 & fixer_x1_anonIn_1_a_bits_source == 2'h1 ? fixer__flight_T_2 : fixer_flight_2_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2_2 <= ~(fixer__T_54 & fixer_x1_anonIn_1_d_bits_source == 2'h2) & (fixer__T_52 & fixer_x1_anonIn_1_a_bits_source == 2'h2 ? fixer__flight_T_2 : fixer_flight_2_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_2 <= fixer__SourceIdFIFOed_T_2; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) FixedClockBroadcast_4 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_sbus_i3_o9_a32d128s6k7z4c system_bus_xbar ( // @[SystemBus.scala:47:43] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_2_a_ready (fixer_auto_anon_out_2_a_ready), .auto_anon_in_2_a_valid (fixer_auto_anon_out_2_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_opcode (fixer_auto_anon_out_2_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_param (fixer_auto_anon_out_2_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_size (fixer_auto_anon_out_2_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_source (fixer_auto_anon_out_2_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_address (fixer_auto_anon_out_2_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_mask (fixer_auto_anon_out_2_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_data (fixer_auto_anon_out_2_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_corrupt (fixer_auto_anon_out_2_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_b_ready (fixer_auto_anon_out_2_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_b_valid (fixer_auto_anon_out_2_b_valid), .auto_anon_in_2_b_bits_opcode (fixer_auto_anon_out_2_b_bits_opcode), .auto_anon_in_2_b_bits_param (fixer_auto_anon_out_2_b_bits_param), .auto_anon_in_2_b_bits_size (fixer_auto_anon_out_2_b_bits_size), .auto_anon_in_2_b_bits_source (fixer_auto_anon_out_2_b_bits_source), .auto_anon_in_2_b_bits_address (fixer_auto_anon_out_2_b_bits_address), .auto_anon_in_2_b_bits_mask (fixer_auto_anon_out_2_b_bits_mask), .auto_anon_in_2_c_ready (fixer_auto_anon_out_2_c_ready), .auto_anon_in_2_c_valid (fixer_auto_anon_out_2_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_opcode (fixer_auto_anon_out_2_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_param (fixer_auto_anon_out_2_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_size (fixer_auto_anon_out_2_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_source (fixer_auto_anon_out_2_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_address (fixer_auto_anon_out_2_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_data (fixer_auto_anon_out_2_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_corrupt (fixer_auto_anon_out_2_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_d_ready (fixer_auto_anon_out_2_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_d_valid (fixer_auto_anon_out_2_d_valid), .auto_anon_in_2_d_bits_opcode (fixer_auto_anon_out_2_d_bits_opcode), .auto_anon_in_2_d_bits_param (fixer_auto_anon_out_2_d_bits_param), .auto_anon_in_2_d_bits_size (fixer_auto_anon_out_2_d_bits_size), .auto_anon_in_2_d_bits_source (fixer_auto_anon_out_2_d_bits_source), .auto_anon_in_2_d_bits_sink (fixer_auto_anon_out_2_d_bits_sink), .auto_anon_in_2_d_bits_denied (fixer_auto_anon_out_2_d_bits_denied), .auto_anon_in_2_d_bits_data (fixer_auto_anon_out_2_d_bits_data), .auto_anon_in_2_d_bits_corrupt (fixer_auto_anon_out_2_d_bits_corrupt), .auto_anon_in_2_e_ready (fixer_auto_anon_out_2_e_ready), .auto_anon_in_2_e_valid (fixer_auto_anon_out_2_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_e_bits_sink (fixer_auto_anon_out_2_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready), .auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid), .auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param), .auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size), .auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source), .auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied), .auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt), .auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready), .auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid), .auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param), .auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size), .auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source), .auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied), .auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt), .auto_anon_out_8_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_valid), .auto_anon_out_8_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_opcode), .auto_anon_out_8_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_param), .auto_anon_out_8_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_size), .auto_anon_out_8_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_source), .auto_anon_out_8_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_address), .auto_anon_out_8_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_mask), .auto_anon_out_8_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_data), .auto_anon_out_8_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_7_a_bits_corrupt), .auto_anon_out_8_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_7_b_ready), .auto_anon_out_8_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_7_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_7_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_valid), .auto_anon_out_8_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_opcode), .auto_anon_out_8_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_param), .auto_anon_out_8_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_size), .auto_anon_out_8_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_source), .auto_anon_out_8_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_address), .auto_anon_out_8_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_data), .auto_anon_out_8_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_7_c_bits_corrupt), .auto_anon_out_8_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_ready), .auto_anon_out_8_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_7_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_8_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_7_e_valid), .auto_anon_out_8_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_7_e_bits_sink), .auto_anon_out_7_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_valid), .auto_anon_out_7_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_opcode), .auto_anon_out_7_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_param), .auto_anon_out_7_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_size), .auto_anon_out_7_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_source), .auto_anon_out_7_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_address), .auto_anon_out_7_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_mask), .auto_anon_out_7_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_data), .auto_anon_out_7_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_6_a_bits_corrupt), .auto_anon_out_7_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_6_b_ready), .auto_anon_out_7_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_6_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_6_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_valid), .auto_anon_out_7_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_opcode), .auto_anon_out_7_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_param), .auto_anon_out_7_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_size), .auto_anon_out_7_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_source), .auto_anon_out_7_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_address), .auto_anon_out_7_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_data), .auto_anon_out_7_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_6_c_bits_corrupt), .auto_anon_out_7_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_ready), .auto_anon_out_7_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_6_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_7_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_6_e_valid), .auto_anon_out_7_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_6_e_bits_sink), .auto_anon_out_6_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_valid), .auto_anon_out_6_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_opcode), .auto_anon_out_6_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_param), .auto_anon_out_6_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_size), .auto_anon_out_6_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_source), .auto_anon_out_6_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_address), .auto_anon_out_6_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_mask), .auto_anon_out_6_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_data), .auto_anon_out_6_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_5_a_bits_corrupt), .auto_anon_out_6_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_5_b_ready), .auto_anon_out_6_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_5_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_5_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_valid), .auto_anon_out_6_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_opcode), .auto_anon_out_6_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_param), .auto_anon_out_6_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_size), .auto_anon_out_6_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_source), .auto_anon_out_6_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_address), .auto_anon_out_6_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_data), .auto_anon_out_6_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_5_c_bits_corrupt), .auto_anon_out_6_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_ready), .auto_anon_out_6_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_5_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_6_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_5_e_valid), .auto_anon_out_6_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_5_e_bits_sink), .auto_anon_out_5_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_valid), .auto_anon_out_5_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_opcode), .auto_anon_out_5_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_param), .auto_anon_out_5_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_size), .auto_anon_out_5_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_source), .auto_anon_out_5_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_address), .auto_anon_out_5_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_mask), .auto_anon_out_5_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_data), .auto_anon_out_5_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_4_a_bits_corrupt), .auto_anon_out_5_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_4_b_ready), .auto_anon_out_5_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_4_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_4_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_valid), .auto_anon_out_5_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_opcode), .auto_anon_out_5_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_param), .auto_anon_out_5_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_size), .auto_anon_out_5_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_source), .auto_anon_out_5_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_address), .auto_anon_out_5_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_data), .auto_anon_out_5_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_4_c_bits_corrupt), .auto_anon_out_5_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_ready), .auto_anon_out_5_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_4_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_5_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_4_e_valid), .auto_anon_out_5_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_4_e_bits_sink), .auto_anon_out_4_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_valid), .auto_anon_out_4_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_opcode), .auto_anon_out_4_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_param), .auto_anon_out_4_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_size), .auto_anon_out_4_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_source), .auto_anon_out_4_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_address), .auto_anon_out_4_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_mask), .auto_anon_out_4_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_data), .auto_anon_out_4_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_3_a_bits_corrupt), .auto_anon_out_4_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_3_b_ready), .auto_anon_out_4_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_3_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_3_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_valid), .auto_anon_out_4_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_opcode), .auto_anon_out_4_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_param), .auto_anon_out_4_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_size), .auto_anon_out_4_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_source), .auto_anon_out_4_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_address), .auto_anon_out_4_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_data), .auto_anon_out_4_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_3_c_bits_corrupt), .auto_anon_out_4_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_ready), .auto_anon_out_4_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_3_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_4_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_3_e_valid), .auto_anon_out_4_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_3_e_bits_sink), .auto_anon_out_3_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_valid), .auto_anon_out_3_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_opcode), .auto_anon_out_3_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_param), .auto_anon_out_3_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_size), .auto_anon_out_3_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_source), .auto_anon_out_3_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_address), .auto_anon_out_3_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_mask), .auto_anon_out_3_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_data), .auto_anon_out_3_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_2_a_bits_corrupt), .auto_anon_out_3_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_2_b_ready), .auto_anon_out_3_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_2_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_2_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_valid), .auto_anon_out_3_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_opcode), .auto_anon_out_3_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_param), .auto_anon_out_3_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_size), .auto_anon_out_3_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_source), .auto_anon_out_3_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_address), .auto_anon_out_3_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_data), .auto_anon_out_3_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_2_c_bits_corrupt), .auto_anon_out_3_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_ready), .auto_anon_out_3_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_2_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_3_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_2_e_valid), .auto_anon_out_3_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_2_e_bits_sink), .auto_anon_out_2_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_valid), .auto_anon_out_2_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_opcode), .auto_anon_out_2_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_param), .auto_anon_out_2_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_size), .auto_anon_out_2_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_source), .auto_anon_out_2_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_address), .auto_anon_out_2_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_mask), .auto_anon_out_2_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_data), .auto_anon_out_2_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_1_a_bits_corrupt), .auto_anon_out_2_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_1_b_ready), .auto_anon_out_2_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_1_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_1_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_valid), .auto_anon_out_2_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_opcode), .auto_anon_out_2_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_param), .auto_anon_out_2_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_size), .auto_anon_out_2_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_source), .auto_anon_out_2_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_address), .auto_anon_out_2_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_data), .auto_anon_out_2_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_1_c_bits_corrupt), .auto_anon_out_2_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_ready), .auto_anon_out_2_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_1_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_1_e_valid), .auto_anon_out_2_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_1_e_bits_sink), .auto_anon_out_1_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_valid), .auto_anon_out_1_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_opcode), .auto_anon_out_1_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_param), .auto_anon_out_1_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_size), .auto_anon_out_1_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_source), .auto_anon_out_1_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_address), .auto_anon_out_1_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_mask), .auto_anon_out_1_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_data), .auto_anon_out_1_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_0_a_bits_corrupt), .auto_anon_out_1_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_0_b_ready), .auto_anon_out_1_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_0_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_0_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_valid), .auto_anon_out_1_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_opcode), .auto_anon_out_1_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_param), .auto_anon_out_1_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_size), .auto_anon_out_1_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_source), .auto_anon_out_1_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_address), .auto_anon_out_1_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_data), .auto_anon_out_1_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_0_c_bits_corrupt), .auto_anon_out_1_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_ready), .auto_anon_out_1_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_0_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_0_e_valid), .auto_anon_out_1_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_0_e_bits_sink), .auto_anon_out_0_a_ready (_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_system_bus_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_system_bus_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_system_bus_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_system_bus_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_system_bus_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_system_bus_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_system_bus_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_system_bus_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_system_bus_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_system_bus_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_param (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_sink (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_denied (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_corrupt (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[SystemBus.scala:47:43] TLInterconnectCoupler_sbus_to_bus_named_cbus coupler_to_bus_named_cbus ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_widget_anon_in_a_ready (_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (_system_bus_xbar_auto_anon_out_0_a_valid), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_opcode (_system_bus_xbar_auto_anon_out_0_a_bits_opcode), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_param (_system_bus_xbar_auto_anon_out_0_a_bits_param), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_size (_system_bus_xbar_auto_anon_out_0_a_bits_size), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_source (_system_bus_xbar_auto_anon_out_0_a_bits_source), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_address (_system_bus_xbar_auto_anon_out_0_a_bits_address), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_mask (_system_bus_xbar_auto_anon_out_0_a_bits_mask), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_data (_system_bus_xbar_auto_anon_out_0_a_bits_data), // @[SystemBus.scala:47:43] .auto_widget_anon_in_a_bits_corrupt (_system_bus_xbar_auto_anon_out_0_a_bits_corrupt), // @[SystemBus.scala:47:43] .auto_widget_anon_in_d_ready (_system_bus_xbar_auto_anon_out_0_d_ready), // @[SystemBus.scala:47:43] .auto_widget_anon_in_d_valid (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_param (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param), .auto_widget_anon_in_d_bits_size (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_source (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source), .auto_widget_anon_in_d_bits_sink (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink), .auto_widget_anon_in_d_bits_denied (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt), .auto_bus_xing_out_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0), .auto_bus_xing_out_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0), .auto_bus_xing_out_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0), .auto_bus_xing_out_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0), .auto_bus_xing_out_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0), .auto_bus_xing_out_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0), .auto_bus_xing_out_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0), .auto_bus_xing_out_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0), .auto_bus_xing_out_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0), .auto_bus_xing_out_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0), .auto_bus_xing_out_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_out_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0) // @[ClockDomain.scala:14:9] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_sbus_from_bus_named_fbus coupler_from_bus_named_fbus ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_widget_anon_out_a_ready (fixer_auto_anon_in_0_a_ready), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_a_valid (fixer_auto_anon_in_0_a_valid), .auto_widget_anon_out_a_bits_opcode (fixer_auto_anon_in_0_a_bits_opcode), .auto_widget_anon_out_a_bits_param (fixer_auto_anon_in_0_a_bits_param), .auto_widget_anon_out_a_bits_size (fixer_auto_anon_in_0_a_bits_size), .auto_widget_anon_out_a_bits_source (fixer_auto_anon_in_0_a_bits_source), .auto_widget_anon_out_a_bits_address (fixer_auto_anon_in_0_a_bits_address), .auto_widget_anon_out_a_bits_mask (fixer_auto_anon_in_0_a_bits_mask), .auto_widget_anon_out_a_bits_data (fixer_auto_anon_in_0_a_bits_data), .auto_widget_anon_out_a_bits_corrupt (fixer_auto_anon_in_0_a_bits_corrupt), .auto_widget_anon_out_d_ready (fixer_auto_anon_in_0_d_ready), .auto_widget_anon_out_d_valid (fixer_auto_anon_in_0_d_valid), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_opcode (fixer_auto_anon_in_0_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_param (fixer_auto_anon_in_0_d_bits_param), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_size (fixer_auto_anon_in_0_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_source (fixer_auto_anon_in_0_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_sink (fixer_auto_anon_in_0_d_bits_sink), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_denied (fixer_auto_anon_in_0_d_bits_denied), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_data (fixer_auto_anon_in_0_d_bits_data), // @[FIFOFixer.scala:50:9] .auto_widget_anon_out_d_bits_corrupt (fixer_auto_anon_in_0_d_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_bus_xing_in_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0), .auto_bus_xing_in_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_bus_xing_in_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0), .auto_bus_xing_in_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0), .auto_bus_xing_in_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0), .auto_bus_xing_in_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0), .auto_bus_xing_in_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0), .auto_bus_xing_in_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0), .auto_bus_xing_in_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0), .auto_bus_xing_in_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0), .auto_bus_xing_in_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0) ); // @[LazyScope.scala:98:27] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_7_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_7_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_7_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_7_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_7_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_7_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_7_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_6_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_6_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_6_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_6_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_6_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_6_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_6_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_5_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_5_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_5_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_5_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_5_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_5_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_5_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_4_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_4_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_4_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_4_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_4_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_4_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_4_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_79 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_79( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_12 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_19 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_12( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_19 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_12 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_12 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_12( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_12 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<14>(0h2000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<18>(0h2f000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<17>(0h10000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<13>(0h1000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<27>(0h4000000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = or(_T_165, _T_170) node _T_202 = or(_T_201, _T_175) node _T_203 = or(_T_202, _T_180) node _T_204 = or(_T_203, _T_185) node _T_205 = or(_T_204, _T_190) node _T_206 = or(_T_205, _T_195) node _T_207 = or(_T_206, _T_200) node _T_208 = and(_T_160, _T_207) node _T_209 = or(UInt<1>(0h0), _T_208) node _T_210 = and(_T_159, _T_209) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_210, UInt<1>(0h1), "") : assert_2 node _T_214 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_215 = shr(io.in.a.bits.source, 2) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = leq(UInt<1>(0h0), uncommonBits_10) node _T_218 = and(_T_216, _T_217) node _T_219 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_220 = and(_T_218, _T_219) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_221 = shr(io.in.a.bits.source, 2) node _T_222 = eq(_T_221, UInt<1>(0h1)) node _T_223 = leq(UInt<1>(0h0), uncommonBits_11) node _T_224 = and(_T_222, _T_223) node _T_225 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_226 = and(_T_224, _T_225) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_227 = shr(io.in.a.bits.source, 2) node _T_228 = eq(_T_227, UInt<2>(0h2)) node _T_229 = leq(UInt<1>(0h0), uncommonBits_12) node _T_230 = and(_T_228, _T_229) node _T_231 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<2>(0h3)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_13) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_239 = shr(io.in.a.bits.source, 3) node _T_240 = eq(_T_239, UInt<3>(0h4)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_14) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_247 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_214 connect _WIRE[1], _T_220 connect _WIRE[2], _T_226 connect _WIRE[3], _T_232 connect _WIRE[4], _T_238 connect _WIRE[5], _T_244 connect _WIRE[6], _T_245 connect _WIRE[7], _T_246 connect _WIRE[8], _T_247 node _T_248 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_249 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_250 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_252 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[5], _T_248, UInt<1>(0h0)) node _T_255 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_256 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_258 = or(_T_249, _T_250) node _T_259 = or(_T_258, _T_251) node _T_260 = or(_T_259, _T_252) node _T_261 = or(_T_260, _T_253) node _T_262 = or(_T_261, _T_254) node _T_263 = or(_T_262, _T_255) node _T_264 = or(_T_263, _T_256) node _T_265 = or(_T_264, _T_257) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_265 node _T_266 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_267 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_268 = and(_T_266, _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_271 = cvt(_T_270) node _T_272 = and(_T_271, asSInt(UInt<14>(0h2000))) node _T_273 = asSInt(_T_272) node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0))) node _T_275 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_276 = cvt(_T_275) node _T_277 = and(_T_276, asSInt(UInt<13>(0h1000))) node _T_278 = asSInt(_T_277) node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0))) node _T_280 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<18>(0h2f000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<17>(0h10000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_296 = cvt(_T_295) node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) node _T_298 = asSInt(_T_297) node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_306 = cvt(_T_305) node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000))) node _T_308 = asSInt(_T_307) node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) node _T_310 = or(_T_274, _T_279) node _T_311 = or(_T_310, _T_284) node _T_312 = or(_T_311, _T_289) node _T_313 = or(_T_312, _T_294) node _T_314 = or(_T_313, _T_299) node _T_315 = or(_T_314, _T_304) node _T_316 = or(_T_315, _T_309) node _T_317 = and(_T_269, _T_316) node _T_318 = or(UInt<1>(0h0), _T_317) node _T_319 = and(_WIRE_1, _T_318) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_319, UInt<1>(0h1), "") : assert_3 node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(source_ok, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_326 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_326, UInt<1>(0h1), "") : assert_5 node _T_330 = asUInt(reset) node _T_331 = eq(_T_330, UInt<1>(0h0)) when _T_331 : node _T_332 = eq(is_aligned, UInt<1>(0h0)) when _T_332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_333 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : node _T_336 = eq(_T_333, UInt<1>(0h0)) when _T_336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_333, UInt<1>(0h1), "") : assert_7 node _T_337 = not(io.in.a.bits.mask) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_338, UInt<1>(0h1), "") : assert_8 node _T_342 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_342, UInt<1>(0h1), "") : assert_9 node _T_346 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_346 : node _T_347 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_348 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_351 = shr(io.in.a.bits.source, 2) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_15) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_356 = and(_T_354, _T_355) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_357 = shr(io.in.a.bits.source, 2) node _T_358 = eq(_T_357, UInt<1>(0h1)) node _T_359 = leq(UInt<1>(0h0), uncommonBits_16) node _T_360 = and(_T_358, _T_359) node _T_361 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_362 = and(_T_360, _T_361) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_363 = shr(io.in.a.bits.source, 2) node _T_364 = eq(_T_363, UInt<2>(0h2)) node _T_365 = leq(UInt<1>(0h0), uncommonBits_17) node _T_366 = and(_T_364, _T_365) node _T_367 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_368 = and(_T_366, _T_367) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_369 = shr(io.in.a.bits.source, 2) node _T_370 = eq(_T_369, UInt<2>(0h3)) node _T_371 = leq(UInt<1>(0h0), uncommonBits_18) node _T_372 = and(_T_370, _T_371) node _T_373 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_374 = and(_T_372, _T_373) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_375 = shr(io.in.a.bits.source, 3) node _T_376 = eq(_T_375, UInt<3>(0h4)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_19) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_382 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_383 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_384 = or(_T_350, _T_356) node _T_385 = or(_T_384, _T_362) node _T_386 = or(_T_385, _T_368) node _T_387 = or(_T_386, _T_374) node _T_388 = or(_T_387, _T_380) node _T_389 = or(_T_388, _T_381) node _T_390 = or(_T_389, _T_382) node _T_391 = or(_T_390, _T_383) node _T_392 = and(_T_349, _T_391) node _T_393 = or(UInt<1>(0h0), _T_392) node _T_394 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_395 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<14>(0h2000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<18>(0h2f000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<17>(0h10000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<13>(0h1000))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_426 = cvt(_T_425) node _T_427 = and(_T_426, asSInt(UInt<27>(0h4000000))) node _T_428 = asSInt(_T_427) node _T_429 = eq(_T_428, asSInt(UInt<1>(0h0))) node _T_430 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<13>(0h1000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = or(_T_399, _T_404) node _T_436 = or(_T_435, _T_409) node _T_437 = or(_T_436, _T_414) node _T_438 = or(_T_437, _T_419) node _T_439 = or(_T_438, _T_424) node _T_440 = or(_T_439, _T_429) node _T_441 = or(_T_440, _T_434) node _T_442 = and(_T_394, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = and(_T_393, _T_443) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_444, UInt<1>(0h1), "") : assert_10 node _T_448 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_449 = shr(io.in.a.bits.source, 2) node _T_450 = eq(_T_449, UInt<1>(0h0)) node _T_451 = leq(UInt<1>(0h0), uncommonBits_20) node _T_452 = and(_T_450, _T_451) node _T_453 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_454 = and(_T_452, _T_453) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_455 = shr(io.in.a.bits.source, 2) node _T_456 = eq(_T_455, UInt<1>(0h1)) node _T_457 = leq(UInt<1>(0h0), uncommonBits_21) node _T_458 = and(_T_456, _T_457) node _T_459 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_460 = and(_T_458, _T_459) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_461 = shr(io.in.a.bits.source, 2) node _T_462 = eq(_T_461, UInt<2>(0h2)) node _T_463 = leq(UInt<1>(0h0), uncommonBits_22) node _T_464 = and(_T_462, _T_463) node _T_465 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_466 = and(_T_464, _T_465) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_467 = shr(io.in.a.bits.source, 2) node _T_468 = eq(_T_467, UInt<2>(0h3)) node _T_469 = leq(UInt<1>(0h0), uncommonBits_23) node _T_470 = and(_T_468, _T_469) node _T_471 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_472 = and(_T_470, _T_471) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_473 = shr(io.in.a.bits.source, 3) node _T_474 = eq(_T_473, UInt<3>(0h4)) node _T_475 = leq(UInt<1>(0h0), uncommonBits_24) node _T_476 = and(_T_474, _T_475) node _T_477 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_481 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_448 connect _WIRE_2[1], _T_454 connect _WIRE_2[2], _T_460 connect _WIRE_2[3], _T_466 connect _WIRE_2[4], _T_472 connect _WIRE_2[5], _T_478 connect _WIRE_2[6], _T_479 connect _WIRE_2[7], _T_480 connect _WIRE_2[8], _T_481 node _T_482 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_483 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_484 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_485 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_486 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_487 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_488 = mux(_WIRE_2[5], _T_482, UInt<1>(0h0)) node _T_489 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_490 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_491 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_492 = or(_T_483, _T_484) node _T_493 = or(_T_492, _T_485) node _T_494 = or(_T_493, _T_486) node _T_495 = or(_T_494, _T_487) node _T_496 = or(_T_495, _T_488) node _T_497 = or(_T_496, _T_489) node _T_498 = or(_T_497, _T_490) node _T_499 = or(_T_498, _T_491) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_499 node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<17>(0h10000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<18>(0h2f000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<13>(0h1000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = or(_T_508, _T_513) node _T_545 = or(_T_544, _T_518) node _T_546 = or(_T_545, _T_523) node _T_547 = or(_T_546, _T_528) node _T_548 = or(_T_547, _T_533) node _T_549 = or(_T_548, _T_538) node _T_550 = or(_T_549, _T_543) node _T_551 = and(_T_503, _T_550) node _T_552 = or(UInt<1>(0h0), _T_551) node _T_553 = and(_WIRE_3, _T_552) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_553, UInt<1>(0h1), "") : assert_11 node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(source_ok, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_560 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_560, UInt<1>(0h1), "") : assert_13 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(is_aligned, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_567 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_567, UInt<1>(0h1), "") : assert_15 node _T_571 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_571, UInt<1>(0h1), "") : assert_16 node _T_575 = not(io.in.a.bits.mask) node _T_576 = eq(_T_575, UInt<1>(0h0)) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_576, UInt<1>(0h1), "") : assert_17 node _T_580 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_580, UInt<1>(0h1), "") : assert_18 node _T_584 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_584 : node _T_585 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_586 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_587 = and(_T_585, _T_586) node _T_588 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_589 = shr(io.in.a.bits.source, 2) node _T_590 = eq(_T_589, UInt<1>(0h0)) node _T_591 = leq(UInt<1>(0h0), uncommonBits_25) node _T_592 = and(_T_590, _T_591) node _T_593 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_594 = and(_T_592, _T_593) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_595 = shr(io.in.a.bits.source, 2) node _T_596 = eq(_T_595, UInt<1>(0h1)) node _T_597 = leq(UInt<1>(0h0), uncommonBits_26) node _T_598 = and(_T_596, _T_597) node _T_599 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_600 = and(_T_598, _T_599) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_601 = shr(io.in.a.bits.source, 2) node _T_602 = eq(_T_601, UInt<2>(0h2)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_27) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_607 = shr(io.in.a.bits.source, 2) node _T_608 = eq(_T_607, UInt<2>(0h3)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_28) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_613 = shr(io.in.a.bits.source, 3) node _T_614 = eq(_T_613, UInt<3>(0h4)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_29) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_620 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_621 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_622 = or(_T_588, _T_594) node _T_623 = or(_T_622, _T_600) node _T_624 = or(_T_623, _T_606) node _T_625 = or(_T_624, _T_612) node _T_626 = or(_T_625, _T_618) node _T_627 = or(_T_626, _T_619) node _T_628 = or(_T_627, _T_620) node _T_629 = or(_T_628, _T_621) node _T_630 = and(_T_587, _T_629) node _T_631 = or(UInt<1>(0h0), _T_630) node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(_T_631, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_631, UInt<1>(0h1), "") : assert_19 node _T_635 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_636 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_637 = and(_T_635, _T_636) node _T_638 = or(UInt<1>(0h0), _T_637) node _T_639 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<13>(0h1000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = and(_T_638, _T_643) node _T_645 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_646 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_647 = and(_T_645, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_650 = cvt(_T_649) node _T_651 = and(_T_650, asSInt(UInt<14>(0h2000))) node _T_652 = asSInt(_T_651) node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0))) node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_655 = cvt(_T_654) node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000))) node _T_657 = asSInt(_T_656) node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0))) node _T_659 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<18>(0h2f000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_665 = cvt(_T_664) node _T_666 = and(_T_665, asSInt(UInt<17>(0h10000))) node _T_667 = asSInt(_T_666) node _T_668 = eq(_T_667, asSInt(UInt<1>(0h0))) node _T_669 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_670 = cvt(_T_669) node _T_671 = and(_T_670, asSInt(UInt<13>(0h1000))) node _T_672 = asSInt(_T_671) node _T_673 = eq(_T_672, asSInt(UInt<1>(0h0))) node _T_674 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_675 = cvt(_T_674) node _T_676 = and(_T_675, asSInt(UInt<27>(0h4000000))) node _T_677 = asSInt(_T_676) node _T_678 = eq(_T_677, asSInt(UInt<1>(0h0))) node _T_679 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<13>(0h1000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = or(_T_653, _T_658) node _T_685 = or(_T_684, _T_663) node _T_686 = or(_T_685, _T_668) node _T_687 = or(_T_686, _T_673) node _T_688 = or(_T_687, _T_678) node _T_689 = or(_T_688, _T_683) node _T_690 = and(_T_648, _T_689) node _T_691 = or(UInt<1>(0h0), _T_644) node _T_692 = or(_T_691, _T_690) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_692, UInt<1>(0h1), "") : assert_20 node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(source_ok, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(is_aligned, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_702 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_702, UInt<1>(0h1), "") : assert_23 node _T_706 = eq(io.in.a.bits.mask, mask) node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(_T_706, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_706, UInt<1>(0h1), "") : assert_24 node _T_710 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(_T_710, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_710, UInt<1>(0h1), "") : assert_25 node _T_714 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_714 : node _T_715 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_716 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_717 = and(_T_715, _T_716) node _T_718 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_719 = shr(io.in.a.bits.source, 2) node _T_720 = eq(_T_719, UInt<1>(0h0)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_30) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_724 = and(_T_722, _T_723) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h1)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_31) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<2>(0h2)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_32) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h3)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_33) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_743 = shr(io.in.a.bits.source, 3) node _T_744 = eq(_T_743, UInt<3>(0h4)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_34) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_750 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_752 = or(_T_718, _T_724) node _T_753 = or(_T_752, _T_730) node _T_754 = or(_T_753, _T_736) node _T_755 = or(_T_754, _T_742) node _T_756 = or(_T_755, _T_748) node _T_757 = or(_T_756, _T_749) node _T_758 = or(_T_757, _T_750) node _T_759 = or(_T_758, _T_751) node _T_760 = and(_T_717, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_764 = and(_T_762, _T_763) node _T_765 = or(UInt<1>(0h0), _T_764) node _T_766 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_773 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_774 = and(_T_772, _T_773) node _T_775 = or(UInt<1>(0h0), _T_774) node _T_776 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<14>(0h2000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<18>(0h2f000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_792 = cvt(_T_791) node _T_793 = and(_T_792, asSInt(UInt<13>(0h1000))) node _T_794 = asSInt(_T_793) node _T_795 = eq(_T_794, asSInt(UInt<1>(0h0))) node _T_796 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_797 = cvt(_T_796) node _T_798 = and(_T_797, asSInt(UInt<27>(0h4000000))) node _T_799 = asSInt(_T_798) node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0))) node _T_801 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_802 = cvt(_T_801) node _T_803 = and(_T_802, asSInt(UInt<13>(0h1000))) node _T_804 = asSInt(_T_803) node _T_805 = eq(_T_804, asSInt(UInt<1>(0h0))) node _T_806 = or(_T_780, _T_785) node _T_807 = or(_T_806, _T_790) node _T_808 = or(_T_807, _T_795) node _T_809 = or(_T_808, _T_800) node _T_810 = or(_T_809, _T_805) node _T_811 = and(_T_775, _T_810) node _T_812 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_813 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = and(_T_812, _T_817) node _T_819 = or(UInt<1>(0h0), _T_771) node _T_820 = or(_T_819, _T_811) node _T_821 = or(_T_820, _T_818) node _T_822 = and(_T_761, _T_821) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_822, UInt<1>(0h1), "") : assert_26 node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(source_ok, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(is_aligned, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_832 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_832, UInt<1>(0h1), "") : assert_29 node _T_836 = eq(io.in.a.bits.mask, mask) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_836, UInt<1>(0h1), "") : assert_30 node _T_840 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_840 : node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<1>(0h0)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_35) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<1>(0h1)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_36) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_857 = shr(io.in.a.bits.source, 2) node _T_858 = eq(_T_857, UInt<2>(0h2)) node _T_859 = leq(UInt<1>(0h0), uncommonBits_37) node _T_860 = and(_T_858, _T_859) node _T_861 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_862 = and(_T_860, _T_861) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_863 = shr(io.in.a.bits.source, 2) node _T_864 = eq(_T_863, UInt<2>(0h3)) node _T_865 = leq(UInt<1>(0h0), uncommonBits_38) node _T_866 = and(_T_864, _T_865) node _T_867 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_868 = and(_T_866, _T_867) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_869 = shr(io.in.a.bits.source, 3) node _T_870 = eq(_T_869, UInt<3>(0h4)) node _T_871 = leq(UInt<1>(0h0), uncommonBits_39) node _T_872 = and(_T_870, _T_871) node _T_873 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_874 = and(_T_872, _T_873) node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_878 = or(_T_844, _T_850) node _T_879 = or(_T_878, _T_856) node _T_880 = or(_T_879, _T_862) node _T_881 = or(_T_880, _T_868) node _T_882 = or(_T_881, _T_874) node _T_883 = or(_T_882, _T_875) node _T_884 = or(_T_883, _T_876) node _T_885 = or(_T_884, _T_877) node _T_886 = and(_T_843, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_899 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_900 = and(_T_898, _T_899) node _T_901 = or(UInt<1>(0h0), _T_900) node _T_902 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<14>(0h2000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<18>(0h2f000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<17>(0h10000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<27>(0h4000000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<13>(0h1000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = or(_T_906, _T_911) node _T_933 = or(_T_932, _T_916) node _T_934 = or(_T_933, _T_921) node _T_935 = or(_T_934, _T_926) node _T_936 = or(_T_935, _T_931) node _T_937 = and(_T_901, _T_936) node _T_938 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_939 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<17>(0h10000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = and(_T_938, _T_943) node _T_945 = or(UInt<1>(0h0), _T_897) node _T_946 = or(_T_945, _T_937) node _T_947 = or(_T_946, _T_944) node _T_948 = and(_T_887, _T_947) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_948, UInt<1>(0h1), "") : assert_31 node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(source_ok, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_958 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_958, UInt<1>(0h1), "") : assert_34 node _T_962 = not(mask) node _T_963 = and(io.in.a.bits.mask, _T_962) node _T_964 = eq(_T_963, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_964, UInt<1>(0h1), "") : assert_35 node _T_968 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_968 : node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_971 = and(_T_969, _T_970) node _T_972 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_973 = shr(io.in.a.bits.source, 2) node _T_974 = eq(_T_973, UInt<1>(0h0)) node _T_975 = leq(UInt<1>(0h0), uncommonBits_40) node _T_976 = and(_T_974, _T_975) node _T_977 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_978 = and(_T_976, _T_977) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_979 = shr(io.in.a.bits.source, 2) node _T_980 = eq(_T_979, UInt<1>(0h1)) node _T_981 = leq(UInt<1>(0h0), uncommonBits_41) node _T_982 = and(_T_980, _T_981) node _T_983 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_984 = and(_T_982, _T_983) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_985 = shr(io.in.a.bits.source, 2) node _T_986 = eq(_T_985, UInt<2>(0h2)) node _T_987 = leq(UInt<1>(0h0), uncommonBits_42) node _T_988 = and(_T_986, _T_987) node _T_989 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_990 = and(_T_988, _T_989) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_991 = shr(io.in.a.bits.source, 2) node _T_992 = eq(_T_991, UInt<2>(0h3)) node _T_993 = leq(UInt<1>(0h0), uncommonBits_43) node _T_994 = and(_T_992, _T_993) node _T_995 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_996 = and(_T_994, _T_995) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_997 = shr(io.in.a.bits.source, 3) node _T_998 = eq(_T_997, UInt<3>(0h4)) node _T_999 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1000 = and(_T_998, _T_999) node _T_1001 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_1002 = and(_T_1000, _T_1001) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1005 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1006 = or(_T_972, _T_978) node _T_1007 = or(_T_1006, _T_984) node _T_1008 = or(_T_1007, _T_990) node _T_1009 = or(_T_1008, _T_996) node _T_1010 = or(_T_1009, _T_1002) node _T_1011 = or(_T_1010, _T_1003) node _T_1012 = or(_T_1011, _T_1004) node _T_1013 = or(_T_1012, _T_1005) node _T_1014 = and(_T_971, _T_1013) node _T_1015 = or(UInt<1>(0h0), _T_1014) node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1017 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<14>(0h2000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<13>(0h1000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1031 = cvt(_T_1030) node _T_1032 = and(_T_1031, asSInt(UInt<18>(0h2f000))) node _T_1033 = asSInt(_T_1032) node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0))) node _T_1035 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1036 = cvt(_T_1035) node _T_1037 = and(_T_1036, asSInt(UInt<17>(0h10000))) node _T_1038 = asSInt(_T_1037) node _T_1039 = eq(_T_1038, asSInt(UInt<1>(0h0))) node _T_1040 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1041 = cvt(_T_1040) node _T_1042 = and(_T_1041, asSInt(UInt<13>(0h1000))) node _T_1043 = asSInt(_T_1042) node _T_1044 = eq(_T_1043, asSInt(UInt<1>(0h0))) node _T_1045 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1046 = cvt(_T_1045) node _T_1047 = and(_T_1046, asSInt(UInt<27>(0h4000000))) node _T_1048 = asSInt(_T_1047) node _T_1049 = eq(_T_1048, asSInt(UInt<1>(0h0))) node _T_1050 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1051 = cvt(_T_1050) node _T_1052 = and(_T_1051, asSInt(UInt<13>(0h1000))) node _T_1053 = asSInt(_T_1052) node _T_1054 = eq(_T_1053, asSInt(UInt<1>(0h0))) node _T_1055 = or(_T_1024, _T_1029) node _T_1056 = or(_T_1055, _T_1034) node _T_1057 = or(_T_1056, _T_1039) node _T_1058 = or(_T_1057, _T_1044) node _T_1059 = or(_T_1058, _T_1049) node _T_1060 = or(_T_1059, _T_1054) node _T_1061 = and(_T_1019, _T_1060) node _T_1062 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1063 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<17>(0h10000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = and(_T_1062, _T_1067) node _T_1069 = or(UInt<1>(0h0), _T_1061) node _T_1070 = or(_T_1069, _T_1068) node _T_1071 = and(_T_1015, _T_1070) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_36 node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(source_ok, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(is_aligned, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1081 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_39 node _T_1085 = eq(io.in.a.bits.mask, mask) node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(_T_1085, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1085, UInt<1>(0h1), "") : assert_40 node _T_1089 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1089 : node _T_1090 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1091 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1094 = shr(io.in.a.bits.source, 2) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) node _T_1096 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1097 = and(_T_1095, _T_1096) node _T_1098 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1099 = and(_T_1097, _T_1098) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1100 = shr(io.in.a.bits.source, 2) node _T_1101 = eq(_T_1100, UInt<1>(0h1)) node _T_1102 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1103 = and(_T_1101, _T_1102) node _T_1104 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1105 = and(_T_1103, _T_1104) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1106 = shr(io.in.a.bits.source, 2) node _T_1107 = eq(_T_1106, UInt<2>(0h2)) node _T_1108 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1109 = and(_T_1107, _T_1108) node _T_1110 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1111 = and(_T_1109, _T_1110) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1112 = shr(io.in.a.bits.source, 2) node _T_1113 = eq(_T_1112, UInt<2>(0h3)) node _T_1114 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1115 = and(_T_1113, _T_1114) node _T_1116 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1117 = and(_T_1115, _T_1116) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_1118 = shr(io.in.a.bits.source, 3) node _T_1119 = eq(_T_1118, UInt<3>(0h4)) node _T_1120 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1125 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1126 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1127 = or(_T_1093, _T_1099) node _T_1128 = or(_T_1127, _T_1105) node _T_1129 = or(_T_1128, _T_1111) node _T_1130 = or(_T_1129, _T_1117) node _T_1131 = or(_T_1130, _T_1123) node _T_1132 = or(_T_1131, _T_1124) node _T_1133 = or(_T_1132, _T_1125) node _T_1134 = or(_T_1133, _T_1126) node _T_1135 = and(_T_1092, _T_1134) node _T_1136 = or(UInt<1>(0h0), _T_1135) node _T_1137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1138 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1139 = and(_T_1137, _T_1138) node _T_1140 = or(UInt<1>(0h0), _T_1139) node _T_1141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<14>(0h2000))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1147 = cvt(_T_1146) node _T_1148 = and(_T_1147, asSInt(UInt<13>(0h1000))) node _T_1149 = asSInt(_T_1148) node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0))) node _T_1151 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1152 = cvt(_T_1151) node _T_1153 = and(_T_1152, asSInt(UInt<18>(0h2f000))) node _T_1154 = asSInt(_T_1153) node _T_1155 = eq(_T_1154, asSInt(UInt<1>(0h0))) node _T_1156 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<17>(0h10000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1162 = cvt(_T_1161) node _T_1163 = and(_T_1162, asSInt(UInt<13>(0h1000))) node _T_1164 = asSInt(_T_1163) node _T_1165 = eq(_T_1164, asSInt(UInt<1>(0h0))) node _T_1166 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1167 = cvt(_T_1166) node _T_1168 = and(_T_1167, asSInt(UInt<27>(0h4000000))) node _T_1169 = asSInt(_T_1168) node _T_1170 = eq(_T_1169, asSInt(UInt<1>(0h0))) node _T_1171 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1172 = cvt(_T_1171) node _T_1173 = and(_T_1172, asSInt(UInt<13>(0h1000))) node _T_1174 = asSInt(_T_1173) node _T_1175 = eq(_T_1174, asSInt(UInt<1>(0h0))) node _T_1176 = or(_T_1145, _T_1150) node _T_1177 = or(_T_1176, _T_1155) node _T_1178 = or(_T_1177, _T_1160) node _T_1179 = or(_T_1178, _T_1165) node _T_1180 = or(_T_1179, _T_1170) node _T_1181 = or(_T_1180, _T_1175) node _T_1182 = and(_T_1140, _T_1181) node _T_1183 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1184 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1185 = cvt(_T_1184) node _T_1186 = and(_T_1185, asSInt(UInt<17>(0h10000))) node _T_1187 = asSInt(_T_1186) node _T_1188 = eq(_T_1187, asSInt(UInt<1>(0h0))) node _T_1189 = and(_T_1183, _T_1188) node _T_1190 = or(UInt<1>(0h0), _T_1182) node _T_1191 = or(_T_1190, _T_1189) node _T_1192 = and(_T_1136, _T_1191) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_41 node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(source_ok, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(is_aligned, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1202 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_44 node _T_1206 = eq(io.in.a.bits.mask, mask) node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(_T_1206, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1206, UInt<1>(0h1), "") : assert_45 node _T_1210 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1210 : node _T_1211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1212 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1213 = and(_T_1211, _T_1212) node _T_1214 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1215 = shr(io.in.a.bits.source, 2) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) node _T_1217 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1220 = and(_T_1218, _T_1219) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1221 = shr(io.in.a.bits.source, 2) node _T_1222 = eq(_T_1221, UInt<1>(0h1)) node _T_1223 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1226 = and(_T_1224, _T_1225) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1227 = shr(io.in.a.bits.source, 2) node _T_1228 = eq(_T_1227, UInt<2>(0h2)) node _T_1229 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1230 = and(_T_1228, _T_1229) node _T_1231 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1232 = and(_T_1230, _T_1231) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1233 = shr(io.in.a.bits.source, 2) node _T_1234 = eq(_T_1233, UInt<2>(0h3)) node _T_1235 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1236 = and(_T_1234, _T_1235) node _T_1237 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1238 = and(_T_1236, _T_1237) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_1239 = shr(io.in.a.bits.source, 3) node _T_1240 = eq(_T_1239, UInt<3>(0h4)) node _T_1241 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1242 = and(_T_1240, _T_1241) node _T_1243 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_1244 = and(_T_1242, _T_1243) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1247 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1248 = or(_T_1214, _T_1220) node _T_1249 = or(_T_1248, _T_1226) node _T_1250 = or(_T_1249, _T_1232) node _T_1251 = or(_T_1250, _T_1238) node _T_1252 = or(_T_1251, _T_1244) node _T_1253 = or(_T_1252, _T_1245) node _T_1254 = or(_T_1253, _T_1246) node _T_1255 = or(_T_1254, _T_1247) node _T_1256 = and(_T_1213, _T_1255) node _T_1257 = or(UInt<1>(0h0), _T_1256) node _T_1258 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1259 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = or(UInt<1>(0h0), _T_1260) node _T_1262 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1263 = cvt(_T_1262) node _T_1264 = and(_T_1263, asSInt(UInt<13>(0h1000))) node _T_1265 = asSInt(_T_1264) node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0))) node _T_1267 = and(_T_1261, _T_1266) node _T_1268 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1269 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1270 = cvt(_T_1269) node _T_1271 = and(_T_1270, asSInt(UInt<14>(0h2000))) node _T_1272 = asSInt(_T_1271) node _T_1273 = eq(_T_1272, asSInt(UInt<1>(0h0))) node _T_1274 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1275 = cvt(_T_1274) node _T_1276 = and(_T_1275, asSInt(UInt<17>(0h10000))) node _T_1277 = asSInt(_T_1276) node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0))) node _T_1279 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1280 = cvt(_T_1279) node _T_1281 = and(_T_1280, asSInt(UInt<18>(0h2f000))) node _T_1282 = asSInt(_T_1281) node _T_1283 = eq(_T_1282, asSInt(UInt<1>(0h0))) node _T_1284 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1285 = cvt(_T_1284) node _T_1286 = and(_T_1285, asSInt(UInt<17>(0h10000))) node _T_1287 = asSInt(_T_1286) node _T_1288 = eq(_T_1287, asSInt(UInt<1>(0h0))) node _T_1289 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1290 = cvt(_T_1289) node _T_1291 = and(_T_1290, asSInt(UInt<13>(0h1000))) node _T_1292 = asSInt(_T_1291) node _T_1293 = eq(_T_1292, asSInt(UInt<1>(0h0))) node _T_1294 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1295 = cvt(_T_1294) node _T_1296 = and(_T_1295, asSInt(UInt<27>(0h4000000))) node _T_1297 = asSInt(_T_1296) node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0))) node _T_1299 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1300 = cvt(_T_1299) node _T_1301 = and(_T_1300, asSInt(UInt<13>(0h1000))) node _T_1302 = asSInt(_T_1301) node _T_1303 = eq(_T_1302, asSInt(UInt<1>(0h0))) node _T_1304 = or(_T_1273, _T_1278) node _T_1305 = or(_T_1304, _T_1283) node _T_1306 = or(_T_1305, _T_1288) node _T_1307 = or(_T_1306, _T_1293) node _T_1308 = or(_T_1307, _T_1298) node _T_1309 = or(_T_1308, _T_1303) node _T_1310 = and(_T_1268, _T_1309) node _T_1311 = or(UInt<1>(0h0), _T_1267) node _T_1312 = or(_T_1311, _T_1310) node _T_1313 = and(_T_1257, _T_1312) node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(_T_1313, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1313, UInt<1>(0h1), "") : assert_46 node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(source_ok, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(is_aligned, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1323 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_49 node _T_1327 = eq(io.in.a.bits.mask, mask) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_50 node _T_1331 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1335 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 3) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1339 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1339 : node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(source_ok_1, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1343 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_54 node _T_1347 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_55 node _T_1351 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_56 node _T_1355 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_57 node _T_1359 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1359 : node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(source_ok_1, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(sink_ok, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1366 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1367 = asUInt(reset) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) when _T_1368 : node _T_1369 = eq(_T_1366, UInt<1>(0h0)) when _T_1369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1366, UInt<1>(0h1), "") : assert_60 node _T_1370 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(_T_1370, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1370, UInt<1>(0h1), "") : assert_61 node _T_1374 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_62 node _T_1378 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_63 node _T_1382 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1383 = or(UInt<1>(0h1), _T_1382) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_64 node _T_1387 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1387 : node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(source_ok_1, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(sink_ok, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1394 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_67 node _T_1398 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_68 node _T_1402 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_69 node _T_1406 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1407 = or(_T_1406, io.in.d.bits.corrupt) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_70 node _T_1411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1412 = or(UInt<1>(0h1), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_71 node _T_1416 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1416 : node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(source_ok_1, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1420 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1421 = asUInt(reset) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(_T_1420, UInt<1>(0h0)) when _T_1423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1420, UInt<1>(0h1), "") : assert_73 node _T_1424 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1425 = asUInt(reset) node _T_1426 = eq(_T_1425, UInt<1>(0h0)) when _T_1426 : node _T_1427 = eq(_T_1424, UInt<1>(0h0)) when _T_1427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1424, UInt<1>(0h1), "") : assert_74 node _T_1428 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1429 = or(UInt<1>(0h1), _T_1428) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_75 node _T_1433 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1433 : node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(source_ok_1, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1437 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(_T_1437, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1437, UInt<1>(0h1), "") : assert_77 node _T_1441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1442 = or(_T_1441, io.in.d.bits.corrupt) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_78 node _T_1446 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1447 = or(UInt<1>(0h1), _T_1446) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_79 node _T_1451 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1451 : node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(source_ok_1, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1455 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(_T_1455, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1455, UInt<1>(0h1), "") : assert_81 node _T_1459 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(_T_1459, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1459, UInt<1>(0h1), "") : assert_82 node _T_1463 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1464 = or(UInt<1>(0h1), _T_1463) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1468 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1472 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1476 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(_T_1476, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1476, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1480 = eq(a_first, UInt<1>(0h0)) node _T_1481 = and(io.in.a.valid, _T_1480) when _T_1481 : node _T_1482 = eq(io.in.a.bits.opcode, opcode) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_87 node _T_1486 = eq(io.in.a.bits.param, param) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_88 node _T_1490 = eq(io.in.a.bits.size, size) node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(_T_1490, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1490, UInt<1>(0h1), "") : assert_89 node _T_1494 = eq(io.in.a.bits.source, source) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_90 node _T_1498 = eq(io.in.a.bits.address, address) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_91 node _T_1502 = and(io.in.a.ready, io.in.a.valid) node _T_1503 = and(_T_1502, a_first) when _T_1503 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1504 = eq(d_first, UInt<1>(0h0)) node _T_1505 = and(io.in.d.valid, _T_1504) when _T_1505 : node _T_1506 = eq(io.in.d.bits.opcode, opcode_1) node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(_T_1506, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1506, UInt<1>(0h1), "") : assert_92 node _T_1510 = eq(io.in.d.bits.param, param_1) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_93 node _T_1514 = eq(io.in.d.bits.size, size_1) node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(_T_1514, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1514, UInt<1>(0h1), "") : assert_94 node _T_1518 = eq(io.in.d.bits.source, source_1) node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(_T_1518, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1518, UInt<1>(0h1), "") : assert_95 node _T_1522 = eq(io.in.d.bits.sink, sink) node _T_1523 = asUInt(reset) node _T_1524 = eq(_T_1523, UInt<1>(0h0)) when _T_1524 : node _T_1525 = eq(_T_1522, UInt<1>(0h0)) when _T_1525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1522, UInt<1>(0h1), "") : assert_96 node _T_1526 = eq(io.in.d.bits.denied, denied) node _T_1527 = asUInt(reset) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = eq(_T_1526, UInt<1>(0h0)) when _T_1529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1526, UInt<1>(0h1), "") : assert_97 node _T_1530 = and(io.in.d.ready, io.in.d.valid) node _T_1531 = and(_T_1530, d_first) when _T_1531 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1532 = and(io.in.a.valid, a_first_1) node _T_1533 = and(_T_1532, UInt<1>(0h1)) when _T_1533 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1534 = and(io.in.a.ready, io.in.a.valid) node _T_1535 = and(_T_1534, a_first_1) node _T_1536 = and(_T_1535, UInt<1>(0h1)) when _T_1536 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1537 = dshr(inflight, io.in.a.bits.source) node _T_1538 = bits(_T_1537, 0, 0) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1543 = and(io.in.d.valid, d_first_1) node _T_1544 = and(_T_1543, UInt<1>(0h1)) node _T_1545 = eq(d_release_ack, UInt<1>(0h0)) node _T_1546 = and(_T_1544, _T_1545) when _T_1546 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1547 = and(io.in.d.ready, io.in.d.valid) node _T_1548 = and(_T_1547, d_first_1) node _T_1549 = and(_T_1548, UInt<1>(0h1)) node _T_1550 = eq(d_release_ack, UInt<1>(0h0)) node _T_1551 = and(_T_1549, _T_1550) when _T_1551 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1552 = and(io.in.d.valid, d_first_1) node _T_1553 = and(_T_1552, UInt<1>(0h1)) node _T_1554 = eq(d_release_ack, UInt<1>(0h0)) node _T_1555 = and(_T_1553, _T_1554) when _T_1555 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1556 = dshr(inflight, io.in.d.bits.source) node _T_1557 = bits(_T_1556, 0, 0) node _T_1558 = or(_T_1557, same_cycle_resp) node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(_T_1558, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1558, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1562 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1563 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1564 = or(_T_1562, _T_1563) node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(_T_1564, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1564, UInt<1>(0h1), "") : assert_100 node _T_1568 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_101 else : node _T_1572 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1573 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1574 = or(_T_1572, _T_1573) node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(_T_1574, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1574, UInt<1>(0h1), "") : assert_102 node _T_1578 = eq(io.in.d.bits.size, a_size_lookup) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_103 node _T_1582 = and(io.in.d.valid, d_first_1) node _T_1583 = and(_T_1582, a_first_1) node _T_1584 = and(_T_1583, io.in.a.valid) node _T_1585 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1586 = and(_T_1584, _T_1585) node _T_1587 = eq(d_release_ack, UInt<1>(0h0)) node _T_1588 = and(_T_1586, _T_1587) when _T_1588 : node _T_1589 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1590 = or(_T_1589, io.in.a.ready) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_104 node _T_1594 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1595 = orr(a_set_wo_ready) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) node _T_1597 = or(_T_1594, _T_1596) node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(_T_1597, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1597, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_40 node _T_1601 = orr(inflight) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) node _T_1603 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1604 = or(_T_1602, _T_1603) node _T_1605 = lt(watchdog, plusarg_reader.out) node _T_1606 = or(_T_1604, _T_1605) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1610 = and(io.in.a.ready, io.in.a.valid) node _T_1611 = and(io.in.d.ready, io.in.d.valid) node _T_1612 = or(_T_1610, _T_1611) when _T_1612 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1613 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1614 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1615 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1616 = and(_T_1614, _T_1615) node _T_1617 = and(_T_1613, _T_1616) when _T_1617 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1618 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1619 = and(_T_1618, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1620 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1621 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1622 = and(_T_1620, _T_1621) node _T_1623 = and(_T_1619, _T_1622) when _T_1623 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1624 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1625 = bits(_T_1624, 0, 0) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1630 = and(io.in.d.valid, d_first_2) node _T_1631 = and(_T_1630, UInt<1>(0h1)) node _T_1632 = and(_T_1631, d_release_ack_1) when _T_1632 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1633 = and(io.in.d.ready, io.in.d.valid) node _T_1634 = and(_T_1633, d_first_2) node _T_1635 = and(_T_1634, UInt<1>(0h1)) node _T_1636 = and(_T_1635, d_release_ack_1) when _T_1636 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1637 = and(io.in.d.valid, d_first_2) node _T_1638 = and(_T_1637, UInt<1>(0h1)) node _T_1639 = and(_T_1638, d_release_ack_1) when _T_1639 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1640 = dshr(inflight_1, io.in.d.bits.source) node _T_1641 = bits(_T_1640, 0, 0) node _T_1642 = or(_T_1641, same_cycle_resp_1) node _T_1643 = asUInt(reset) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) when _T_1644 : node _T_1645 = eq(_T_1642, UInt<1>(0h0)) when _T_1645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1642, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1646 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_109 else : node _T_1650 = eq(io.in.d.bits.size, c_size_lookup) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_110 node _T_1654 = and(io.in.d.valid, d_first_2) node _T_1655 = and(_T_1654, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1656 = and(_T_1655, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1657 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1658 = and(_T_1656, _T_1657) node _T_1659 = and(_T_1658, d_release_ack_1) node _T_1660 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1661 = and(_T_1659, _T_1660) when _T_1661 : node _T_1662 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1663 = or(_T_1662, _WIRE_27.ready) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_111 node _T_1667 = orr(c_set_wo_ready) when _T_1667 : node _T_1668 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_41 node _T_1672 = orr(inflight_1) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) node _T_1674 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1675 = or(_T_1673, _T_1674) node _T_1676 = lt(watchdog_1, plusarg_reader_1.out) node _T_1677 = or(_T_1675, _T_1676) node _T_1678 = asUInt(reset) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) when _T_1679 : node _T_1680 = eq(_T_1677, UInt<1>(0h0)) when _T_1680 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1677, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1681 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1682 = and(io.in.d.ready, io.in.d.valid) node _T_1683 = or(_T_1681, _T_1682) when _T_1683 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1610 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1610; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1610; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1683 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1683; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1683; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1683; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1536 = _T_1610 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1536 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1536 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1536 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1536 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1536 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1582 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1582 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1551 = _T_1683 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1551 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1551 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1551 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1654 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1654 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1636 = _T_1683 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1636 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1636 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1636 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCache : input clock : Clock input reset : Reset output auto : { flip ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} inst ctrls of InclusiveCacheControl connect ctrls.clock, clock connect ctrls.reset, reset wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn_1.e.bits.sink invalidate nodeIn_1.e.valid invalidate nodeIn_1.e.ready invalidate nodeIn_1.d.bits.corrupt invalidate nodeIn_1.d.bits.data invalidate nodeIn_1.d.bits.denied invalidate nodeIn_1.d.bits.sink invalidate nodeIn_1.d.bits.source invalidate nodeIn_1.d.bits.size invalidate nodeIn_1.d.bits.param invalidate nodeIn_1.d.bits.opcode invalidate nodeIn_1.d.valid invalidate nodeIn_1.d.ready invalidate nodeIn_1.c.bits.corrupt invalidate nodeIn_1.c.bits.data invalidate nodeIn_1.c.bits.address invalidate nodeIn_1.c.bits.source invalidate nodeIn_1.c.bits.size invalidate nodeIn_1.c.bits.param invalidate nodeIn_1.c.bits.opcode invalidate nodeIn_1.c.valid invalidate nodeIn_1.c.ready invalidate nodeIn_1.b.bits.corrupt invalidate nodeIn_1.b.bits.data invalidate nodeIn_1.b.bits.mask invalidate nodeIn_1.b.bits.address invalidate nodeIn_1.b.bits.source invalidate nodeIn_1.b.bits.size invalidate nodeIn_1.b.bits.param invalidate nodeIn_1.b.bits.opcode invalidate nodeIn_1.b.valid invalidate nodeIn_1.b.ready invalidate nodeIn_1.a.bits.corrupt invalidate nodeIn_1.a.bits.data invalidate nodeIn_1.a.bits.mask invalidate nodeIn_1.a.bits.address invalidate nodeIn_1.a.bits.source invalidate nodeIn_1.a.bits.size invalidate nodeIn_1.a.bits.param invalidate nodeIn_1.a.bits.opcode invalidate nodeIn_1.a.valid invalidate nodeIn_1.a.ready wire nodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn_2.e.bits.sink invalidate nodeIn_2.e.valid invalidate nodeIn_2.e.ready invalidate nodeIn_2.d.bits.corrupt invalidate nodeIn_2.d.bits.data invalidate nodeIn_2.d.bits.denied invalidate nodeIn_2.d.bits.sink invalidate nodeIn_2.d.bits.source invalidate nodeIn_2.d.bits.size invalidate nodeIn_2.d.bits.param invalidate nodeIn_2.d.bits.opcode invalidate nodeIn_2.d.valid invalidate nodeIn_2.d.ready invalidate nodeIn_2.c.bits.corrupt invalidate nodeIn_2.c.bits.data invalidate nodeIn_2.c.bits.address invalidate nodeIn_2.c.bits.source invalidate nodeIn_2.c.bits.size invalidate nodeIn_2.c.bits.param invalidate nodeIn_2.c.bits.opcode invalidate nodeIn_2.c.valid invalidate nodeIn_2.c.ready invalidate nodeIn_2.b.bits.corrupt invalidate nodeIn_2.b.bits.data invalidate nodeIn_2.b.bits.mask invalidate nodeIn_2.b.bits.address invalidate nodeIn_2.b.bits.source invalidate nodeIn_2.b.bits.size invalidate nodeIn_2.b.bits.param invalidate nodeIn_2.b.bits.opcode invalidate nodeIn_2.b.valid invalidate nodeIn_2.b.ready invalidate nodeIn_2.a.bits.corrupt invalidate nodeIn_2.a.bits.data invalidate nodeIn_2.a.bits.mask invalidate nodeIn_2.a.bits.address invalidate nodeIn_2.a.bits.source invalidate nodeIn_2.a.bits.size invalidate nodeIn_2.a.bits.param invalidate nodeIn_2.a.bits.opcode invalidate nodeIn_2.a.valid invalidate nodeIn_2.a.ready wire nodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn_3.e.bits.sink invalidate nodeIn_3.e.valid invalidate nodeIn_3.e.ready invalidate nodeIn_3.d.bits.corrupt invalidate nodeIn_3.d.bits.data invalidate nodeIn_3.d.bits.denied invalidate nodeIn_3.d.bits.sink invalidate nodeIn_3.d.bits.source invalidate nodeIn_3.d.bits.size invalidate nodeIn_3.d.bits.param invalidate nodeIn_3.d.bits.opcode invalidate nodeIn_3.d.valid invalidate nodeIn_3.d.ready invalidate nodeIn_3.c.bits.corrupt invalidate nodeIn_3.c.bits.data invalidate nodeIn_3.c.bits.address invalidate nodeIn_3.c.bits.source invalidate nodeIn_3.c.bits.size invalidate nodeIn_3.c.bits.param invalidate nodeIn_3.c.bits.opcode invalidate nodeIn_3.c.valid invalidate nodeIn_3.c.ready invalidate nodeIn_3.b.bits.corrupt invalidate nodeIn_3.b.bits.data invalidate nodeIn_3.b.bits.mask invalidate nodeIn_3.b.bits.address invalidate nodeIn_3.b.bits.source invalidate nodeIn_3.b.bits.size invalidate nodeIn_3.b.bits.param invalidate nodeIn_3.b.bits.opcode invalidate nodeIn_3.b.valid invalidate nodeIn_3.b.ready invalidate nodeIn_3.a.bits.corrupt invalidate nodeIn_3.a.bits.data invalidate nodeIn_3.a.bits.mask invalidate nodeIn_3.a.bits.address invalidate nodeIn_3.a.bits.source invalidate nodeIn_3.a.bits.size invalidate nodeIn_3.a.bits.param invalidate nodeIn_3.a.bits.opcode invalidate nodeIn_3.a.valid invalidate nodeIn_3.a.ready inst monitor of TLMonitor_40 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready inst monitor_1 of TLMonitor_41 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.e.bits.sink, nodeIn_1.e.bits.sink connect monitor_1.io.in.e.valid, nodeIn_1.e.valid connect monitor_1.io.in.e.ready, nodeIn_1.e.ready connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, nodeIn_1.d.valid connect monitor_1.io.in.d.ready, nodeIn_1.d.ready connect monitor_1.io.in.c.bits.corrupt, nodeIn_1.c.bits.corrupt connect monitor_1.io.in.c.bits.data, nodeIn_1.c.bits.data connect monitor_1.io.in.c.bits.address, nodeIn_1.c.bits.address connect monitor_1.io.in.c.bits.source, nodeIn_1.c.bits.source connect monitor_1.io.in.c.bits.size, nodeIn_1.c.bits.size connect monitor_1.io.in.c.bits.param, nodeIn_1.c.bits.param connect monitor_1.io.in.c.bits.opcode, nodeIn_1.c.bits.opcode connect monitor_1.io.in.c.valid, nodeIn_1.c.valid connect monitor_1.io.in.c.ready, nodeIn_1.c.ready connect monitor_1.io.in.b.bits.corrupt, nodeIn_1.b.bits.corrupt connect monitor_1.io.in.b.bits.data, nodeIn_1.b.bits.data connect monitor_1.io.in.b.bits.mask, nodeIn_1.b.bits.mask connect monitor_1.io.in.b.bits.address, nodeIn_1.b.bits.address connect monitor_1.io.in.b.bits.source, nodeIn_1.b.bits.source connect monitor_1.io.in.b.bits.size, nodeIn_1.b.bits.size connect monitor_1.io.in.b.bits.param, nodeIn_1.b.bits.param connect monitor_1.io.in.b.bits.opcode, nodeIn_1.b.bits.opcode connect monitor_1.io.in.b.valid, nodeIn_1.b.valid connect monitor_1.io.in.b.ready, nodeIn_1.b.ready connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, nodeIn_1.a.valid connect monitor_1.io.in.a.ready, nodeIn_1.a.ready inst monitor_2 of TLMonitor_42 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.e.bits.sink, nodeIn_2.e.bits.sink connect monitor_2.io.in.e.valid, nodeIn_2.e.valid connect monitor_2.io.in.e.ready, nodeIn_2.e.ready connect monitor_2.io.in.d.bits.corrupt, nodeIn_2.d.bits.corrupt connect monitor_2.io.in.d.bits.data, nodeIn_2.d.bits.data connect monitor_2.io.in.d.bits.denied, nodeIn_2.d.bits.denied connect monitor_2.io.in.d.bits.sink, nodeIn_2.d.bits.sink connect monitor_2.io.in.d.bits.source, nodeIn_2.d.bits.source connect monitor_2.io.in.d.bits.size, nodeIn_2.d.bits.size connect monitor_2.io.in.d.bits.param, nodeIn_2.d.bits.param connect monitor_2.io.in.d.bits.opcode, nodeIn_2.d.bits.opcode connect monitor_2.io.in.d.valid, nodeIn_2.d.valid connect monitor_2.io.in.d.ready, nodeIn_2.d.ready connect monitor_2.io.in.c.bits.corrupt, nodeIn_2.c.bits.corrupt connect monitor_2.io.in.c.bits.data, nodeIn_2.c.bits.data connect monitor_2.io.in.c.bits.address, nodeIn_2.c.bits.address connect monitor_2.io.in.c.bits.source, nodeIn_2.c.bits.source connect monitor_2.io.in.c.bits.size, nodeIn_2.c.bits.size connect monitor_2.io.in.c.bits.param, nodeIn_2.c.bits.param connect monitor_2.io.in.c.bits.opcode, nodeIn_2.c.bits.opcode connect monitor_2.io.in.c.valid, nodeIn_2.c.valid connect monitor_2.io.in.c.ready, nodeIn_2.c.ready connect monitor_2.io.in.b.bits.corrupt, nodeIn_2.b.bits.corrupt connect monitor_2.io.in.b.bits.data, nodeIn_2.b.bits.data connect monitor_2.io.in.b.bits.mask, nodeIn_2.b.bits.mask connect monitor_2.io.in.b.bits.address, nodeIn_2.b.bits.address connect monitor_2.io.in.b.bits.source, nodeIn_2.b.bits.source connect monitor_2.io.in.b.bits.size, nodeIn_2.b.bits.size connect monitor_2.io.in.b.bits.param, nodeIn_2.b.bits.param connect monitor_2.io.in.b.bits.opcode, nodeIn_2.b.bits.opcode connect monitor_2.io.in.b.valid, nodeIn_2.b.valid connect monitor_2.io.in.b.ready, nodeIn_2.b.ready connect monitor_2.io.in.a.bits.corrupt, nodeIn_2.a.bits.corrupt connect monitor_2.io.in.a.bits.data, nodeIn_2.a.bits.data connect monitor_2.io.in.a.bits.mask, nodeIn_2.a.bits.mask connect monitor_2.io.in.a.bits.address, nodeIn_2.a.bits.address connect monitor_2.io.in.a.bits.source, nodeIn_2.a.bits.source connect monitor_2.io.in.a.bits.size, nodeIn_2.a.bits.size connect monitor_2.io.in.a.bits.param, nodeIn_2.a.bits.param connect monitor_2.io.in.a.bits.opcode, nodeIn_2.a.bits.opcode connect monitor_2.io.in.a.valid, nodeIn_2.a.valid connect monitor_2.io.in.a.ready, nodeIn_2.a.ready inst monitor_3 of TLMonitor_43 connect monitor_3.clock, clock connect monitor_3.reset, reset connect monitor_3.io.in.e.bits.sink, nodeIn_3.e.bits.sink connect monitor_3.io.in.e.valid, nodeIn_3.e.valid connect monitor_3.io.in.e.ready, nodeIn_3.e.ready connect monitor_3.io.in.d.bits.corrupt, nodeIn_3.d.bits.corrupt connect monitor_3.io.in.d.bits.data, nodeIn_3.d.bits.data connect monitor_3.io.in.d.bits.denied, nodeIn_3.d.bits.denied connect monitor_3.io.in.d.bits.sink, nodeIn_3.d.bits.sink connect monitor_3.io.in.d.bits.source, nodeIn_3.d.bits.source connect monitor_3.io.in.d.bits.size, nodeIn_3.d.bits.size connect monitor_3.io.in.d.bits.param, nodeIn_3.d.bits.param connect monitor_3.io.in.d.bits.opcode, nodeIn_3.d.bits.opcode connect monitor_3.io.in.d.valid, nodeIn_3.d.valid connect monitor_3.io.in.d.ready, nodeIn_3.d.ready connect monitor_3.io.in.c.bits.corrupt, nodeIn_3.c.bits.corrupt connect monitor_3.io.in.c.bits.data, nodeIn_3.c.bits.data connect monitor_3.io.in.c.bits.address, nodeIn_3.c.bits.address connect monitor_3.io.in.c.bits.source, nodeIn_3.c.bits.source connect monitor_3.io.in.c.bits.size, nodeIn_3.c.bits.size connect monitor_3.io.in.c.bits.param, nodeIn_3.c.bits.param connect monitor_3.io.in.c.bits.opcode, nodeIn_3.c.bits.opcode connect monitor_3.io.in.c.valid, nodeIn_3.c.valid connect monitor_3.io.in.c.ready, nodeIn_3.c.ready connect monitor_3.io.in.b.bits.corrupt, nodeIn_3.b.bits.corrupt connect monitor_3.io.in.b.bits.data, nodeIn_3.b.bits.data connect monitor_3.io.in.b.bits.mask, nodeIn_3.b.bits.mask connect monitor_3.io.in.b.bits.address, nodeIn_3.b.bits.address connect monitor_3.io.in.b.bits.source, nodeIn_3.b.bits.source connect monitor_3.io.in.b.bits.size, nodeIn_3.b.bits.size connect monitor_3.io.in.b.bits.param, nodeIn_3.b.bits.param connect monitor_3.io.in.b.bits.opcode, nodeIn_3.b.bits.opcode connect monitor_3.io.in.b.valid, nodeIn_3.b.valid connect monitor_3.io.in.b.ready, nodeIn_3.b.ready connect monitor_3.io.in.a.bits.corrupt, nodeIn_3.a.bits.corrupt connect monitor_3.io.in.a.bits.data, nodeIn_3.a.bits.data connect monitor_3.io.in.a.bits.mask, nodeIn_3.a.bits.mask connect monitor_3.io.in.a.bits.address, nodeIn_3.a.bits.address connect monitor_3.io.in.a.bits.source, nodeIn_3.a.bits.source connect monitor_3.io.in.a.bits.size, nodeIn_3.a.bits.size connect monitor_3.io.in.a.bits.param, nodeIn_3.a.bits.param connect monitor_3.io.in.a.bits.opcode, nodeIn_3.a.bits.opcode connect monitor_3.io.in.a.valid, nodeIn_3.a.valid connect monitor_3.io.in.a.ready, nodeIn_3.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_nodeOut.e.bits.sink invalidate x1_nodeOut.e.valid invalidate x1_nodeOut.e.ready invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.c.bits.corrupt invalidate x1_nodeOut.c.bits.data invalidate x1_nodeOut.c.bits.address invalidate x1_nodeOut.c.bits.source invalidate x1_nodeOut.c.bits.size invalidate x1_nodeOut.c.bits.param invalidate x1_nodeOut.c.bits.opcode invalidate x1_nodeOut.c.valid invalidate x1_nodeOut.c.ready invalidate x1_nodeOut.b.bits.corrupt invalidate x1_nodeOut.b.bits.data invalidate x1_nodeOut.b.bits.mask invalidate x1_nodeOut.b.bits.address invalidate x1_nodeOut.b.bits.source invalidate x1_nodeOut.b.bits.size invalidate x1_nodeOut.b.bits.param invalidate x1_nodeOut.b.bits.opcode invalidate x1_nodeOut.b.valid invalidate x1_nodeOut.b.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready wire x1_nodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_nodeOut_1.e.bits.sink invalidate x1_nodeOut_1.e.valid invalidate x1_nodeOut_1.e.ready invalidate x1_nodeOut_1.d.bits.corrupt invalidate x1_nodeOut_1.d.bits.data invalidate x1_nodeOut_1.d.bits.denied invalidate x1_nodeOut_1.d.bits.sink invalidate x1_nodeOut_1.d.bits.source invalidate x1_nodeOut_1.d.bits.size invalidate x1_nodeOut_1.d.bits.param invalidate x1_nodeOut_1.d.bits.opcode invalidate x1_nodeOut_1.d.valid invalidate x1_nodeOut_1.d.ready invalidate x1_nodeOut_1.c.bits.corrupt invalidate x1_nodeOut_1.c.bits.data invalidate x1_nodeOut_1.c.bits.address invalidate x1_nodeOut_1.c.bits.source invalidate x1_nodeOut_1.c.bits.size invalidate x1_nodeOut_1.c.bits.param invalidate x1_nodeOut_1.c.bits.opcode invalidate x1_nodeOut_1.c.valid invalidate x1_nodeOut_1.c.ready invalidate x1_nodeOut_1.b.bits.corrupt invalidate x1_nodeOut_1.b.bits.data invalidate x1_nodeOut_1.b.bits.mask invalidate x1_nodeOut_1.b.bits.address invalidate x1_nodeOut_1.b.bits.source invalidate x1_nodeOut_1.b.bits.size invalidate x1_nodeOut_1.b.bits.param invalidate x1_nodeOut_1.b.bits.opcode invalidate x1_nodeOut_1.b.valid invalidate x1_nodeOut_1.b.ready invalidate x1_nodeOut_1.a.bits.corrupt invalidate x1_nodeOut_1.a.bits.data invalidate x1_nodeOut_1.a.bits.mask invalidate x1_nodeOut_1.a.bits.address invalidate x1_nodeOut_1.a.bits.source invalidate x1_nodeOut_1.a.bits.size invalidate x1_nodeOut_1.a.bits.param invalidate x1_nodeOut_1.a.bits.opcode invalidate x1_nodeOut_1.a.valid invalidate x1_nodeOut_1.a.ready wire x1_nodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_nodeOut_2.e.bits.sink invalidate x1_nodeOut_2.e.valid invalidate x1_nodeOut_2.e.ready invalidate x1_nodeOut_2.d.bits.corrupt invalidate x1_nodeOut_2.d.bits.data invalidate x1_nodeOut_2.d.bits.denied invalidate x1_nodeOut_2.d.bits.sink invalidate x1_nodeOut_2.d.bits.source invalidate x1_nodeOut_2.d.bits.size invalidate x1_nodeOut_2.d.bits.param invalidate x1_nodeOut_2.d.bits.opcode invalidate x1_nodeOut_2.d.valid invalidate x1_nodeOut_2.d.ready invalidate x1_nodeOut_2.c.bits.corrupt invalidate x1_nodeOut_2.c.bits.data invalidate x1_nodeOut_2.c.bits.address invalidate x1_nodeOut_2.c.bits.source invalidate x1_nodeOut_2.c.bits.size invalidate x1_nodeOut_2.c.bits.param invalidate x1_nodeOut_2.c.bits.opcode invalidate x1_nodeOut_2.c.valid invalidate x1_nodeOut_2.c.ready invalidate x1_nodeOut_2.b.bits.corrupt invalidate x1_nodeOut_2.b.bits.data invalidate x1_nodeOut_2.b.bits.mask invalidate x1_nodeOut_2.b.bits.address invalidate x1_nodeOut_2.b.bits.source invalidate x1_nodeOut_2.b.bits.size invalidate x1_nodeOut_2.b.bits.param invalidate x1_nodeOut_2.b.bits.opcode invalidate x1_nodeOut_2.b.valid invalidate x1_nodeOut_2.b.ready invalidate x1_nodeOut_2.a.bits.corrupt invalidate x1_nodeOut_2.a.bits.data invalidate x1_nodeOut_2.a.bits.mask invalidate x1_nodeOut_2.a.bits.address invalidate x1_nodeOut_2.a.bits.source invalidate x1_nodeOut_2.a.bits.size invalidate x1_nodeOut_2.a.bits.param invalidate x1_nodeOut_2.a.bits.opcode invalidate x1_nodeOut_2.a.valid invalidate x1_nodeOut_2.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeIn_2, auto.in_2 connect nodeIn_3, auto.in_3 connect ctrls.auto.ctrl_in, auto.ctrls_ctrl_in inst inclusive_cache_bank_sched of InclusiveCacheBankScheduler connect inclusive_cache_bank_sched.clock, clock connect inclusive_cache_bank_sched.reset, reset connect inclusive_cache_bank_sched.io.in, nodeIn connect nodeOut.e.bits, inclusive_cache_bank_sched.io.out.e.bits connect nodeOut.e.valid, inclusive_cache_bank_sched.io.out.e.valid connect inclusive_cache_bank_sched.io.out.e.ready, nodeOut.e.ready connect inclusive_cache_bank_sched.io.out.d, nodeOut.d connect nodeOut.c.bits, inclusive_cache_bank_sched.io.out.c.bits connect nodeOut.c.valid, inclusive_cache_bank_sched.io.out.c.valid connect inclusive_cache_bank_sched.io.out.c.ready, nodeOut.c.ready connect inclusive_cache_bank_sched.io.out.b, nodeOut.b connect nodeOut.a.bits, inclusive_cache_bank_sched.io.out.a.bits connect nodeOut.a.valid, inclusive_cache_bank_sched.io.out.a.valid connect inclusive_cache_bank_sched.io.out.a.ready, nodeOut.a.ready invalidate inclusive_cache_bank_sched.io.ways[0] invalidate inclusive_cache_bank_sched.io.ways[1] invalidate inclusive_cache_bank_sched.io.ways[2] invalidate inclusive_cache_bank_sched.io.ways[3] invalidate inclusive_cache_bank_sched.io.ways[4] invalidate inclusive_cache_bank_sched.io.ways[5] invalidate inclusive_cache_bank_sched.io.ways[6] invalidate inclusive_cache_bank_sched.io.ways[7] invalidate inclusive_cache_bank_sched.io.ways[8] invalidate inclusive_cache_bank_sched.io.ways[9] invalidate inclusive_cache_bank_sched.io.ways[10] invalidate inclusive_cache_bank_sched.io.ways[11] invalidate inclusive_cache_bank_sched.io.ways[12] invalidate inclusive_cache_bank_sched.io.divs[0] invalidate inclusive_cache_bank_sched.io.divs[1] invalidate inclusive_cache_bank_sched.io.divs[2] invalidate inclusive_cache_bank_sched.io.divs[3] invalidate inclusive_cache_bank_sched.io.divs[4] invalidate inclusive_cache_bank_sched.io.divs[5] invalidate inclusive_cache_bank_sched.io.divs[6] invalidate inclusive_cache_bank_sched.io.divs[7] invalidate inclusive_cache_bank_sched.io.divs[8] invalidate inclusive_cache_bank_sched.io.divs[9] invalidate inclusive_cache_bank_sched.io.divs[10] invalidate inclusive_cache_bank_sched.io.divs[11] invalidate inclusive_cache_bank_sched.io.divs[12] connect inclusive_cache_bank_sched.io.req.valid, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.req.bits.address, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1) node _nodeOut_a_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_address_mux_matches_T_1 = cvt(_nodeOut_a_bits_address_mux_matches_T) node _nodeOut_a_bits_address_mux_matches_T_2 = and(_nodeOut_a_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_mux_matches_T_3 = asSInt(_nodeOut_a_bits_address_mux_matches_T_2) node nodeOut_a_bits_address_mux_0_1 = eq(_nodeOut_a_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_T = or(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T node _nodeIn_b_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) node _nodeIn_b_bits_address_mux_matches_T_1 = cvt(_nodeIn_b_bits_address_mux_matches_T) node _nodeIn_b_bits_address_mux_matches_T_2 = and(_nodeIn_b_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_mux_matches_T_3 = asSInt(_nodeIn_b_bits_address_mux_matches_T_2) node nodeIn_b_bits_address_mux_0_1 = eq(_nodeIn_b_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_T = or(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) connect nodeIn.b.bits.address, _nodeIn_b_bits_address_T node _nodeOut_c_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) node _nodeOut_c_bits_address_mux_matches_T_1 = cvt(_nodeOut_c_bits_address_mux_matches_T) node _nodeOut_c_bits_address_mux_matches_T_2 = and(_nodeOut_c_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_mux_matches_T_3 = asSInt(_nodeOut_c_bits_address_mux_matches_T_2) node nodeOut_c_bits_address_mux_0_1 = eq(_nodeOut_c_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_T = or(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) connect nodeOut.c.bits.address, _nodeOut_c_bits_address_T inst inclusive_cache_bank_sched_1 of InclusiveCacheBankScheduler_1 connect inclusive_cache_bank_sched_1.clock, clock connect inclusive_cache_bank_sched_1.reset, reset connect inclusive_cache_bank_sched_1.io.in, nodeIn_1 connect x1_nodeOut.e.bits, inclusive_cache_bank_sched_1.io.out.e.bits connect x1_nodeOut.e.valid, inclusive_cache_bank_sched_1.io.out.e.valid connect inclusive_cache_bank_sched_1.io.out.e.ready, x1_nodeOut.e.ready connect inclusive_cache_bank_sched_1.io.out.d, x1_nodeOut.d connect x1_nodeOut.c.bits, inclusive_cache_bank_sched_1.io.out.c.bits connect x1_nodeOut.c.valid, inclusive_cache_bank_sched_1.io.out.c.valid connect inclusive_cache_bank_sched_1.io.out.c.ready, x1_nodeOut.c.ready connect inclusive_cache_bank_sched_1.io.out.b, x1_nodeOut.b connect x1_nodeOut.a.bits, inclusive_cache_bank_sched_1.io.out.a.bits connect x1_nodeOut.a.valid, inclusive_cache_bank_sched_1.io.out.a.valid connect inclusive_cache_bank_sched_1.io.out.a.ready, x1_nodeOut.a.ready invalidate inclusive_cache_bank_sched_1.io.ways[0] invalidate inclusive_cache_bank_sched_1.io.ways[1] invalidate inclusive_cache_bank_sched_1.io.ways[2] invalidate inclusive_cache_bank_sched_1.io.ways[3] invalidate inclusive_cache_bank_sched_1.io.ways[4] invalidate inclusive_cache_bank_sched_1.io.ways[5] invalidate inclusive_cache_bank_sched_1.io.ways[6] invalidate inclusive_cache_bank_sched_1.io.ways[7] invalidate inclusive_cache_bank_sched_1.io.ways[8] invalidate inclusive_cache_bank_sched_1.io.ways[9] invalidate inclusive_cache_bank_sched_1.io.ways[10] invalidate inclusive_cache_bank_sched_1.io.ways[11] invalidate inclusive_cache_bank_sched_1.io.ways[12] invalidate inclusive_cache_bank_sched_1.io.divs[0] invalidate inclusive_cache_bank_sched_1.io.divs[1] invalidate inclusive_cache_bank_sched_1.io.divs[2] invalidate inclusive_cache_bank_sched_1.io.divs[3] invalidate inclusive_cache_bank_sched_1.io.divs[4] invalidate inclusive_cache_bank_sched_1.io.divs[5] invalidate inclusive_cache_bank_sched_1.io.divs[6] invalidate inclusive_cache_bank_sched_1.io.divs[7] invalidate inclusive_cache_bank_sched_1.io.divs[8] invalidate inclusive_cache_bank_sched_1.io.divs[9] invalidate inclusive_cache_bank_sched_1.io.divs[10] invalidate inclusive_cache_bank_sched_1.io.divs[11] invalidate inclusive_cache_bank_sched_1.io.divs[12] connect inclusive_cache_bank_sched_1.io.req.valid, UInt<1>(0h0) connect inclusive_cache_bank_sched_1.io.req.bits.address, UInt<1>(0h0) connect inclusive_cache_bank_sched_1.io.resp.ready, UInt<1>(0h1) node _nodeOut_a_bits_address_mux_matches_T_4 = xor(inclusive_cache_bank_sched_1.io.out.a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_address_mux_matches_T_5 = cvt(_nodeOut_a_bits_address_mux_matches_T_4) node _nodeOut_a_bits_address_mux_matches_T_6 = and(_nodeOut_a_bits_address_mux_matches_T_5, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_mux_matches_T_7 = asSInt(_nodeOut_a_bits_address_mux_matches_T_6) node nodeOut_a_bits_address_mux_0_1_1 = eq(_nodeOut_a_bits_address_mux_matches_T_7, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_T_1 = or(inclusive_cache_bank_sched_1.io.out.a.bits.address, UInt<7>(0h40)) connect x1_nodeOut.a.bits.address, _nodeOut_a_bits_address_T_1 node _nodeIn_b_bits_address_mux_matches_T_4 = xor(inclusive_cache_bank_sched_1.io.in.b.bits.address, UInt<1>(0h0)) node _nodeIn_b_bits_address_mux_matches_T_5 = cvt(_nodeIn_b_bits_address_mux_matches_T_4) node _nodeIn_b_bits_address_mux_matches_T_6 = and(_nodeIn_b_bits_address_mux_matches_T_5, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_mux_matches_T_7 = asSInt(_nodeIn_b_bits_address_mux_matches_T_6) node nodeIn_b_bits_address_mux_0_1_1 = eq(_nodeIn_b_bits_address_mux_matches_T_7, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_T_1 = or(inclusive_cache_bank_sched_1.io.in.b.bits.address, UInt<7>(0h40)) connect nodeIn_1.b.bits.address, _nodeIn_b_bits_address_T_1 node _nodeOut_c_bits_address_mux_matches_T_4 = xor(inclusive_cache_bank_sched_1.io.out.c.bits.address, UInt<1>(0h0)) node _nodeOut_c_bits_address_mux_matches_T_5 = cvt(_nodeOut_c_bits_address_mux_matches_T_4) node _nodeOut_c_bits_address_mux_matches_T_6 = and(_nodeOut_c_bits_address_mux_matches_T_5, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_mux_matches_T_7 = asSInt(_nodeOut_c_bits_address_mux_matches_T_6) node nodeOut_c_bits_address_mux_0_1_1 = eq(_nodeOut_c_bits_address_mux_matches_T_7, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_T_1 = or(inclusive_cache_bank_sched_1.io.out.c.bits.address, UInt<7>(0h40)) connect x1_nodeOut.c.bits.address, _nodeOut_c_bits_address_T_1 inst inclusive_cache_bank_sched_2 of InclusiveCacheBankScheduler_2 connect inclusive_cache_bank_sched_2.clock, clock connect inclusive_cache_bank_sched_2.reset, reset connect inclusive_cache_bank_sched_2.io.in, nodeIn_2 connect x1_nodeOut_1.e.bits, inclusive_cache_bank_sched_2.io.out.e.bits connect x1_nodeOut_1.e.valid, inclusive_cache_bank_sched_2.io.out.e.valid connect inclusive_cache_bank_sched_2.io.out.e.ready, x1_nodeOut_1.e.ready connect inclusive_cache_bank_sched_2.io.out.d, x1_nodeOut_1.d connect x1_nodeOut_1.c.bits, inclusive_cache_bank_sched_2.io.out.c.bits connect x1_nodeOut_1.c.valid, inclusive_cache_bank_sched_2.io.out.c.valid connect inclusive_cache_bank_sched_2.io.out.c.ready, x1_nodeOut_1.c.ready connect inclusive_cache_bank_sched_2.io.out.b, x1_nodeOut_1.b connect x1_nodeOut_1.a.bits, inclusive_cache_bank_sched_2.io.out.a.bits connect x1_nodeOut_1.a.valid, inclusive_cache_bank_sched_2.io.out.a.valid connect inclusive_cache_bank_sched_2.io.out.a.ready, x1_nodeOut_1.a.ready invalidate inclusive_cache_bank_sched_2.io.ways[0] invalidate inclusive_cache_bank_sched_2.io.ways[1] invalidate inclusive_cache_bank_sched_2.io.ways[2] invalidate inclusive_cache_bank_sched_2.io.ways[3] invalidate inclusive_cache_bank_sched_2.io.ways[4] invalidate inclusive_cache_bank_sched_2.io.ways[5] invalidate inclusive_cache_bank_sched_2.io.ways[6] invalidate inclusive_cache_bank_sched_2.io.ways[7] invalidate inclusive_cache_bank_sched_2.io.ways[8] invalidate inclusive_cache_bank_sched_2.io.ways[9] invalidate inclusive_cache_bank_sched_2.io.ways[10] invalidate inclusive_cache_bank_sched_2.io.ways[11] invalidate inclusive_cache_bank_sched_2.io.ways[12] invalidate inclusive_cache_bank_sched_2.io.divs[0] invalidate inclusive_cache_bank_sched_2.io.divs[1] invalidate inclusive_cache_bank_sched_2.io.divs[2] invalidate inclusive_cache_bank_sched_2.io.divs[3] invalidate inclusive_cache_bank_sched_2.io.divs[4] invalidate inclusive_cache_bank_sched_2.io.divs[5] invalidate inclusive_cache_bank_sched_2.io.divs[6] invalidate inclusive_cache_bank_sched_2.io.divs[7] invalidate inclusive_cache_bank_sched_2.io.divs[8] invalidate inclusive_cache_bank_sched_2.io.divs[9] invalidate inclusive_cache_bank_sched_2.io.divs[10] invalidate inclusive_cache_bank_sched_2.io.divs[11] invalidate inclusive_cache_bank_sched_2.io.divs[12] connect inclusive_cache_bank_sched_2.io.req.valid, UInt<1>(0h0) connect inclusive_cache_bank_sched_2.io.req.bits.address, UInt<1>(0h0) connect inclusive_cache_bank_sched_2.io.resp.ready, UInt<1>(0h1) node _nodeOut_a_bits_address_mux_matches_T_8 = xor(inclusive_cache_bank_sched_2.io.out.a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_address_mux_matches_T_9 = cvt(_nodeOut_a_bits_address_mux_matches_T_8) node _nodeOut_a_bits_address_mux_matches_T_10 = and(_nodeOut_a_bits_address_mux_matches_T_9, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_mux_matches_T_11 = asSInt(_nodeOut_a_bits_address_mux_matches_T_10) node nodeOut_a_bits_address_mux_0_1_2 = eq(_nodeOut_a_bits_address_mux_matches_T_11, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_T_2 = or(inclusive_cache_bank_sched_2.io.out.a.bits.address, UInt<8>(0h80)) connect x1_nodeOut_1.a.bits.address, _nodeOut_a_bits_address_T_2 node _nodeIn_b_bits_address_mux_matches_T_8 = xor(inclusive_cache_bank_sched_2.io.in.b.bits.address, UInt<1>(0h0)) node _nodeIn_b_bits_address_mux_matches_T_9 = cvt(_nodeIn_b_bits_address_mux_matches_T_8) node _nodeIn_b_bits_address_mux_matches_T_10 = and(_nodeIn_b_bits_address_mux_matches_T_9, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_mux_matches_T_11 = asSInt(_nodeIn_b_bits_address_mux_matches_T_10) node nodeIn_b_bits_address_mux_0_1_2 = eq(_nodeIn_b_bits_address_mux_matches_T_11, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_T_2 = or(inclusive_cache_bank_sched_2.io.in.b.bits.address, UInt<8>(0h80)) connect nodeIn_2.b.bits.address, _nodeIn_b_bits_address_T_2 node _nodeOut_c_bits_address_mux_matches_T_8 = xor(inclusive_cache_bank_sched_2.io.out.c.bits.address, UInt<1>(0h0)) node _nodeOut_c_bits_address_mux_matches_T_9 = cvt(_nodeOut_c_bits_address_mux_matches_T_8) node _nodeOut_c_bits_address_mux_matches_T_10 = and(_nodeOut_c_bits_address_mux_matches_T_9, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_mux_matches_T_11 = asSInt(_nodeOut_c_bits_address_mux_matches_T_10) node nodeOut_c_bits_address_mux_0_1_2 = eq(_nodeOut_c_bits_address_mux_matches_T_11, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_T_2 = or(inclusive_cache_bank_sched_2.io.out.c.bits.address, UInt<8>(0h80)) connect x1_nodeOut_1.c.bits.address, _nodeOut_c_bits_address_T_2 inst inclusive_cache_bank_sched_3 of InclusiveCacheBankScheduler_3 connect inclusive_cache_bank_sched_3.clock, clock connect inclusive_cache_bank_sched_3.reset, reset connect inclusive_cache_bank_sched_3.io.in, nodeIn_3 connect x1_nodeOut_2.e.bits, inclusive_cache_bank_sched_3.io.out.e.bits connect x1_nodeOut_2.e.valid, inclusive_cache_bank_sched_3.io.out.e.valid connect inclusive_cache_bank_sched_3.io.out.e.ready, x1_nodeOut_2.e.ready connect inclusive_cache_bank_sched_3.io.out.d, x1_nodeOut_2.d connect x1_nodeOut_2.c.bits, inclusive_cache_bank_sched_3.io.out.c.bits connect x1_nodeOut_2.c.valid, inclusive_cache_bank_sched_3.io.out.c.valid connect inclusive_cache_bank_sched_3.io.out.c.ready, x1_nodeOut_2.c.ready connect inclusive_cache_bank_sched_3.io.out.b, x1_nodeOut_2.b connect x1_nodeOut_2.a.bits, inclusive_cache_bank_sched_3.io.out.a.bits connect x1_nodeOut_2.a.valid, inclusive_cache_bank_sched_3.io.out.a.valid connect inclusive_cache_bank_sched_3.io.out.a.ready, x1_nodeOut_2.a.ready invalidate inclusive_cache_bank_sched_3.io.ways[0] invalidate inclusive_cache_bank_sched_3.io.ways[1] invalidate inclusive_cache_bank_sched_3.io.ways[2] invalidate inclusive_cache_bank_sched_3.io.ways[3] invalidate inclusive_cache_bank_sched_3.io.ways[4] invalidate inclusive_cache_bank_sched_3.io.ways[5] invalidate inclusive_cache_bank_sched_3.io.ways[6] invalidate inclusive_cache_bank_sched_3.io.ways[7] invalidate inclusive_cache_bank_sched_3.io.ways[8] invalidate inclusive_cache_bank_sched_3.io.ways[9] invalidate inclusive_cache_bank_sched_3.io.ways[10] invalidate inclusive_cache_bank_sched_3.io.ways[11] invalidate inclusive_cache_bank_sched_3.io.ways[12] invalidate inclusive_cache_bank_sched_3.io.divs[0] invalidate inclusive_cache_bank_sched_3.io.divs[1] invalidate inclusive_cache_bank_sched_3.io.divs[2] invalidate inclusive_cache_bank_sched_3.io.divs[3] invalidate inclusive_cache_bank_sched_3.io.divs[4] invalidate inclusive_cache_bank_sched_3.io.divs[5] invalidate inclusive_cache_bank_sched_3.io.divs[6] invalidate inclusive_cache_bank_sched_3.io.divs[7] invalidate inclusive_cache_bank_sched_3.io.divs[8] invalidate inclusive_cache_bank_sched_3.io.divs[9] invalidate inclusive_cache_bank_sched_3.io.divs[10] invalidate inclusive_cache_bank_sched_3.io.divs[11] invalidate inclusive_cache_bank_sched_3.io.divs[12] connect inclusive_cache_bank_sched_3.io.req.valid, UInt<1>(0h0) connect inclusive_cache_bank_sched_3.io.req.bits.address, UInt<1>(0h0) connect inclusive_cache_bank_sched_3.io.resp.ready, UInt<1>(0h1) node _nodeOut_a_bits_address_mux_matches_T_12 = xor(inclusive_cache_bank_sched_3.io.out.a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_address_mux_matches_T_13 = cvt(_nodeOut_a_bits_address_mux_matches_T_12) node _nodeOut_a_bits_address_mux_matches_T_14 = and(_nodeOut_a_bits_address_mux_matches_T_13, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_mux_matches_T_15 = asSInt(_nodeOut_a_bits_address_mux_matches_T_14) node nodeOut_a_bits_address_mux_0_1_3 = eq(_nodeOut_a_bits_address_mux_matches_T_15, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_T_3 = or(inclusive_cache_bank_sched_3.io.out.a.bits.address, UInt<8>(0hc0)) connect x1_nodeOut_2.a.bits.address, _nodeOut_a_bits_address_T_3 node _nodeIn_b_bits_address_mux_matches_T_12 = xor(inclusive_cache_bank_sched_3.io.in.b.bits.address, UInt<1>(0h0)) node _nodeIn_b_bits_address_mux_matches_T_13 = cvt(_nodeIn_b_bits_address_mux_matches_T_12) node _nodeIn_b_bits_address_mux_matches_T_14 = and(_nodeIn_b_bits_address_mux_matches_T_13, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_mux_matches_T_15 = asSInt(_nodeIn_b_bits_address_mux_matches_T_14) node nodeIn_b_bits_address_mux_0_1_3 = eq(_nodeIn_b_bits_address_mux_matches_T_15, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_T_3 = or(inclusive_cache_bank_sched_3.io.in.b.bits.address, UInt<8>(0hc0)) connect nodeIn_3.b.bits.address, _nodeIn_b_bits_address_T_3 node _nodeOut_c_bits_address_mux_matches_T_12 = xor(inclusive_cache_bank_sched_3.io.out.c.bits.address, UInt<1>(0h0)) node _nodeOut_c_bits_address_mux_matches_T_13 = cvt(_nodeOut_c_bits_address_mux_matches_T_12) node _nodeOut_c_bits_address_mux_matches_T_14 = and(_nodeOut_c_bits_address_mux_matches_T_13, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_mux_matches_T_15 = asSInt(_nodeOut_c_bits_address_mux_matches_T_14) node nodeOut_c_bits_address_mux_0_1_3 = eq(_nodeOut_c_bits_address_mux_matches_T_15, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_T_3 = or(inclusive_cache_bank_sched_3.io.out.c.bits.address, UInt<8>(0hc0)) connect x1_nodeOut_2.c.bits.address, _nodeOut_c_bits_address_T_3 connect ctrls.io.flush_req.ready, UInt<1>(0h0) connect ctrls.io.flush_resp, UInt<1>(0h0) connect ctrls.io.flush_match, UInt<1>(0h0) node _contained_T = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000000)) node _contained_T_1 = cvt(_contained_T) node _contained_T_2 = and(_contained_T_1, asSInt(UInt<29>(0h100000c0))) node _contained_T_3 = asSInt(_contained_T_2) node _contained_T_4 = eq(_contained_T_3, asSInt(UInt<1>(0h0))) node _contained_T_5 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000000)) node _contained_T_6 = cvt(_contained_T_5) node _contained_T_7 = and(_contained_T_6, asSInt(UInt<17>(0h100c0))) node _contained_T_8 = asSInt(_contained_T_7) node _contained_T_9 = eq(_contained_T_8, asSInt(UInt<1>(0h0))) node contained = or(_contained_T_4, _contained_T_9) when contained : connect ctrls.io.flush_match, UInt<1>(0h1) node _inclusive_cache_bank_sched_io_req_valid_T = and(contained, ctrls.io.flush_req.valid) connect inclusive_cache_bank_sched.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T connect inclusive_cache_bank_sched.io.req.bits.address, ctrls.io.flush_req.bits node _T = and(contained, inclusive_cache_bank_sched.io.req.ready) when _T : connect ctrls.io.flush_req.ready, UInt<1>(0h1) when inclusive_cache_bank_sched.io.resp.valid : connect ctrls.io.flush_resp, UInt<1>(0h1) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1) node _contained_T_10 = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000040)) node _contained_T_11 = cvt(_contained_T_10) node _contained_T_12 = and(_contained_T_11, asSInt(UInt<29>(0h100000c0))) node _contained_T_13 = asSInt(_contained_T_12) node _contained_T_14 = eq(_contained_T_13, asSInt(UInt<1>(0h0))) node _contained_T_15 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000040)) node _contained_T_16 = cvt(_contained_T_15) node _contained_T_17 = and(_contained_T_16, asSInt(UInt<17>(0h100c0))) node _contained_T_18 = asSInt(_contained_T_17) node _contained_T_19 = eq(_contained_T_18, asSInt(UInt<1>(0h0))) node contained_1 = or(_contained_T_14, _contained_T_19) when contained_1 : connect ctrls.io.flush_match, UInt<1>(0h1) node _inclusive_cache_bank_sched_io_req_valid_T_1 = and(contained_1, ctrls.io.flush_req.valid) connect inclusive_cache_bank_sched_1.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T_1 connect inclusive_cache_bank_sched_1.io.req.bits.address, ctrls.io.flush_req.bits node _T_1 = and(contained_1, inclusive_cache_bank_sched_1.io.req.ready) when _T_1 : connect ctrls.io.flush_req.ready, UInt<1>(0h1) when inclusive_cache_bank_sched_1.io.resp.valid : connect ctrls.io.flush_resp, UInt<1>(0h1) connect inclusive_cache_bank_sched_1.io.resp.ready, UInt<1>(0h1) node _contained_T_20 = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000080)) node _contained_T_21 = cvt(_contained_T_20) node _contained_T_22 = and(_contained_T_21, asSInt(UInt<29>(0h100000c0))) node _contained_T_23 = asSInt(_contained_T_22) node _contained_T_24 = eq(_contained_T_23, asSInt(UInt<1>(0h0))) node _contained_T_25 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000080)) node _contained_T_26 = cvt(_contained_T_25) node _contained_T_27 = and(_contained_T_26, asSInt(UInt<17>(0h100c0))) node _contained_T_28 = asSInt(_contained_T_27) node _contained_T_29 = eq(_contained_T_28, asSInt(UInt<1>(0h0))) node contained_2 = or(_contained_T_24, _contained_T_29) when contained_2 : connect ctrls.io.flush_match, UInt<1>(0h1) node _inclusive_cache_bank_sched_io_req_valid_T_2 = and(contained_2, ctrls.io.flush_req.valid) connect inclusive_cache_bank_sched_2.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T_2 connect inclusive_cache_bank_sched_2.io.req.bits.address, ctrls.io.flush_req.bits node _T_2 = and(contained_2, inclusive_cache_bank_sched_2.io.req.ready) when _T_2 : connect ctrls.io.flush_req.ready, UInt<1>(0h1) when inclusive_cache_bank_sched_2.io.resp.valid : connect ctrls.io.flush_resp, UInt<1>(0h1) connect inclusive_cache_bank_sched_2.io.resp.ready, UInt<1>(0h1) node _contained_T_30 = xor(ctrls.io.flush_req.bits, UInt<32>(0h800000c0)) node _contained_T_31 = cvt(_contained_T_30) node _contained_T_32 = and(_contained_T_31, asSInt(UInt<29>(0h100000c0))) node _contained_T_33 = asSInt(_contained_T_32) node _contained_T_34 = eq(_contained_T_33, asSInt(UInt<1>(0h0))) node _contained_T_35 = xor(ctrls.io.flush_req.bits, UInt<28>(0h80000c0)) node _contained_T_36 = cvt(_contained_T_35) node _contained_T_37 = and(_contained_T_36, asSInt(UInt<17>(0h100c0))) node _contained_T_38 = asSInt(_contained_T_37) node _contained_T_39 = eq(_contained_T_38, asSInt(UInt<1>(0h0))) node contained_3 = or(_contained_T_34, _contained_T_39) when contained_3 : connect ctrls.io.flush_match, UInt<1>(0h1) node _inclusive_cache_bank_sched_io_req_valid_T_3 = and(contained_3, ctrls.io.flush_req.valid) connect inclusive_cache_bank_sched_3.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T_3 connect inclusive_cache_bank_sched_3.io.req.bits.address, ctrls.io.flush_req.bits node _T_3 = and(contained_3, inclusive_cache_bank_sched_3.io.req.ready) when _T_3 : connect ctrls.io.flush_req.ready, UInt<1>(0h1) when inclusive_cache_bank_sched_3.io.resp.valid : connect ctrls.io.flush_resp, UInt<1>(0h1) connect inclusive_cache_bank_sched_3.io.resp.ready, UInt<1>(0h1)
module InclusiveCache( // @[InclusiveCache.scala:108:9] input clock, // @[InclusiveCache.scala:108:9] input reset, // @[InclusiveCache.scala:108:9] output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_3_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_3_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_3_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_3_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_3_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_2_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_2_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_2_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_2_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_2_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_3_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_3_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_3_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_3_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_3_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_2_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_2_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_2_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_2_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_2_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire _inclusive_cache_bank_sched_3_io_in_a_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_3_io_in_b_valid; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_3_io_in_b_bits_param; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_3_io_in_b_bits_source; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_3_io_in_b_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_3_io_in_c_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_3_io_in_d_valid; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_3_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_3_io_in_d_bits_param; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_3_io_in_d_bits_size; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_3_io_in_d_bits_source; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_3_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_3_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_3_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_3_io_out_a_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_3_io_out_c_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_3_io_req_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_3_io_resp_valid; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_in_a_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_in_b_valid; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_2_io_in_b_bits_param; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_2_io_in_b_bits_source; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_2_io_in_b_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_in_c_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_in_d_valid; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_2_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_2_io_in_d_bits_param; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_2_io_in_d_bits_size; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_2_io_in_d_bits_source; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_2_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_2_io_out_a_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_2_io_out_c_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_req_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_2_io_resp_valid; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_in_a_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_in_b_valid; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_1_io_in_b_bits_param; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_1_io_in_b_bits_source; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_1_io_in_b_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_in_c_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_in_d_valid; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_1_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_1_io_in_d_bits_param; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_1_io_in_d_bits_size; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_1_io_in_d_bits_source; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_1_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_1_io_out_a_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_1_io_out_c_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_req_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_1_io_resp_valid; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_in_a_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_in_b_valid; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_io_in_b_bits_param; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_io_in_b_bits_source; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_in_c_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_in_d_valid; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29] wire [1:0] _inclusive_cache_bank_sched_io_in_d_bits_param; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_size; // @[InclusiveCache.scala:137:29] wire [5:0] _inclusive_cache_bank_sched_io_in_d_bits_source; // @[InclusiveCache.scala:137:29] wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29] wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43] wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43] wire [31:0] nodeIn_1_b_bits_address = {_inclusive_cache_bank_sched_1_io_in_b_bits_address[31:7], _inclusive_cache_bank_sched_1_io_in_b_bits_address[6:0] | 7'h40}; // @[Parameters.scala:248:14] wire [31:0] nodeIn_2_b_bits_address = {_inclusive_cache_bank_sched_2_io_in_b_bits_address[31:8], _inclusive_cache_bank_sched_2_io_in_b_bits_address[7:0] | 8'h80}; // @[Parameters.scala:248:14] wire [31:0] nodeIn_3_b_bits_address = {_inclusive_cache_bank_sched_3_io_in_b_bits_address[31:8], _inclusive_cache_bank_sched_3_io_in_b_bits_address[7:0] | 8'hC0}; // @[Parameters.scala:248:14] wire contained = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:28] ^ 4'h8, _ctrls_io_flush_req_bits[7:6]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:16] ^ 12'h800, _ctrls_io_flush_req_bits[7:6]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}] wire [25:0] _GEN = _ctrls_io_flush_req_bits[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31] wire [21:0] _GEN_0 = _ctrls_io_flush_req_bits[27:6] ^ 22'h200001; // @[Parameters.scala:137:31] wire contained_1 = {_ctrls_io_flush_req_bits[63:32], _GEN[25:22], _GEN[1:0]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _GEN_0[21:10], _GEN_0[1:0]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}] wire [25:0] _GEN_1 = _ctrls_io_flush_req_bits[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31] wire [21:0] _GEN_2 = _ctrls_io_flush_req_bits[27:6] ^ 22'h200002; // @[Parameters.scala:137:31] wire contained_2 = {_ctrls_io_flush_req_bits[63:32], _GEN_1[25:22], _GEN_1[1:0]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _GEN_2[21:10], _GEN_2[1:0]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}] wire [25:0] _GEN_3 = _ctrls_io_flush_req_bits[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31] wire [21:0] _GEN_4 = _ctrls_io_flush_req_bits[27:6] ^ 22'h200003; // @[Parameters.scala:137:31] wire contained_3 = {_ctrls_io_flush_req_bits[63:32], _GEN_3[25:22], _GEN_3[1:0]} == 38'h0 | {_ctrls_io_flush_req_bits[63:28], _GEN_4[21:10], _GEN_4[1:0]} == 50'h0; // @[Parameters.scala:137:{31,41,46,59}] InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43] .clock (clock), .reset (reset), .auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready), .auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid), .auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode), .auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param), .auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size), .auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source), .auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address), .auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask), .auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data), .auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt), .auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready), .auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid), .auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode), .auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size), .auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source), .auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data), .io_flush_match (contained_3 | contained_2 | contained_1 | contained), // @[InclusiveCache.scala:169:67, :170:{26,55}] .io_flush_req_ready (contained_3 & _inclusive_cache_bank_sched_3_io_req_ready | contained_2 & _inclusive_cache_bank_sched_2_io_req_ready | contained_1 & _inclusive_cache_bank_sched_1_io_req_ready | contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:{25,48,81}] .io_flush_req_valid (_ctrls_io_flush_req_valid), .io_flush_req_bits (_ctrls_io_flush_req_bits), .io_flush_resp (_inclusive_cache_bank_sched_3_io_resp_valid | _inclusive_cache_bank_sched_2_io_resp_valid | _inclusive_cache_bank_sched_1_io_resp_valid | _inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29, :176:{36,64}] ); // @[InclusiveCache.scala:103:43] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_io_in_a_ready), // @[InclusiveCache.scala:137:29] .io_in_a_valid (auto_in_0_a_valid), .io_in_a_bits_opcode (auto_in_0_a_bits_opcode), .io_in_a_bits_param (auto_in_0_a_bits_param), .io_in_a_bits_size (auto_in_0_a_bits_size), .io_in_a_bits_source (auto_in_0_a_bits_source), .io_in_a_bits_address (auto_in_0_a_bits_address), .io_in_a_bits_mask (auto_in_0_a_bits_mask), .io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt), .io_in_b_ready (auto_in_0_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_io_in_b_valid), // @[InclusiveCache.scala:137:29] .io_in_b_bits_param (_inclusive_cache_bank_sched_io_in_b_bits_param), // @[InclusiveCache.scala:137:29] .io_in_b_bits_source (_inclusive_cache_bank_sched_io_in_b_bits_source), // @[InclusiveCache.scala:137:29] .io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address), // @[InclusiveCache.scala:137:29] .io_in_c_ready (_inclusive_cache_bank_sched_io_in_c_ready), // @[InclusiveCache.scala:137:29] .io_in_c_valid (auto_in_0_c_valid), .io_in_c_bits_opcode (auto_in_0_c_bits_opcode), .io_in_c_bits_param (auto_in_0_c_bits_param), .io_in_c_bits_size (auto_in_0_c_bits_size), .io_in_c_bits_source (auto_in_0_c_bits_source), .io_in_c_bits_address (auto_in_0_c_bits_address), .io_in_c_bits_corrupt (auto_in_0_c_bits_corrupt), .io_in_d_ready (auto_in_0_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_io_in_d_valid), // @[InclusiveCache.scala:137:29] .io_in_d_bits_opcode (_inclusive_cache_bank_sched_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29] .io_in_d_bits_param (_inclusive_cache_bank_sched_io_in_d_bits_param), // @[InclusiveCache.scala:137:29] .io_in_d_bits_size (_inclusive_cache_bank_sched_io_in_d_bits_size), // @[InclusiveCache.scala:137:29] .io_in_d_bits_source (_inclusive_cache_bank_sched_io_in_d_bits_source), // @[InclusiveCache.scala:137:29] .io_in_d_bits_sink (_inclusive_cache_bank_sched_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29] .io_in_d_bits_denied (_inclusive_cache_bank_sched_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29] .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29] .io_in_e_valid (auto_in_0_e_valid), .io_in_e_bits_sink (auto_in_0_e_bits_sink) ); // @[Nodes.scala:27:25] TLMonitor_41 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_1_io_in_a_ready), // @[InclusiveCache.scala:137:29] .io_in_a_valid (auto_in_1_a_valid), .io_in_a_bits_opcode (auto_in_1_a_bits_opcode), .io_in_a_bits_param (auto_in_1_a_bits_param), .io_in_a_bits_size (auto_in_1_a_bits_size), .io_in_a_bits_source (auto_in_1_a_bits_source), .io_in_a_bits_address (auto_in_1_a_bits_address), .io_in_a_bits_mask (auto_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt), .io_in_b_ready (auto_in_1_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_1_io_in_b_valid), // @[InclusiveCache.scala:137:29] .io_in_b_bits_param (_inclusive_cache_bank_sched_1_io_in_b_bits_param), // @[InclusiveCache.scala:137:29] .io_in_b_bits_source (_inclusive_cache_bank_sched_1_io_in_b_bits_source), // @[InclusiveCache.scala:137:29] .io_in_b_bits_address (nodeIn_1_b_bits_address), // @[Parameters.scala:248:14] .io_in_c_ready (_inclusive_cache_bank_sched_1_io_in_c_ready), // @[InclusiveCache.scala:137:29] .io_in_c_valid (auto_in_1_c_valid), .io_in_c_bits_opcode (auto_in_1_c_bits_opcode), .io_in_c_bits_param (auto_in_1_c_bits_param), .io_in_c_bits_size (auto_in_1_c_bits_size), .io_in_c_bits_source (auto_in_1_c_bits_source), .io_in_c_bits_address (auto_in_1_c_bits_address), .io_in_c_bits_corrupt (auto_in_1_c_bits_corrupt), .io_in_d_ready (auto_in_1_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_1_io_in_d_valid), // @[InclusiveCache.scala:137:29] .io_in_d_bits_opcode (_inclusive_cache_bank_sched_1_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29] .io_in_d_bits_param (_inclusive_cache_bank_sched_1_io_in_d_bits_param), // @[InclusiveCache.scala:137:29] .io_in_d_bits_size (_inclusive_cache_bank_sched_1_io_in_d_bits_size), // @[InclusiveCache.scala:137:29] .io_in_d_bits_source (_inclusive_cache_bank_sched_1_io_in_d_bits_source), // @[InclusiveCache.scala:137:29] .io_in_d_bits_sink (_inclusive_cache_bank_sched_1_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29] .io_in_d_bits_denied (_inclusive_cache_bank_sched_1_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29] .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_1_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29] .io_in_e_valid (auto_in_1_e_valid), .io_in_e_bits_sink (auto_in_1_e_bits_sink) ); // @[Nodes.scala:27:25] TLMonitor_42 monitor_2 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_2_io_in_a_ready), // @[InclusiveCache.scala:137:29] .io_in_a_valid (auto_in_2_a_valid), .io_in_a_bits_opcode (auto_in_2_a_bits_opcode), .io_in_a_bits_param (auto_in_2_a_bits_param), .io_in_a_bits_size (auto_in_2_a_bits_size), .io_in_a_bits_source (auto_in_2_a_bits_source), .io_in_a_bits_address (auto_in_2_a_bits_address), .io_in_a_bits_mask (auto_in_2_a_bits_mask), .io_in_a_bits_corrupt (auto_in_2_a_bits_corrupt), .io_in_b_ready (auto_in_2_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_2_io_in_b_valid), // @[InclusiveCache.scala:137:29] .io_in_b_bits_param (_inclusive_cache_bank_sched_2_io_in_b_bits_param), // @[InclusiveCache.scala:137:29] .io_in_b_bits_source (_inclusive_cache_bank_sched_2_io_in_b_bits_source), // @[InclusiveCache.scala:137:29] .io_in_b_bits_address (nodeIn_2_b_bits_address), // @[Parameters.scala:248:14] .io_in_c_ready (_inclusive_cache_bank_sched_2_io_in_c_ready), // @[InclusiveCache.scala:137:29] .io_in_c_valid (auto_in_2_c_valid), .io_in_c_bits_opcode (auto_in_2_c_bits_opcode), .io_in_c_bits_param (auto_in_2_c_bits_param), .io_in_c_bits_size (auto_in_2_c_bits_size), .io_in_c_bits_source (auto_in_2_c_bits_source), .io_in_c_bits_address (auto_in_2_c_bits_address), .io_in_c_bits_corrupt (auto_in_2_c_bits_corrupt), .io_in_d_ready (auto_in_2_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_2_io_in_d_valid), // @[InclusiveCache.scala:137:29] .io_in_d_bits_opcode (_inclusive_cache_bank_sched_2_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29] .io_in_d_bits_param (_inclusive_cache_bank_sched_2_io_in_d_bits_param), // @[InclusiveCache.scala:137:29] .io_in_d_bits_size (_inclusive_cache_bank_sched_2_io_in_d_bits_size), // @[InclusiveCache.scala:137:29] .io_in_d_bits_source (_inclusive_cache_bank_sched_2_io_in_d_bits_source), // @[InclusiveCache.scala:137:29] .io_in_d_bits_sink (_inclusive_cache_bank_sched_2_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29] .io_in_d_bits_denied (_inclusive_cache_bank_sched_2_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29] .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_2_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29] .io_in_e_valid (auto_in_2_e_valid), .io_in_e_bits_sink (auto_in_2_e_bits_sink) ); // @[Nodes.scala:27:25] TLMonitor_43 monitor_3 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_3_io_in_a_ready), // @[InclusiveCache.scala:137:29] .io_in_a_valid (auto_in_3_a_valid), .io_in_a_bits_opcode (auto_in_3_a_bits_opcode), .io_in_a_bits_param (auto_in_3_a_bits_param), .io_in_a_bits_size (auto_in_3_a_bits_size), .io_in_a_bits_source (auto_in_3_a_bits_source), .io_in_a_bits_address (auto_in_3_a_bits_address), .io_in_a_bits_mask (auto_in_3_a_bits_mask), .io_in_a_bits_corrupt (auto_in_3_a_bits_corrupt), .io_in_b_ready (auto_in_3_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_3_io_in_b_valid), // @[InclusiveCache.scala:137:29] .io_in_b_bits_param (_inclusive_cache_bank_sched_3_io_in_b_bits_param), // @[InclusiveCache.scala:137:29] .io_in_b_bits_source (_inclusive_cache_bank_sched_3_io_in_b_bits_source), // @[InclusiveCache.scala:137:29] .io_in_b_bits_address (nodeIn_3_b_bits_address), // @[Parameters.scala:248:14] .io_in_c_ready (_inclusive_cache_bank_sched_3_io_in_c_ready), // @[InclusiveCache.scala:137:29] .io_in_c_valid (auto_in_3_c_valid), .io_in_c_bits_opcode (auto_in_3_c_bits_opcode), .io_in_c_bits_param (auto_in_3_c_bits_param), .io_in_c_bits_size (auto_in_3_c_bits_size), .io_in_c_bits_source (auto_in_3_c_bits_source), .io_in_c_bits_address (auto_in_3_c_bits_address), .io_in_c_bits_corrupt (auto_in_3_c_bits_corrupt), .io_in_d_ready (auto_in_3_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_3_io_in_d_valid), // @[InclusiveCache.scala:137:29] .io_in_d_bits_opcode (_inclusive_cache_bank_sched_3_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29] .io_in_d_bits_param (_inclusive_cache_bank_sched_3_io_in_d_bits_param), // @[InclusiveCache.scala:137:29] .io_in_d_bits_size (_inclusive_cache_bank_sched_3_io_in_d_bits_size), // @[InclusiveCache.scala:137:29] .io_in_d_bits_source (_inclusive_cache_bank_sched_3_io_in_d_bits_source), // @[InclusiveCache.scala:137:29] .io_in_d_bits_sink (_inclusive_cache_bank_sched_3_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29] .io_in_d_bits_denied (_inclusive_cache_bank_sched_3_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29] .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_3_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29] .io_in_e_valid (auto_in_3_e_valid), .io_in_e_bits_sink (auto_in_3_e_bits_sink) ); // @[Nodes.scala:27:25] InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_io_in_a_ready), .io_in_a_valid (auto_in_0_a_valid), .io_in_a_bits_opcode (auto_in_0_a_bits_opcode), .io_in_a_bits_param (auto_in_0_a_bits_param), .io_in_a_bits_size (auto_in_0_a_bits_size), .io_in_a_bits_source (auto_in_0_a_bits_source), .io_in_a_bits_address (auto_in_0_a_bits_address), .io_in_a_bits_mask (auto_in_0_a_bits_mask), .io_in_a_bits_data (auto_in_0_a_bits_data), .io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt), .io_in_b_ready (auto_in_0_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_io_in_b_valid), .io_in_b_bits_param (_inclusive_cache_bank_sched_io_in_b_bits_param), .io_in_b_bits_source (_inclusive_cache_bank_sched_io_in_b_bits_source), .io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address), .io_in_c_ready (_inclusive_cache_bank_sched_io_in_c_ready), .io_in_c_valid (auto_in_0_c_valid), .io_in_c_bits_opcode (auto_in_0_c_bits_opcode), .io_in_c_bits_param (auto_in_0_c_bits_param), .io_in_c_bits_size (auto_in_0_c_bits_size), .io_in_c_bits_source (auto_in_0_c_bits_source), .io_in_c_bits_address (auto_in_0_c_bits_address), .io_in_c_bits_data (auto_in_0_c_bits_data), .io_in_c_bits_corrupt (auto_in_0_c_bits_corrupt), .io_in_d_ready (auto_in_0_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_io_in_d_valid), .io_in_d_bits_opcode (_inclusive_cache_bank_sched_io_in_d_bits_opcode), .io_in_d_bits_param (_inclusive_cache_bank_sched_io_in_d_bits_param), .io_in_d_bits_size (_inclusive_cache_bank_sched_io_in_d_bits_size), .io_in_d_bits_source (_inclusive_cache_bank_sched_io_in_d_bits_source), .io_in_d_bits_sink (_inclusive_cache_bank_sched_io_in_d_bits_sink), .io_in_d_bits_denied (_inclusive_cache_bank_sched_io_in_d_bits_denied), .io_in_d_bits_data (auto_in_0_d_bits_data), .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_io_in_d_bits_corrupt), .io_in_e_valid (auto_in_0_e_valid), .io_in_e_bits_sink (auto_in_0_e_bits_sink), .io_out_a_ready (auto_out_0_a_ready), .io_out_a_valid (auto_out_0_a_valid), .io_out_a_bits_opcode (auto_out_0_a_bits_opcode), .io_out_a_bits_param (auto_out_0_a_bits_param), .io_out_a_bits_size (auto_out_0_a_bits_size), .io_out_a_bits_source (auto_out_0_a_bits_source), .io_out_a_bits_address (auto_out_0_a_bits_address), .io_out_a_bits_mask (auto_out_0_a_bits_mask), .io_out_a_bits_data (auto_out_0_a_bits_data), .io_out_a_bits_corrupt (auto_out_0_a_bits_corrupt), .io_out_c_ready (auto_out_0_c_ready), .io_out_c_valid (auto_out_0_c_valid), .io_out_c_bits_opcode (auto_out_0_c_bits_opcode), .io_out_c_bits_param (auto_out_0_c_bits_param), .io_out_c_bits_size (auto_out_0_c_bits_size), .io_out_c_bits_source (auto_out_0_c_bits_source), .io_out_c_bits_address (auto_out_0_c_bits_address), .io_out_c_bits_data (auto_out_0_c_bits_data), .io_out_c_bits_corrupt (auto_out_0_c_bits_corrupt), .io_out_d_ready (auto_out_0_d_ready), .io_out_d_valid (auto_out_0_d_valid), .io_out_d_bits_opcode (auto_out_0_d_bits_opcode), .io_out_d_bits_param (auto_out_0_d_bits_param), .io_out_d_bits_size (auto_out_0_d_bits_size), .io_out_d_bits_source (auto_out_0_d_bits_source), .io_out_d_bits_sink (auto_out_0_d_bits_sink), .io_out_d_bits_denied (auto_out_0_d_bits_denied), .io_out_d_bits_data (auto_out_0_d_bits_data), .io_out_d_bits_corrupt (auto_out_0_d_bits_corrupt), .io_out_e_valid (auto_out_0_e_valid), .io_out_e_bits_sink (auto_out_0_e_bits_sink), .io_req_ready (_inclusive_cache_bank_sched_io_req_ready), .io_req_valid (contained & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41] .io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31] .io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid) ); // @[InclusiveCache.scala:137:29] InclusiveCacheBankScheduler inclusive_cache_bank_sched_1 ( // @[InclusiveCache.scala:137:29] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_1_io_in_a_ready), .io_in_a_valid (auto_in_1_a_valid), .io_in_a_bits_opcode (auto_in_1_a_bits_opcode), .io_in_a_bits_param (auto_in_1_a_bits_param), .io_in_a_bits_size (auto_in_1_a_bits_size), .io_in_a_bits_source (auto_in_1_a_bits_source), .io_in_a_bits_address (auto_in_1_a_bits_address), .io_in_a_bits_mask (auto_in_1_a_bits_mask), .io_in_a_bits_data (auto_in_1_a_bits_data), .io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt), .io_in_b_ready (auto_in_1_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_1_io_in_b_valid), .io_in_b_bits_param (_inclusive_cache_bank_sched_1_io_in_b_bits_param), .io_in_b_bits_source (_inclusive_cache_bank_sched_1_io_in_b_bits_source), .io_in_b_bits_address (_inclusive_cache_bank_sched_1_io_in_b_bits_address), .io_in_c_ready (_inclusive_cache_bank_sched_1_io_in_c_ready), .io_in_c_valid (auto_in_1_c_valid), .io_in_c_bits_opcode (auto_in_1_c_bits_opcode), .io_in_c_bits_param (auto_in_1_c_bits_param), .io_in_c_bits_size (auto_in_1_c_bits_size), .io_in_c_bits_source (auto_in_1_c_bits_source), .io_in_c_bits_address (auto_in_1_c_bits_address), .io_in_c_bits_data (auto_in_1_c_bits_data), .io_in_c_bits_corrupt (auto_in_1_c_bits_corrupt), .io_in_d_ready (auto_in_1_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_1_io_in_d_valid), .io_in_d_bits_opcode (_inclusive_cache_bank_sched_1_io_in_d_bits_opcode), .io_in_d_bits_param (_inclusive_cache_bank_sched_1_io_in_d_bits_param), .io_in_d_bits_size (_inclusive_cache_bank_sched_1_io_in_d_bits_size), .io_in_d_bits_source (_inclusive_cache_bank_sched_1_io_in_d_bits_source), .io_in_d_bits_sink (_inclusive_cache_bank_sched_1_io_in_d_bits_sink), .io_in_d_bits_denied (_inclusive_cache_bank_sched_1_io_in_d_bits_denied), .io_in_d_bits_data (auto_in_1_d_bits_data), .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_1_io_in_d_bits_corrupt), .io_in_e_valid (auto_in_1_e_valid), .io_in_e_bits_sink (auto_in_1_e_bits_sink), .io_out_a_ready (auto_out_1_a_ready), .io_out_a_valid (auto_out_1_a_valid), .io_out_a_bits_opcode (auto_out_1_a_bits_opcode), .io_out_a_bits_param (auto_out_1_a_bits_param), .io_out_a_bits_size (auto_out_1_a_bits_size), .io_out_a_bits_source (auto_out_1_a_bits_source), .io_out_a_bits_address (_inclusive_cache_bank_sched_1_io_out_a_bits_address), .io_out_a_bits_mask (auto_out_1_a_bits_mask), .io_out_a_bits_data (auto_out_1_a_bits_data), .io_out_a_bits_corrupt (auto_out_1_a_bits_corrupt), .io_out_c_ready (auto_out_1_c_ready), .io_out_c_valid (auto_out_1_c_valid), .io_out_c_bits_opcode (auto_out_1_c_bits_opcode), .io_out_c_bits_param (auto_out_1_c_bits_param), .io_out_c_bits_size (auto_out_1_c_bits_size), .io_out_c_bits_source (auto_out_1_c_bits_source), .io_out_c_bits_address (_inclusive_cache_bank_sched_1_io_out_c_bits_address), .io_out_c_bits_data (auto_out_1_c_bits_data), .io_out_c_bits_corrupt (auto_out_1_c_bits_corrupt), .io_out_d_ready (auto_out_1_d_ready), .io_out_d_valid (auto_out_1_d_valid), .io_out_d_bits_opcode (auto_out_1_d_bits_opcode), .io_out_d_bits_param (auto_out_1_d_bits_param), .io_out_d_bits_size (auto_out_1_d_bits_size), .io_out_d_bits_source (auto_out_1_d_bits_source), .io_out_d_bits_sink (auto_out_1_d_bits_sink), .io_out_d_bits_denied (auto_out_1_d_bits_denied), .io_out_d_bits_data (auto_out_1_d_bits_data), .io_out_d_bits_corrupt (auto_out_1_d_bits_corrupt), .io_out_e_valid (auto_out_1_e_valid), .io_out_e_bits_sink (auto_out_1_e_bits_sink), .io_req_ready (_inclusive_cache_bank_sched_1_io_req_ready), .io_req_valid (contained_1 & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41] .io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31] .io_resp_valid (_inclusive_cache_bank_sched_1_io_resp_valid) ); // @[InclusiveCache.scala:137:29] InclusiveCacheBankScheduler inclusive_cache_bank_sched_2 ( // @[InclusiveCache.scala:137:29] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_2_io_in_a_ready), .io_in_a_valid (auto_in_2_a_valid), .io_in_a_bits_opcode (auto_in_2_a_bits_opcode), .io_in_a_bits_param (auto_in_2_a_bits_param), .io_in_a_bits_size (auto_in_2_a_bits_size), .io_in_a_bits_source (auto_in_2_a_bits_source), .io_in_a_bits_address (auto_in_2_a_bits_address), .io_in_a_bits_mask (auto_in_2_a_bits_mask), .io_in_a_bits_data (auto_in_2_a_bits_data), .io_in_a_bits_corrupt (auto_in_2_a_bits_corrupt), .io_in_b_ready (auto_in_2_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_2_io_in_b_valid), .io_in_b_bits_param (_inclusive_cache_bank_sched_2_io_in_b_bits_param), .io_in_b_bits_source (_inclusive_cache_bank_sched_2_io_in_b_bits_source), .io_in_b_bits_address (_inclusive_cache_bank_sched_2_io_in_b_bits_address), .io_in_c_ready (_inclusive_cache_bank_sched_2_io_in_c_ready), .io_in_c_valid (auto_in_2_c_valid), .io_in_c_bits_opcode (auto_in_2_c_bits_opcode), .io_in_c_bits_param (auto_in_2_c_bits_param), .io_in_c_bits_size (auto_in_2_c_bits_size), .io_in_c_bits_source (auto_in_2_c_bits_source), .io_in_c_bits_address (auto_in_2_c_bits_address), .io_in_c_bits_data (auto_in_2_c_bits_data), .io_in_c_bits_corrupt (auto_in_2_c_bits_corrupt), .io_in_d_ready (auto_in_2_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_2_io_in_d_valid), .io_in_d_bits_opcode (_inclusive_cache_bank_sched_2_io_in_d_bits_opcode), .io_in_d_bits_param (_inclusive_cache_bank_sched_2_io_in_d_bits_param), .io_in_d_bits_size (_inclusive_cache_bank_sched_2_io_in_d_bits_size), .io_in_d_bits_source (_inclusive_cache_bank_sched_2_io_in_d_bits_source), .io_in_d_bits_sink (_inclusive_cache_bank_sched_2_io_in_d_bits_sink), .io_in_d_bits_denied (_inclusive_cache_bank_sched_2_io_in_d_bits_denied), .io_in_d_bits_data (auto_in_2_d_bits_data), .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_2_io_in_d_bits_corrupt), .io_in_e_valid (auto_in_2_e_valid), .io_in_e_bits_sink (auto_in_2_e_bits_sink), .io_out_a_ready (auto_out_2_a_ready), .io_out_a_valid (auto_out_2_a_valid), .io_out_a_bits_opcode (auto_out_2_a_bits_opcode), .io_out_a_bits_param (auto_out_2_a_bits_param), .io_out_a_bits_size (auto_out_2_a_bits_size), .io_out_a_bits_source (auto_out_2_a_bits_source), .io_out_a_bits_address (_inclusive_cache_bank_sched_2_io_out_a_bits_address), .io_out_a_bits_mask (auto_out_2_a_bits_mask), .io_out_a_bits_data (auto_out_2_a_bits_data), .io_out_a_bits_corrupt (auto_out_2_a_bits_corrupt), .io_out_c_ready (auto_out_2_c_ready), .io_out_c_valid (auto_out_2_c_valid), .io_out_c_bits_opcode (auto_out_2_c_bits_opcode), .io_out_c_bits_param (auto_out_2_c_bits_param), .io_out_c_bits_size (auto_out_2_c_bits_size), .io_out_c_bits_source (auto_out_2_c_bits_source), .io_out_c_bits_address (_inclusive_cache_bank_sched_2_io_out_c_bits_address), .io_out_c_bits_data (auto_out_2_c_bits_data), .io_out_c_bits_corrupt (auto_out_2_c_bits_corrupt), .io_out_d_ready (auto_out_2_d_ready), .io_out_d_valid (auto_out_2_d_valid), .io_out_d_bits_opcode (auto_out_2_d_bits_opcode), .io_out_d_bits_param (auto_out_2_d_bits_param), .io_out_d_bits_size (auto_out_2_d_bits_size), .io_out_d_bits_source (auto_out_2_d_bits_source), .io_out_d_bits_sink (auto_out_2_d_bits_sink), .io_out_d_bits_denied (auto_out_2_d_bits_denied), .io_out_d_bits_data (auto_out_2_d_bits_data), .io_out_d_bits_corrupt (auto_out_2_d_bits_corrupt), .io_out_e_valid (auto_out_2_e_valid), .io_out_e_bits_sink (auto_out_2_e_bits_sink), .io_req_ready (_inclusive_cache_bank_sched_2_io_req_ready), .io_req_valid (contained_2 & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41] .io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31] .io_resp_valid (_inclusive_cache_bank_sched_2_io_resp_valid) ); // @[InclusiveCache.scala:137:29] InclusiveCacheBankScheduler inclusive_cache_bank_sched_3 ( // @[InclusiveCache.scala:137:29] .clock (clock), .reset (reset), .io_in_a_ready (_inclusive_cache_bank_sched_3_io_in_a_ready), .io_in_a_valid (auto_in_3_a_valid), .io_in_a_bits_opcode (auto_in_3_a_bits_opcode), .io_in_a_bits_param (auto_in_3_a_bits_param), .io_in_a_bits_size (auto_in_3_a_bits_size), .io_in_a_bits_source (auto_in_3_a_bits_source), .io_in_a_bits_address (auto_in_3_a_bits_address), .io_in_a_bits_mask (auto_in_3_a_bits_mask), .io_in_a_bits_data (auto_in_3_a_bits_data), .io_in_a_bits_corrupt (auto_in_3_a_bits_corrupt), .io_in_b_ready (auto_in_3_b_ready), .io_in_b_valid (_inclusive_cache_bank_sched_3_io_in_b_valid), .io_in_b_bits_param (_inclusive_cache_bank_sched_3_io_in_b_bits_param), .io_in_b_bits_source (_inclusive_cache_bank_sched_3_io_in_b_bits_source), .io_in_b_bits_address (_inclusive_cache_bank_sched_3_io_in_b_bits_address), .io_in_c_ready (_inclusive_cache_bank_sched_3_io_in_c_ready), .io_in_c_valid (auto_in_3_c_valid), .io_in_c_bits_opcode (auto_in_3_c_bits_opcode), .io_in_c_bits_param (auto_in_3_c_bits_param), .io_in_c_bits_size (auto_in_3_c_bits_size), .io_in_c_bits_source (auto_in_3_c_bits_source), .io_in_c_bits_address (auto_in_3_c_bits_address), .io_in_c_bits_data (auto_in_3_c_bits_data), .io_in_c_bits_corrupt (auto_in_3_c_bits_corrupt), .io_in_d_ready (auto_in_3_d_ready), .io_in_d_valid (_inclusive_cache_bank_sched_3_io_in_d_valid), .io_in_d_bits_opcode (_inclusive_cache_bank_sched_3_io_in_d_bits_opcode), .io_in_d_bits_param (_inclusive_cache_bank_sched_3_io_in_d_bits_param), .io_in_d_bits_size (_inclusive_cache_bank_sched_3_io_in_d_bits_size), .io_in_d_bits_source (_inclusive_cache_bank_sched_3_io_in_d_bits_source), .io_in_d_bits_sink (_inclusive_cache_bank_sched_3_io_in_d_bits_sink), .io_in_d_bits_denied (_inclusive_cache_bank_sched_3_io_in_d_bits_denied), .io_in_d_bits_data (auto_in_3_d_bits_data), .io_in_d_bits_corrupt (_inclusive_cache_bank_sched_3_io_in_d_bits_corrupt), .io_in_e_valid (auto_in_3_e_valid), .io_in_e_bits_sink (auto_in_3_e_bits_sink), .io_out_a_ready (auto_out_3_a_ready), .io_out_a_valid (auto_out_3_a_valid), .io_out_a_bits_opcode (auto_out_3_a_bits_opcode), .io_out_a_bits_param (auto_out_3_a_bits_param), .io_out_a_bits_size (auto_out_3_a_bits_size), .io_out_a_bits_source (auto_out_3_a_bits_source), .io_out_a_bits_address (_inclusive_cache_bank_sched_3_io_out_a_bits_address), .io_out_a_bits_mask (auto_out_3_a_bits_mask), .io_out_a_bits_data (auto_out_3_a_bits_data), .io_out_a_bits_corrupt (auto_out_3_a_bits_corrupt), .io_out_c_ready (auto_out_3_c_ready), .io_out_c_valid (auto_out_3_c_valid), .io_out_c_bits_opcode (auto_out_3_c_bits_opcode), .io_out_c_bits_param (auto_out_3_c_bits_param), .io_out_c_bits_size (auto_out_3_c_bits_size), .io_out_c_bits_source (auto_out_3_c_bits_source), .io_out_c_bits_address (_inclusive_cache_bank_sched_3_io_out_c_bits_address), .io_out_c_bits_data (auto_out_3_c_bits_data), .io_out_c_bits_corrupt (auto_out_3_c_bits_corrupt), .io_out_d_ready (auto_out_3_d_ready), .io_out_d_valid (auto_out_3_d_valid), .io_out_d_bits_opcode (auto_out_3_d_bits_opcode), .io_out_d_bits_param (auto_out_3_d_bits_param), .io_out_d_bits_size (auto_out_3_d_bits_size), .io_out_d_bits_source (auto_out_3_d_bits_source), .io_out_d_bits_sink (auto_out_3_d_bits_sink), .io_out_d_bits_denied (auto_out_3_d_bits_denied), .io_out_d_bits_data (auto_out_3_d_bits_data), .io_out_d_bits_corrupt (auto_out_3_d_bits_corrupt), .io_out_e_valid (auto_out_3_e_valid), .io_out_e_bits_sink (auto_out_3_e_bits_sink), .io_req_ready (_inclusive_cache_bank_sched_3_io_req_ready), .io_req_valid (contained_3 & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41] .io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31] .io_resp_valid (_inclusive_cache_bank_sched_3_io_resp_valid) ); // @[InclusiveCache.scala:137:29] assign auto_in_3_a_ready = _inclusive_cache_bank_sched_3_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_b_valid = _inclusive_cache_bank_sched_3_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_b_bits_param = _inclusive_cache_bank_sched_3_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_b_bits_source = _inclusive_cache_bank_sched_3_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_b_bits_address = nodeIn_3_b_bits_address; // @[Parameters.scala:248:14] assign auto_in_3_c_ready = _inclusive_cache_bank_sched_3_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_valid = _inclusive_cache_bank_sched_3_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_bits_opcode = _inclusive_cache_bank_sched_3_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_bits_param = _inclusive_cache_bank_sched_3_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_bits_size = _inclusive_cache_bank_sched_3_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_bits_source = _inclusive_cache_bank_sched_3_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_bits_sink = _inclusive_cache_bank_sched_3_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_bits_denied = _inclusive_cache_bank_sched_3_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_3_d_bits_corrupt = _inclusive_cache_bank_sched_3_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_a_ready = _inclusive_cache_bank_sched_2_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_b_valid = _inclusive_cache_bank_sched_2_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_b_bits_param = _inclusive_cache_bank_sched_2_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_b_bits_source = _inclusive_cache_bank_sched_2_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_b_bits_address = nodeIn_2_b_bits_address; // @[Parameters.scala:248:14] assign auto_in_2_c_ready = _inclusive_cache_bank_sched_2_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_valid = _inclusive_cache_bank_sched_2_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_bits_opcode = _inclusive_cache_bank_sched_2_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_bits_param = _inclusive_cache_bank_sched_2_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_bits_size = _inclusive_cache_bank_sched_2_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_bits_source = _inclusive_cache_bank_sched_2_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_bits_sink = _inclusive_cache_bank_sched_2_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_bits_denied = _inclusive_cache_bank_sched_2_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_2_d_bits_corrupt = _inclusive_cache_bank_sched_2_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_a_ready = _inclusive_cache_bank_sched_1_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_b_valid = _inclusive_cache_bank_sched_1_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_b_bits_param = _inclusive_cache_bank_sched_1_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_b_bits_source = _inclusive_cache_bank_sched_1_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_b_bits_address = nodeIn_1_b_bits_address; // @[Parameters.scala:248:14] assign auto_in_1_c_ready = _inclusive_cache_bank_sched_1_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_valid = _inclusive_cache_bank_sched_1_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_bits_opcode = _inclusive_cache_bank_sched_1_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_bits_param = _inclusive_cache_bank_sched_1_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_bits_size = _inclusive_cache_bank_sched_1_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_bits_source = _inclusive_cache_bank_sched_1_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_bits_sink = _inclusive_cache_bank_sched_1_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_bits_denied = _inclusive_cache_bank_sched_1_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_1_d_bits_corrupt = _inclusive_cache_bank_sched_1_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_a_ready = _inclusive_cache_bank_sched_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_b_valid = _inclusive_cache_bank_sched_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_b_bits_param = _inclusive_cache_bank_sched_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_b_bits_source = _inclusive_cache_bank_sched_io_in_b_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_b_bits_address = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_c_ready = _inclusive_cache_bank_sched_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_valid = _inclusive_cache_bank_sched_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_bits_opcode = _inclusive_cache_bank_sched_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_bits_param = _inclusive_cache_bank_sched_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_bits_size = _inclusive_cache_bank_sched_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_bits_source = _inclusive_cache_bank_sched_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_bits_sink = _inclusive_cache_bank_sched_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_bits_denied = _inclusive_cache_bank_sched_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29] assign auto_in_0_d_bits_corrupt = _inclusive_cache_bank_sched_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29] assign auto_out_3_a_bits_address = {_inclusive_cache_bank_sched_3_io_out_a_bits_address[31:8], _inclusive_cache_bank_sched_3_io_out_a_bits_address[7:0] | 8'hC0}; // @[Parameters.scala:248:14] assign auto_out_3_c_bits_address = {_inclusive_cache_bank_sched_3_io_out_c_bits_address[31:8], _inclusive_cache_bank_sched_3_io_out_c_bits_address[7:0] | 8'hC0}; // @[Parameters.scala:248:14] assign auto_out_2_a_bits_address = {_inclusive_cache_bank_sched_2_io_out_a_bits_address[31:8], _inclusive_cache_bank_sched_2_io_out_a_bits_address[7:0] | 8'h80}; // @[Parameters.scala:248:14] assign auto_out_2_c_bits_address = {_inclusive_cache_bank_sched_2_io_out_c_bits_address[31:8], _inclusive_cache_bank_sched_2_io_out_c_bits_address[7:0] | 8'h80}; // @[Parameters.scala:248:14] assign auto_out_1_a_bits_address = {_inclusive_cache_bank_sched_1_io_out_a_bits_address[31:7], _inclusive_cache_bank_sched_1_io_out_a_bits_address[6:0] | 7'h40}; // @[Parameters.scala:248:14] assign auto_out_1_c_bits_address = {_inclusive_cache_bank_sched_1_io_out_c_bits_address[31:7], _inclusive_cache_bank_sched_1_io_out_c_bits_address[6:0] | 7'h40}; // @[Parameters.scala:248:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_clint : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_CLINT connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready extmodule plusarg_reader_50 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_51 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLInterconnectCoupler_cbus_to_clint( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_CLINT fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_89 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_89( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module Tile_88 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_344 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_88( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_344 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_10 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} inst input_buffer of InputBuffer_10 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) inst route_arbiter of Arbiter6_RouteComputerReq_10 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<6>}[6], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_11 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_12 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_13 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_13 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_14 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_14 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_15 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_15 : connect states[5].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<6>, clock, reset, UInt<6>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}[6] wire vcalloc_vals : UInt<1>[6] node vcalloc_filter_lo_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[3]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[3]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_16, UInt<12>(0h800), UInt<12>(0h0)) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_15, UInt<12>(0h400), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_14, UInt<12>(0h200), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_13, UInt<12>(0h100), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_12, UInt<12>(0h80), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_11, UInt<12>(0h40), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_10, UInt<12>(0h20), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_9, UInt<12>(0h10), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_8, UInt<12>(0h8), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_7, UInt<12>(0h4), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_6, UInt<12>(0h2), _vcalloc_filter_T_26) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<12>(0h1), _vcalloc_filter_T_27) node _vcalloc_sel_T = bits(vcalloc_filter, 5, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 6) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_27 = and(io.router_req.ready, io.router_req.valid) when _T_27 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_28 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_29 = or(_T_28, vcalloc_vals[2]) node _T_30 = or(_T_29, vcalloc_vals[3]) node _T_31 = or(_T_30, vcalloc_vals[4]) node _T_32 = or(_T_31, vcalloc_vals[5]) when _T_32 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = bits(vcalloc_sel, 0, 0) node _mask_T_10 = bits(vcalloc_sel, 1, 1) node _mask_T_11 = bits(vcalloc_sel, 2, 2) node _mask_T_12 = bits(vcalloc_sel, 3, 3) node _mask_T_13 = bits(vcalloc_sel, 4, 4) node _mask_T_14 = bits(vcalloc_sel, 5, 5) node _mask_T_15 = mux(_mask_T_9, _mask_T_3, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_10, _mask_T_4, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_11, _mask_T_5, UInt<1>(0h0)) node _mask_T_18 = mux(_mask_T_12, _mask_T_6, UInt<1>(0h0)) node _mask_T_19 = mux(_mask_T_13, _mask_T_7, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_14, _mask_T_8, UInt<1>(0h0)) node _mask_T_21 = or(_mask_T_15, _mask_T_16) node _mask_T_22 = or(_mask_T_21, _mask_T_17) node _mask_T_23 = or(_mask_T_22, _mask_T_18) node _mask_T_24 = or(_mask_T_23, _mask_T_19) node _mask_T_25 = or(_mask_T_24, _mask_T_20) wire _mask_WIRE : UInt<6> connect _mask_WIRE, _mask_T_25 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_4 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[6] node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_14 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_11) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_20) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_21) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_22) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_38 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_44) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_60 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_68 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_63) node _io_vcalloc_req_bits_T_69 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_70 = or(_io_vcalloc_req_bits_T_69, _io_vcalloc_req_bits_T_65) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_70, _io_vcalloc_req_bits_T_66) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_71 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>[1] node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_76) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_77) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_9[0], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_9 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1] node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_90 = or(_io_vcalloc_req_bits_T_89, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_90, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_88) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_93 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_11 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_95) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_13 : UInt<3> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_14 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_113 = or(_io_vcalloc_req_bits_T_112, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_114 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_114, _io_vcalloc_req_bits_T_110) wire _io_vcalloc_req_bits_WIRE_15 : UInt<2> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_115 connect _io_vcalloc_req_bits_WIRE_14.egress_node_id, _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_120) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_121) wire _io_vcalloc_req_bits_WIRE_16 : UInt<4> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_126 connect _io_vcalloc_req_bits_WIRE_14.egress_node, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_133, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_132) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_137 connect _io_vcalloc_req_bits_WIRE_14.ingress_node_id, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_138 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_139 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_139) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_144, _io_vcalloc_req_bits_T_140) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_143) wire _io_vcalloc_req_bits_WIRE_18 : UInt<4> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_14.ingress_node, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_154 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_149, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_152) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_153) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_154) wire _io_vcalloc_req_bits_WIRE_19 : UInt<2> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_159 connect _io_vcalloc_req_bits_WIRE_14.vnet_id, _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_14 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].flow, states[1].flow node _T_33 = bits(vcalloc_sel, 1, 1) node _T_34 = and(vcalloc_vals[1], _T_33) node _T_35 = and(_T_34, io.vcalloc_req.ready) when _T_35 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].flow, states[2].flow node _T_36 = bits(vcalloc_sel, 2, 2) node _T_37 = and(vcalloc_vals[2], _T_36) node _T_38 = and(_T_37, io.vcalloc_req.ready) when _T_38 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].flow, states[3].flow node _T_39 = bits(vcalloc_sel, 3, 3) node _T_40 = and(vcalloc_vals[3], _T_39) node _T_41 = and(_T_40, io.vcalloc_req.ready) when _T_41 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].flow, states[4].flow node _T_42 = bits(vcalloc_sel, 4, 4) node _T_43 = and(vcalloc_vals[4], _T_42) node _T_44 = and(_T_43, io.vcalloc_req.ready) when _T_44 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].flow, states[5].flow node _T_45 = bits(vcalloc_sel, 5, 5) node _T_46 = and(vcalloc_vals[5], _T_45) node _T_47 = and(_T_46, io.vcalloc_req.ready) when _T_47 : connect states[5].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[3], _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(_io_debug_va_stall_T_3, _io_debug_va_stall_T_7) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 2, 0) node _io_debug_va_stall_T_10 = sub(_io_debug_va_stall_T_9, io.vcalloc_req.ready) node _io_debug_va_stall_T_11 = tail(_io_debug_va_stall_T_10, 1) connect io.debug.va_stall, _io_debug_va_stall_T_11 node _T_48 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_48 : node _T_49 = bits(vcalloc_sel, 0, 0) when _T_49 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_50 = eq(states[0].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_50, UInt<1>(0h1), "") : assert_3 node _T_54 = bits(vcalloc_sel, 1, 1) when _T_54 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_55 = eq(states[1].g, UInt<3>(0h2)) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_55, UInt<1>(0h1), "") : assert_4 node _T_59 = bits(vcalloc_sel, 2, 2) when _T_59 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_60 = eq(states[2].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_60, UInt<1>(0h1), "") : assert_5 node _T_64 = bits(vcalloc_sel, 3, 3) when _T_64 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_65 = eq(states[3].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_65, UInt<1>(0h1), "") : assert_6 node _T_69 = bits(vcalloc_sel, 4, 4) when _T_69 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_70 = eq(states[4].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_70, UInt<1>(0h1), "") : assert_7 node _T_74 = bits(vcalloc_sel, 5, 5) when _T_74 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_75 = eq(states[5].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_75, UInt<1>(0h1), "") : assert_8 inst salloc_arb of SwitchArbiter_33 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] node credit_available_lo_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node credit_available_lo = cat(credit_available_lo_hi, states[1].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi = cat(credit_available_hi_hi, states[1].vc_sel.`0`[3]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_hi_1 = cat(states[1].vc_sel.`2`[0], states[1].vc_sel.`1`[0]) node _credit_available_T_1 = cat(credit_available_hi_1, _credit_available_T) node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, io.out_credit_available.`0`[0]) node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_2 = cat(credit_available_hi_hi_1, io.out_credit_available.`0`[3]) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_1) node credit_available_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T_2) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_79 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_80 = and(_T_79, input_buffer.io.deq[1].bits.tail) when _T_80 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_hi_2 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, states[2].vc_sel.`0`[0]) node credit_available_hi_hi_2 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_4 = cat(credit_available_hi_hi_2, states[2].vc_sel.`0`[3]) node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_2) node credit_available_hi_5 = cat(states[2].vc_sel.`2`[0], states[2].vc_sel.`1`[0]) node _credit_available_T_6 = cat(credit_available_hi_5, _credit_available_T_5) node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, io.out_credit_available.`0`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_6 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[3]) node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_3) node credit_available_hi_7 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_8 = cat(credit_available_hi_7, _credit_available_T_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_81 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_82 = and(_T_81, input_buffer.io.deq[2].bits.tail) when _T_82 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_hi_4 = cat(states[3].vc_sel.`0`[2], states[3].vc_sel.`0`[1]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, states[3].vc_sel.`0`[0]) node credit_available_hi_hi_4 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_8 = cat(credit_available_hi_hi_4, states[3].vc_sel.`0`[3]) node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_4) node credit_available_hi_9 = cat(states[3].vc_sel.`2`[0], states[3].vc_sel.`1`[0]) node _credit_available_T_11 = cat(credit_available_hi_9, _credit_available_T_10) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_10 = cat(credit_available_hi_hi_5, io.out_credit_available.`0`[3]) node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_5) node credit_available_hi_11 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_13 = cat(credit_available_hi_11, _credit_available_T_12) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_83 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_84 = and(_T_83, input_buffer.io.deq[3].bits.tail) when _T_84 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_hi_6 = cat(states[4].vc_sel.`0`[2], states[4].vc_sel.`0`[1]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, states[4].vc_sel.`0`[0]) node credit_available_hi_hi_6 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_12 = cat(credit_available_hi_hi_6, states[4].vc_sel.`0`[3]) node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_6) node credit_available_hi_13 = cat(states[4].vc_sel.`2`[0], states[4].vc_sel.`1`[0]) node _credit_available_T_16 = cat(credit_available_hi_13, _credit_available_T_15) node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, io.out_credit_available.`0`[0]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_14 = cat(credit_available_hi_hi_7, io.out_credit_available.`0`[3]) node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_7) node credit_available_hi_15 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_18 = cat(credit_available_hi_15, _credit_available_T_17) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_85 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_86 = and(_T_85, input_buffer.io.deq[4].bits.tail) when _T_86 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_hi_8 = cat(states[5].vc_sel.`0`[2], states[5].vc_sel.`0`[1]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, states[5].vc_sel.`0`[0]) node credit_available_hi_hi_8 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_16 = cat(credit_available_hi_hi_8, states[5].vc_sel.`0`[3]) node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_8) node credit_available_hi_17 = cat(states[5].vc_sel.`2`[0], states[5].vc_sel.`1`[0]) node _credit_available_T_21 = cat(credit_available_hi_17, _credit_available_T_20) node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, io.out_credit_available.`0`[0]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_18 = cat(credit_available_hi_hi_9, io.out_credit_available.`0`[3]) node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_9) node credit_available_hi_19 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_23 = cat(credit_available_hi_19, _credit_available_T_22) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_87 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_88 = and(_T_87, input_buffer.io.deq[5].bits.tail) when _T_88 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_17) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_21 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_8) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_9) node _io_in_vc_free_T_15 = or(_io_in_vc_free_T_14, _io_in_vc_free_T_10) node _io_in_vc_free_T_16 = or(_io_in_vc_free_T_15, _io_in_vc_free_T_11) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_16, _io_in_vc_free_T_12) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_17 node _io_in_vc_free_T_18 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_18, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_19 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 5, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _vc_sel_WIRE : UInt<1>[6] node _vc_sel_T_6 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = or(_vc_sel_T_6, _vc_sel_T_7) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_8) node _vc_sel_T_14 = or(_vc_sel_T_13, _vc_sel_T_9) node _vc_sel_T_15 = or(_vc_sel_T_14, _vc_sel_T_10) node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_11) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_16 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_22 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_23 = or(_vc_sel_T_17, _vc_sel_T_18) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_19) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_20) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_21) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_22) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_27 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_34 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_30) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_31) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_32) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_33) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_38 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_39 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_45 = or(_vc_sel_T_39, _vc_sel_T_40) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_41) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_42) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_43) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_44) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_49 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_52) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_53) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_54) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_55) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_60 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_61 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_66 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_67 = or(_vc_sel_T_61, _vc_sel_T_62) node _vc_sel_T_68 = or(_vc_sel_T_67, _vc_sel_T_63) node _vc_sel_T_69 = or(_vc_sel_T_68, _vc_sel_T_64) node _vc_sel_T_70 = or(_vc_sel_T_69, _vc_sel_T_65) node _vc_sel_T_71 = or(_vc_sel_T_70, _vc_sel_T_66) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_71 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_7 : UInt<1>[1] node _vc_sel_T_72 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_77 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_78 = or(_vc_sel_T_72, _vc_sel_T_73) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_74) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_75) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_76) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_77) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_82 connect _vc_sel_WIRE_7[0], _vc_sel_WIRE_8 connect vc_sel.`1`, _vc_sel_WIRE_7 wire _vc_sel_WIRE_9 : UInt<1>[1] node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_89 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_90 = or(_vc_sel_T_89, _vc_sel_T_85) node _vc_sel_T_91 = or(_vc_sel_T_90, _vc_sel_T_86) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_87) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_88) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_93 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 connect vc_sel.`2`, _vc_sel_WIRE_9 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node channel_oh_0 = or(_channel_oh_T_3, vc_sel.`0`[5]) node virt_channel_lo_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node virt_channel_lo = cat(virt_channel_lo_hi, vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[3]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 5, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_11 = or(_virt_channel_T_8, _virt_channel_T_9) node _virt_channel_T_12 = or(_virt_channel_T_11, _virt_channel_T_10) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_12 node _T_89 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_89 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_14 = or(_salloc_outs_0_flit_payload_T_13, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_15 = or(_salloc_outs_0_flit_payload_T_14, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_15, _salloc_outs_0_flit_payload_T_11) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_16 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_14 = or(_salloc_outs_0_flit_head_T_13, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_15 = or(_salloc_outs_0_flit_head_T_14, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_15, _salloc_outs_0_flit_head_T_11) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_16 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_14 = or(_salloc_outs_0_flit_tail_T_13, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_15 = or(_salloc_outs_0_flit_tail_T_14, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_15, _salloc_outs_0_flit_tail_T_11) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_16 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_14 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_11) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_22 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_20) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_21) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_22) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_33) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_38 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_44) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_57 = or(_salloc_outs_0_flit_flow_T_56, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_57, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_55) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_60 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`2`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) node _T_90 = asUInt(reset) when _T_90 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0)
module InputUnit_10( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [5:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [5:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [5:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [5:0] mask; // @[InputUnit.scala:250:21] wire [5:0] _vcalloc_filter_T_3 = {vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [11:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 12'h1 : _vcalloc_filter_T_3[1] ? 12'h2 : _vcalloc_filter_T_3[2] ? 12'h4 : _vcalloc_filter_T_3[3] ? 12'h8 : _vcalloc_filter_T_3[4] ? 12'h10 : _vcalloc_filter_T_3[5] ? 12'h20 : vcalloc_vals_1 ? 12'h80 : vcalloc_vals_2 ? 12'h100 : vcalloc_vals_3 ? 12'h200 : vcalloc_vals_4 ? 12'h400 : {vcalloc_vals_5, 11'h0}; // @[OneHot.scala:85:71] wire [5:0] vcalloc_sel = vcalloc_filter[5:0] | vcalloc_filter[11:6]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_38 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_38( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_5 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_5( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheControl : input clock : Clock input reset : Reset output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip flush_match : UInt<1>, flush_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip flush_resp : UInt<1>} wire ctrlnodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate ctrlnodeIn.d.bits.corrupt invalidate ctrlnodeIn.d.bits.data invalidate ctrlnodeIn.d.bits.denied invalidate ctrlnodeIn.d.bits.sink invalidate ctrlnodeIn.d.bits.source invalidate ctrlnodeIn.d.bits.size invalidate ctrlnodeIn.d.bits.param invalidate ctrlnodeIn.d.bits.opcode invalidate ctrlnodeIn.d.valid invalidate ctrlnodeIn.d.ready invalidate ctrlnodeIn.a.bits.corrupt invalidate ctrlnodeIn.a.bits.data invalidate ctrlnodeIn.a.bits.mask invalidate ctrlnodeIn.a.bits.address invalidate ctrlnodeIn.a.bits.source invalidate ctrlnodeIn.a.bits.size invalidate ctrlnodeIn.a.bits.param invalidate ctrlnodeIn.a.bits.opcode invalidate ctrlnodeIn.a.valid invalidate ctrlnodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, ctrlnodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, ctrlnodeIn.d.bits.data connect monitor.io.in.d.bits.denied, ctrlnodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, ctrlnodeIn.d.bits.sink connect monitor.io.in.d.bits.source, ctrlnodeIn.d.bits.source connect monitor.io.in.d.bits.size, ctrlnodeIn.d.bits.size connect monitor.io.in.d.bits.param, ctrlnodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, ctrlnodeIn.d.bits.opcode connect monitor.io.in.d.valid, ctrlnodeIn.d.valid connect monitor.io.in.d.ready, ctrlnodeIn.d.ready connect monitor.io.in.a.bits.corrupt, ctrlnodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, ctrlnodeIn.a.bits.data connect monitor.io.in.a.bits.mask, ctrlnodeIn.a.bits.mask connect monitor.io.in.a.bits.address, ctrlnodeIn.a.bits.address connect monitor.io.in.a.bits.source, ctrlnodeIn.a.bits.source connect monitor.io.in.a.bits.size, ctrlnodeIn.a.bits.size connect monitor.io.in.a.bits.param, ctrlnodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, ctrlnodeIn.a.bits.opcode connect monitor.io.in.a.valid, ctrlnodeIn.a.valid connect monitor.io.in.a.ready, ctrlnodeIn.a.ready connect ctrlnodeIn, auto.ctrl_in regreset flushInValid : UInt<1>, clock, reset, UInt<1>(0h0) reg flushInAddress : UInt<64>, clock regreset flushOutValid : UInt<1>, clock, reset, UInt<1>(0h0) wire flushOutReady : UInt<1> connect flushOutReady, UInt<1>(0h0) when flushOutReady : connect flushOutValid, UInt<1>(0h0) when io.flush_resp : connect flushOutValid, UInt<1>(0h1) when io.flush_req.ready : connect flushInValid, UInt<1>(0h0) connect io.flush_req.valid, flushInValid connect io.flush_req.bits, flushInAddress node _T = eq(io.flush_match, UInt<1>(0h0)) node _T_1 = and(_T, flushInValid) when _T_1 : connect flushInValid, UInt<1>(0h0) connect flushOutValid, UInt<1>(0h1) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} node _in_bits_read_T = eq(ctrlnodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(ctrlnodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, ctrlnodeIn.a.bits.data connect in.bits.mask, ctrlnodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, ctrlnodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, ctrlnodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i9_m8 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<9>(0h48)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[6] wire out_wivalid : UInt<1>[6] wire out_roready : UInt<1>[6] wire out_woready : UInt<1>[6] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = eq(out_rimask, UInt<1>(0h0)) node _out_T_10 = eq(out_wimask, UInt<1>(0h0)) node _out_T_11 = eq(out_romask, UInt<1>(0h0)) node _out_T_12 = eq(out_womask, UInt<1>(0h0)) node _out_T_13 = or(UInt<1>(0h1), UInt<8>(0h0)) node _out_T_14 = bits(_out_T_13, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_15 = bits(out_back_front_q.io.deq.bits.data, 15, 8) node _out_T_16 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_17 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_18 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_20 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_14, UInt<8>(0h0)) node out_prepend = cat(UInt<4>(0h8), _out_prepend_T) node _out_T_22 = or(out_prepend, UInt<16>(0h0)) node _out_T_23 = bits(_out_T_22, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_24 = bits(out_back_front_q.io.deq.bits.data, 23, 16) node _out_T_25 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_26 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_27 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_28 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_29 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_23, UInt<16>(0h0)) node out_prepend_1 = cat(UInt<4>(0ha), _out_prepend_T_1) node _out_T_31 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_32 = bits(_out_T_31, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_33 = bits(out_back_front_q.io.deq.bits.data, 31, 24) node _out_T_34 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_35 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_36 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_37 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_38 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_32, UInt<24>(0h0)) node out_prepend_2 = cat(UInt<3>(0h6), _out_prepend_T_2) node _out_T_40 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_41 = bits(_out_T_40, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 63, 0) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 63, 0) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 63, 0) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 63, 0) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_42 = bits(out_front.bits.data, 63, 0) when out_f_woready_4 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_4 : connect flushInValid, UInt<1>(0h1) node _out_T_43 = eq(flushInValid, UInt<1>(0h0)) node _out_T_44 = and(out_f_wivalid_4, _out_T_43) when _out_T_44 : connect flushInAddress, _out_T_42 node out_f_wiready = eq(flushInValid, UInt<1>(0h0)) node _out_T_45 = and(out_f_wivalid_4, out_f_wiready) node _out_T_46 = and(flushOutValid, out_f_woready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = or(out_f_wiready, _out_T_48) node _out_T_50 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_51 = eq(out_womask_4, UInt<1>(0h0)) node _out_T_52 = or(flushOutValid, _out_T_51) node _out_T_53 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_54 = bits(_out_T_53, 63, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 0) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 0) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 0) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 0) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_55 = bits(out_front.bits.data, 31, 0) when out_f_woready_5 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_5 : connect flushInValid, UInt<1>(0h1) node _out_T_56 = eq(flushInValid, UInt<1>(0h0)) node _out_T_57 = and(out_f_wivalid_5, _out_T_56) when _out_T_57 : node _out_flushInAddress_T = shl(_out_T_55, 4) connect flushInAddress, _out_flushInAddress_T node out_f_wiready_1 = eq(flushInValid, UInt<1>(0h0)) node _out_T_58 = and(out_f_wivalid_5, out_f_wiready_1) node _out_T_59 = and(flushOutValid, out_f_woready_5) node _out_T_60 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_61 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_62 = or(out_f_wiready_1, _out_T_61) node _out_T_63 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_64 = eq(out_womask_5, UInt<1>(0h0)) node _out_T_65 = or(flushOutValid, _out_T_64) node _out_T_66 = or(UInt<1>(0h0), UInt<32>(0h0)) node _out_T_67 = bits(_out_T_66, 31, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_6, _out_iindex_T_3) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_6, _out_oindex_T_3) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1)) connect out_rifireMux_out_1, UInt<1>(0h1) node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[4], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_4) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1)) connect out_wifireMux_out_1, UInt<1>(0h1) node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) node out_wifireMux_all = and(_out_wifireMux_T_12, _out_T_49) connect out_wifireMux_out_2, _out_T_49 connect out_wivalid[4], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_4) node out_wifireMux_all_1 = and(_out_wifireMux_T_16, _out_T_62) connect out_wifireMux_out_3, _out_T_62 connect out_wivalid[5], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1)) connect out_rofireMux_out_1, UInt<1>(0h1) node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[4], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_5) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1)) connect out_wofireMux_out_1, UInt<1>(0h1) node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) node out_wofireMux_all = and(_out_wofireMux_T_12, _out_T_52) connect out_wofireMux_out_2, _out_T_52 connect out_woready[4], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_5) node out_wofireMux_all_1 = and(_out_wofireMux_T_16, _out_T_65) connect out_wofireMux_out_3, _out_T_65 connect out_woready[5], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], UInt<1>(0h1) connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], _out_T_5 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_41 connect _out_out_bits_data_WIRE_1[1], UInt<1>(0h0) connect _out_out_bits_data_WIRE_1[2], _out_T_54 connect _out_out_bits_data_WIRE_1[3], _out_T_67 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, ctrlnodeIn.a.valid connect ctrlnodeIn.a.ready, in.ready connect ctrlnodeIn.d.valid, out.valid connect out.ready, ctrlnodeIn.d.ready wire ctrlnodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect ctrlnodeIn_d_bits_d.opcode, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.param, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect ctrlnodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect ctrlnodeIn_d_bits_d.sink, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate ctrlnodeIn_d_bits_d.data connect ctrlnodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect ctrlnodeIn.d.bits.corrupt, ctrlnodeIn_d_bits_d.corrupt connect ctrlnodeIn.d.bits.data, ctrlnodeIn_d_bits_d.data connect ctrlnodeIn.d.bits.denied, ctrlnodeIn_d_bits_d.denied connect ctrlnodeIn.d.bits.sink, ctrlnodeIn_d_bits_d.sink connect ctrlnodeIn.d.bits.source, ctrlnodeIn_d_bits_d.source connect ctrlnodeIn.d.bits.size, ctrlnodeIn_d_bits_d.size connect ctrlnodeIn.d.bits.param, ctrlnodeIn_d_bits_d.param connect ctrlnodeIn.d.bits.opcode, ctrlnodeIn_d_bits_d.opcode connect ctrlnodeIn.d.bits.data, out.bits.data node _ctrlnodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect ctrlnodeIn.d.bits.opcode, _ctrlnodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_86 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] wire out_backSel_3; // @[RegisterRouter.scala:87:24] wire out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_enq_ready; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire [13:0] _out_back_front_q_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] _out_back_front_q_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801}; reg flushInValid; // @[Control.scala:45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] reg flushOutValid; // @[Control.scala:47:33] wire in_bits_read = auto_ctrl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_5 = {_out_back_front_q_io_deq_bits_index[8:7], _out_back_front_q_io_deq_bits_index[5:4], _out_back_front_q_io_deq_bits_index[2:0]} == 7'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{auto_ctrl_in_a_bits_mask[0]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{auto_ctrl_in_a_bits_mask[1]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{auto_ctrl_in_a_bits_mask[2]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{auto_ctrl_in_a_bits_mask[3]}}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {{8{auto_ctrl_in_a_bits_mask[7]}}, {8{auto_ctrl_in_a_bits_mask[6]}}, {8{auto_ctrl_in_a_bits_mask[5]}}, {8{auto_ctrl_in_a_bits_mask[4]}}, _out_frontMask_T_11, _out_frontMask_T_10, _out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_back_front_q_io_deq_bits_mask[0]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_back_front_q_io_deq_bits_mask[1]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_back_front_q_io_deq_bits_mask[2]}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_back_front_q_io_deq_bits_mask[3]}}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {{8{_out_back_front_q_io_deq_bits_mask[7]}}, {8{_out_back_front_q_io_deq_bits_mask[6]}}, {8{_out_back_front_q_io_deq_bits_mask[5]}}, {8{_out_back_front_q_io_deq_bits_mask[4]}}, _out_backMask_T_11, _out_backMask_T_10, _out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = {_out_frontMask_T_11, _out_frontMask_T_10, _out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = {_out_backMask_T_11, _out_backMask_T_10, _out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_back_front_q_io_deq_bits_index[6], _out_back_front_q_io_deq_bits_index[3]}; // @[RegisterRouter.scala:87:24] wire [1:0] _GEN_0 = {auto_ctrl_in_a_bits_address[9], auto_ctrl_in_a_bits_address[6]}; // @[OneHot.scala:58:35] wire [1:0] _GEN_1 = {_out_back_front_q_io_deq_bits_index[6], _out_back_front_q_io_deq_bits_index[3]}; // @[OneHot.scala:58:35] assign out_backSel_2 = _GEN_1 == 2'h2; // @[OneHot.scala:58:35] assign out_backSel_3 = &_GEN_1; // @[OneHot.scala:58:35] wire _out_wifireMux_T_2 = auto_ctrl_in_a_valid & _out_back_front_q_io_enq_ready & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] wire [3:0] _GEN_2 = {{|{~flushInValid | ~(&_out_wimask_T_5), auto_ctrl_in_a_bits_address[11:10], auto_ctrl_in_a_bits_address[8:7], auto_ctrl_in_a_bits_address[5:3]}}, {|{~flushInValid | ~(&out_frontMask), auto_ctrl_in_a_bits_address[11:10], auto_ctrl_in_a_bits_address[8:7], auto_ctrl_in_a_bits_address[5:3]}}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:10] assign _out_wofireMux_T_2 = _out_back_front_q_io_deq_valid & auto_ctrl_in_d_ready & ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_3 = {{|{flushOutValid | ~(&_out_womask_T_5), _out_back_front_q_io_deq_bits_index[8:7], _out_back_front_q_io_deq_bits_index[5:4], _out_back_front_q_io_deq_bits_index[2:0]}}, {|{flushOutValid | ~(&out_backMask), _out_back_front_q_io_deq_bits_index[8:7], _out_back_front_q_io_deq_bits_index[5:4], _out_back_front_q_io_deq_bits_index[2:0]}}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:10] wire out_iready = in_bits_read | _GEN_2[{auto_ctrl_in_a_bits_address[9], auto_ctrl_in_a_bits_address[6]}]; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read | _GEN_3[out_oindex]; // @[MuxLiteral.scala:49:10] wire in_ready = _out_back_front_q_io_enq_ready & out_iready; // @[RegisterRouter.scala:87:24] wire out_valid = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{_out_T_5}, {_out_T_5}, {1'h1}, {_out_T_5}}; // @[MuxLiteral.scala:49:10] wire [2:0] ctrlnodeIn_d_bits_opcode = {2'h0, _out_back_front_q_io_deq_bits_read}; // @[RegisterRouter.scala:87:24, :105:19] wire _GEN_5 = ~io_flush_match & flushInValid; // @[Control.scala:45:33, :56:{11,27}] wire _out_T_4 = {auto_ctrl_in_a_bits_address[11:10], auto_ctrl_in_a_bits_address[8:7], auto_ctrl_in_a_bits_address[5:3]} == 7'h0; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = _out_wifireMux_T_2 & _GEN_0 == 2'h2 & _out_T_4 & (&out_frontMask); // @[OneHot.scala:58:35] wire out_f_wivalid_5 = _out_wifireMux_T_2 & (&_GEN_0) & _out_T_4 & (&_out_wimask_T_5); // @[OneHot.scala:58:35] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_GEN_5 | io_flush_req_ready) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _GEN_5 | io_flush_resp | ~(_out_wofireMux_T_2 & out_backSel_3 & _out_T_5 & (&_out_womask_T_5) | _out_wofireMux_T_2 & out_backSel_2 & _out_T_5 & (&out_backMask)) & flushOutValid; // @[RegisterRouter.scala:87:24] end if (out_f_wivalid_5 & ~flushInValid) // @[RegisterRouter.scala:87:24] flushInAddress <= {28'h0, auto_ctrl_in_a_bits_data[31:0], 4'h0}; // @[RegisterRouter.scala:87:24] else if (out_f_wivalid_4 & ~flushInValid) // @[RegisterRouter.scala:87:24] flushInAddress <= auto_ctrl_in_a_bits_data; // @[Control.scala:46:29] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_5 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = or(_T_165, _T_170) node _T_172 = and(_T_160, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = and(_T_159, _T_173) node _T_175 = asUInt(reset) node _T_176 = eq(_T_175, UInt<1>(0h0)) when _T_176 : node _T_177 = eq(_T_174, UInt<1>(0h0)) when _T_177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_174, UInt<1>(0h1), "") : assert_2 node _T_178 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h0)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_10) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<1>(0h1)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_11) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h2)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_12) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<2>(0h3)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_13) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_202 = and(_T_200, _T_201) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_203 = shr(io.in.a.bits.source, 3) node _T_204 = eq(_T_203, UInt<3>(0h4)) node _T_205 = leq(UInt<1>(0h0), uncommonBits_14) node _T_206 = and(_T_204, _T_205) node _T_207 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_208 = and(_T_206, _T_207) node _T_209 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_210 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_211 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_178 connect _WIRE[1], _T_184 connect _WIRE[2], _T_190 connect _WIRE[3], _T_196 connect _WIRE[4], _T_202 connect _WIRE[5], _T_208 connect _WIRE[6], _T_209 connect _WIRE[7], _T_210 connect _WIRE[8], _T_211 node _T_212 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_213 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_217 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_218 = mux(_WIRE[5], _T_212, UInt<1>(0h0)) node _T_219 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_220 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_221 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_222 = or(_T_213, _T_214) node _T_223 = or(_T_222, _T_215) node _T_224 = or(_T_223, _T_216) node _T_225 = or(_T_224, _T_217) node _T_226 = or(_T_225, _T_218) node _T_227 = or(_T_226, _T_219) node _T_228 = or(_T_227, _T_220) node _T_229 = or(_T_228, _T_221) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_229 node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<13>(0h1000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = or(_T_238, _T_243) node _T_245 = and(_T_233, _T_244) node _T_246 = or(UInt<1>(0h0), _T_245) node _T_247 = and(_WIRE_1, _T_246) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_247, UInt<1>(0h1), "") : assert_3 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(source_ok, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_254 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_254, UInt<1>(0h1), "") : assert_5 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(is_aligned, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_261 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_261, UInt<1>(0h1), "") : assert_7 node _T_265 = not(io.in.a.bits.mask) node _T_266 = eq(_T_265, UInt<1>(0h0)) node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : node _T_269 = eq(_T_266, UInt<1>(0h0)) when _T_269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_266, UInt<1>(0h1), "") : assert_8 node _T_270 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_270, UInt<1>(0h1), "") : assert_9 node _T_274 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_274 : node _T_275 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_276 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<1>(0h0)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_15) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<1>(0h1)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_16) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<2>(0h2)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_17) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_296 = and(_T_294, _T_295) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_297 = shr(io.in.a.bits.source, 2) node _T_298 = eq(_T_297, UInt<2>(0h3)) node _T_299 = leq(UInt<1>(0h0), uncommonBits_18) node _T_300 = and(_T_298, _T_299) node _T_301 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_303 = shr(io.in.a.bits.source, 3) node _T_304 = eq(_T_303, UInt<3>(0h4)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_19) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_310 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_311 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_312 = or(_T_278, _T_284) node _T_313 = or(_T_312, _T_290) node _T_314 = or(_T_313, _T_296) node _T_315 = or(_T_314, _T_302) node _T_316 = or(_T_315, _T_308) node _T_317 = or(_T_316, _T_309) node _T_318 = or(_T_317, _T_310) node _T_319 = or(_T_318, _T_311) node _T_320 = and(_T_277, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_323 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<13>(0h1000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = or(_T_327, _T_332) node _T_334 = and(_T_322, _T_333) node _T_335 = or(UInt<1>(0h0), _T_334) node _T_336 = and(_T_321, _T_335) node _T_337 = asUInt(reset) node _T_338 = eq(_T_337, UInt<1>(0h0)) when _T_338 : node _T_339 = eq(_T_336, UInt<1>(0h0)) when _T_339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_336, UInt<1>(0h1), "") : assert_10 node _T_340 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<1>(0h0)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_20) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_347 = shr(io.in.a.bits.source, 2) node _T_348 = eq(_T_347, UInt<1>(0h1)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_21) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_353 = shr(io.in.a.bits.source, 2) node _T_354 = eq(_T_353, UInt<2>(0h2)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_22) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_359 = shr(io.in.a.bits.source, 2) node _T_360 = eq(_T_359, UInt<2>(0h3)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_23) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_364 = and(_T_362, _T_363) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_365 = shr(io.in.a.bits.source, 3) node _T_366 = eq(_T_365, UInt<3>(0h4)) node _T_367 = leq(UInt<1>(0h0), uncommonBits_24) node _T_368 = and(_T_366, _T_367) node _T_369 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_370 = and(_T_368, _T_369) node _T_371 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_372 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_373 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_340 connect _WIRE_2[1], _T_346 connect _WIRE_2[2], _T_352 connect _WIRE_2[3], _T_358 connect _WIRE_2[4], _T_364 connect _WIRE_2[5], _T_370 connect _WIRE_2[6], _T_371 connect _WIRE_2[7], _T_372 connect _WIRE_2[8], _T_373 node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_375 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_377 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = mux(_WIRE_2[5], _T_374, UInt<1>(0h0)) node _T_381 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_384 = or(_T_375, _T_376) node _T_385 = or(_T_384, _T_377) node _T_386 = or(_T_385, _T_378) node _T_387 = or(_T_386, _T_379) node _T_388 = or(_T_387, _T_380) node _T_389 = or(_T_388, _T_381) node _T_390 = or(_T_389, _T_382) node _T_391 = or(_T_390, _T_383) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_391 node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = or(UInt<1>(0h0), _T_394) node _T_396 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_397 = cvt(_T_396) node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000))) node _T_399 = asSInt(_T_398) node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0))) node _T_401 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = or(_T_400, _T_405) node _T_407 = and(_T_395, _T_406) node _T_408 = or(UInt<1>(0h0), _T_407) node _T_409 = and(_WIRE_3, _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_409, UInt<1>(0h1), "") : assert_11 node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(source_ok, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_416 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_416, UInt<1>(0h1), "") : assert_13 node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(is_aligned, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_423 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_423, UInt<1>(0h1), "") : assert_15 node _T_427 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_427, UInt<1>(0h1), "") : assert_16 node _T_431 = not(io.in.a.bits.mask) node _T_432 = eq(_T_431, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_432, UInt<1>(0h1), "") : assert_17 node _T_436 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_436, UInt<1>(0h1), "") : assert_18 node _T_440 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_440 : node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _T_444 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_25) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_451 = shr(io.in.a.bits.source, 2) node _T_452 = eq(_T_451, UInt<1>(0h1)) node _T_453 = leq(UInt<1>(0h0), uncommonBits_26) node _T_454 = and(_T_452, _T_453) node _T_455 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_456 = and(_T_454, _T_455) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<2>(0h2)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_27) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<2>(0h3)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_28) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_469 = shr(io.in.a.bits.source, 3) node _T_470 = eq(_T_469, UInt<3>(0h4)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_29) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_477 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_478 = or(_T_444, _T_450) node _T_479 = or(_T_478, _T_456) node _T_480 = or(_T_479, _T_462) node _T_481 = or(_T_480, _T_468) node _T_482 = or(_T_481, _T_474) node _T_483 = or(_T_482, _T_475) node _T_484 = or(_T_483, _T_476) node _T_485 = or(_T_484, _T_477) node _T_486 = and(_T_443, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_487, UInt<1>(0h1), "") : assert_19 node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_493 = and(_T_491, _T_492) node _T_494 = or(UInt<1>(0h0), _T_493) node _T_495 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<13>(0h1000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = or(_T_499, _T_504) node _T_506 = and(_T_494, _T_505) node _T_507 = or(UInt<1>(0h0), _T_506) node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_T_507, UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_507, UInt<1>(0h1), "") : assert_20 node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(source_ok, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(is_aligned, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_517 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_517, UInt<1>(0h1), "") : assert_23 node _T_521 = eq(io.in.a.bits.mask, mask) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_521, UInt<1>(0h1), "") : assert_24 node _T_525 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_525, UInt<1>(0h1), "") : assert_25 node _T_529 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_529 : node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_532 = and(_T_530, _T_531) node _T_533 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_534 = shr(io.in.a.bits.source, 2) node _T_535 = eq(_T_534, UInt<1>(0h0)) node _T_536 = leq(UInt<1>(0h0), uncommonBits_30) node _T_537 = and(_T_535, _T_536) node _T_538 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_539 = and(_T_537, _T_538) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_540 = shr(io.in.a.bits.source, 2) node _T_541 = eq(_T_540, UInt<1>(0h1)) node _T_542 = leq(UInt<1>(0h0), uncommonBits_31) node _T_543 = and(_T_541, _T_542) node _T_544 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_545 = and(_T_543, _T_544) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<2>(0h2)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_32) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<2>(0h3)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_33) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_558 = shr(io.in.a.bits.source, 3) node _T_559 = eq(_T_558, UInt<3>(0h4)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_34) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_566 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_567 = or(_T_533, _T_539) node _T_568 = or(_T_567, _T_545) node _T_569 = or(_T_568, _T_551) node _T_570 = or(_T_569, _T_557) node _T_571 = or(_T_570, _T_563) node _T_572 = or(_T_571, _T_564) node _T_573 = or(_T_572, _T_565) node _T_574 = or(_T_573, _T_566) node _T_575 = and(_T_532, _T_574) node _T_576 = or(UInt<1>(0h0), _T_575) node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_579 = and(_T_577, _T_578) node _T_580 = or(UInt<1>(0h0), _T_579) node _T_581 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<13>(0h1000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = or(_T_585, _T_590) node _T_592 = and(_T_580, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = and(_T_576, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_594, UInt<1>(0h1), "") : assert_26 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(source_ok, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(is_aligned, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_604, UInt<1>(0h1), "") : assert_29 node _T_608 = eq(io.in.a.bits.mask, mask) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_608, UInt<1>(0h1), "") : assert_30 node _T_612 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_612 : node _T_613 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_614 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_617 = shr(io.in.a.bits.source, 2) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = leq(UInt<1>(0h0), uncommonBits_35) node _T_620 = and(_T_618, _T_619) node _T_621 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_622 = and(_T_620, _T_621) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h1)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_36) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<2>(0h2)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_37) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h3)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_38) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_641 = shr(io.in.a.bits.source, 3) node _T_642 = eq(_T_641, UInt<3>(0h4)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_39) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_646 = and(_T_644, _T_645) node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_650 = or(_T_616, _T_622) node _T_651 = or(_T_650, _T_628) node _T_652 = or(_T_651, _T_634) node _T_653 = or(_T_652, _T_640) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = or(_T_655, _T_648) node _T_657 = or(_T_656, _T_649) node _T_658 = and(_T_615, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_661 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_662 = and(_T_660, _T_661) node _T_663 = or(UInt<1>(0h0), _T_662) node _T_664 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_665 = cvt(_T_664) node _T_666 = and(_T_665, asSInt(UInt<13>(0h1000))) node _T_667 = asSInt(_T_666) node _T_668 = eq(_T_667, asSInt(UInt<1>(0h0))) node _T_669 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_670 = cvt(_T_669) node _T_671 = and(_T_670, asSInt(UInt<13>(0h1000))) node _T_672 = asSInt(_T_671) node _T_673 = eq(_T_672, asSInt(UInt<1>(0h0))) node _T_674 = or(_T_668, _T_673) node _T_675 = and(_T_663, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = and(_T_659, _T_676) node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_T_677, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_677, UInt<1>(0h1), "") : assert_31 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(source_ok, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(is_aligned, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_687 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_688 = asUInt(reset) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(_T_687, UInt<1>(0h0)) when _T_690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_687, UInt<1>(0h1), "") : assert_34 node _T_691 = not(mask) node _T_692 = and(io.in.a.bits.mask, _T_691) node _T_693 = eq(_T_692, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_693, UInt<1>(0h1), "") : assert_35 node _T_697 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_697 : node _T_698 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_699 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_700 = and(_T_698, _T_699) node _T_701 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_702 = shr(io.in.a.bits.source, 2) node _T_703 = eq(_T_702, UInt<1>(0h0)) node _T_704 = leq(UInt<1>(0h0), uncommonBits_40) node _T_705 = and(_T_703, _T_704) node _T_706 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_707 = and(_T_705, _T_706) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_708 = shr(io.in.a.bits.source, 2) node _T_709 = eq(_T_708, UInt<1>(0h1)) node _T_710 = leq(UInt<1>(0h0), uncommonBits_41) node _T_711 = and(_T_709, _T_710) node _T_712 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_713 = and(_T_711, _T_712) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_714 = shr(io.in.a.bits.source, 2) node _T_715 = eq(_T_714, UInt<2>(0h2)) node _T_716 = leq(UInt<1>(0h0), uncommonBits_42) node _T_717 = and(_T_715, _T_716) node _T_718 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_719 = and(_T_717, _T_718) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_720 = shr(io.in.a.bits.source, 2) node _T_721 = eq(_T_720, UInt<2>(0h3)) node _T_722 = leq(UInt<1>(0h0), uncommonBits_43) node _T_723 = and(_T_721, _T_722) node _T_724 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_725 = and(_T_723, _T_724) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_726 = shr(io.in.a.bits.source, 3) node _T_727 = eq(_T_726, UInt<3>(0h4)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_44) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_731 = and(_T_729, _T_730) node _T_732 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_733 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_734 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_735 = or(_T_701, _T_707) node _T_736 = or(_T_735, _T_713) node _T_737 = or(_T_736, _T_719) node _T_738 = or(_T_737, _T_725) node _T_739 = or(_T_738, _T_731) node _T_740 = or(_T_739, _T_732) node _T_741 = or(_T_740, _T_733) node _T_742 = or(_T_741, _T_734) node _T_743 = and(_T_700, _T_742) node _T_744 = or(UInt<1>(0h0), _T_743) node _T_745 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_746 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_750, _T_755) node _T_757 = and(_T_745, _T_756) node _T_758 = or(UInt<1>(0h0), _T_757) node _T_759 = and(_T_744, _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_759, UInt<1>(0h1), "") : assert_36 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(source_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_769, UInt<1>(0h1), "") : assert_39 node _T_773 = eq(io.in.a.bits.mask, mask) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_773, UInt<1>(0h1), "") : assert_40 node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_777 : node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_780 = and(_T_778, _T_779) node _T_781 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<1>(0h0)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_45) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<1>(0h1)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_46) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_794 = shr(io.in.a.bits.source, 2) node _T_795 = eq(_T_794, UInt<2>(0h2)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_47) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_799 = and(_T_797, _T_798) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_800 = shr(io.in.a.bits.source, 2) node _T_801 = eq(_T_800, UInt<2>(0h3)) node _T_802 = leq(UInt<1>(0h0), uncommonBits_48) node _T_803 = and(_T_801, _T_802) node _T_804 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_805 = and(_T_803, _T_804) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_806 = shr(io.in.a.bits.source, 3) node _T_807 = eq(_T_806, UInt<3>(0h4)) node _T_808 = leq(UInt<1>(0h0), uncommonBits_49) node _T_809 = and(_T_807, _T_808) node _T_810 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_814 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_815 = or(_T_781, _T_787) node _T_816 = or(_T_815, _T_793) node _T_817 = or(_T_816, _T_799) node _T_818 = or(_T_817, _T_805) node _T_819 = or(_T_818, _T_811) node _T_820 = or(_T_819, _T_812) node _T_821 = or(_T_820, _T_813) node _T_822 = or(_T_821, _T_814) node _T_823 = and(_T_780, _T_822) node _T_824 = or(UInt<1>(0h0), _T_823) node _T_825 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_826 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<13>(0h1000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_832 = cvt(_T_831) node _T_833 = and(_T_832, asSInt(UInt<13>(0h1000))) node _T_834 = asSInt(_T_833) node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0))) node _T_836 = or(_T_830, _T_835) node _T_837 = and(_T_825, _T_836) node _T_838 = or(UInt<1>(0h0), _T_837) node _T_839 = and(_T_824, _T_838) node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(_T_839, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_839, UInt<1>(0h1), "") : assert_41 node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(source_ok, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(is_aligned, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_849 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_849, UInt<1>(0h1), "") : assert_44 node _T_853 = eq(io.in.a.bits.mask, mask) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_853, UInt<1>(0h1), "") : assert_45 node _T_857 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_857 : node _T_858 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_859 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_860 = and(_T_858, _T_859) node _T_861 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_862 = shr(io.in.a.bits.source, 2) node _T_863 = eq(_T_862, UInt<1>(0h0)) node _T_864 = leq(UInt<1>(0h0), uncommonBits_50) node _T_865 = and(_T_863, _T_864) node _T_866 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_868 = shr(io.in.a.bits.source, 2) node _T_869 = eq(_T_868, UInt<1>(0h1)) node _T_870 = leq(UInt<1>(0h0), uncommonBits_51) node _T_871 = and(_T_869, _T_870) node _T_872 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_873 = and(_T_871, _T_872) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<2>(0h2)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_52) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<2>(0h3)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_53) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_886 = shr(io.in.a.bits.source, 3) node _T_887 = eq(_T_886, UInt<3>(0h4)) node _T_888 = leq(UInt<1>(0h0), uncommonBits_54) node _T_889 = and(_T_887, _T_888) node _T_890 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_895 = or(_T_861, _T_867) node _T_896 = or(_T_895, _T_873) node _T_897 = or(_T_896, _T_879) node _T_898 = or(_T_897, _T_885) node _T_899 = or(_T_898, _T_891) node _T_900 = or(_T_899, _T_892) node _T_901 = or(_T_900, _T_893) node _T_902 = or(_T_901, _T_894) node _T_903 = and(_T_860, _T_902) node _T_904 = or(UInt<1>(0h0), _T_903) node _T_905 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_906 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = or(_T_910, _T_915) node _T_917 = and(_T_905, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = and(_T_904, _T_918) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_919, UInt<1>(0h1), "") : assert_46 node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(source_ok, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(is_aligned, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_929 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_929, UInt<1>(0h1), "") : assert_49 node _T_933 = eq(io.in.a.bits.mask, mask) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_933, UInt<1>(0h1), "") : assert_50 node _T_937 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_937, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_941 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_941, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 3) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_949 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_949, UInt<1>(0h1), "") : assert_54 node _T_953 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_953, UInt<1>(0h1), "") : assert_55 node _T_957 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_957, UInt<1>(0h1), "") : assert_56 node _T_961 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_961, UInt<1>(0h1), "") : assert_57 node _T_965 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_965 : node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(source_ok_1, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(sink_ok, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_972 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_972, UInt<1>(0h1), "") : assert_60 node _T_976 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_976, UInt<1>(0h1), "") : assert_61 node _T_980 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_980, UInt<1>(0h1), "") : assert_62 node _T_984 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_984, UInt<1>(0h1), "") : assert_63 node _T_988 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_989 = or(UInt<1>(0h0), _T_988) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_989, UInt<1>(0h1), "") : assert_64 node _T_993 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_993 : node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(source_ok_1, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(sink_ok, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1000 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_67 node _T_1004 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_68 node _T_1008 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_69 node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1013 = or(_T_1012, io.in.d.bits.corrupt) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_70 node _T_1017 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1018 = or(UInt<1>(0h0), _T_1017) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_71 node _T_1022 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1022 : node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(source_ok_1, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1026 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_73 node _T_1030 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_74 node _T_1034 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1035 = or(UInt<1>(0h0), _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_75 node _T_1039 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1039 : node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(source_ok_1, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1043 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_77 node _T_1047 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1048 = or(_T_1047, io.in.d.bits.corrupt) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_78 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h0), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_79 node _T_1057 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1061 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_81 node _T_1065 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_82 node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1070 = or(UInt<1>(0h0), _T_1069) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1074 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1078 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1082 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1086 = eq(a_first, UInt<1>(0h0)) node _T_1087 = and(io.in.a.valid, _T_1086) when _T_1087 : node _T_1088 = eq(io.in.a.bits.opcode, opcode) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_87 node _T_1092 = eq(io.in.a.bits.param, param) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_88 node _T_1096 = eq(io.in.a.bits.size, size) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_89 node _T_1100 = eq(io.in.a.bits.source, source) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_90 node _T_1104 = eq(io.in.a.bits.address, address) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_91 node _T_1108 = and(io.in.a.ready, io.in.a.valid) node _T_1109 = and(_T_1108, a_first) when _T_1109 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1110 = eq(d_first, UInt<1>(0h0)) node _T_1111 = and(io.in.d.valid, _T_1110) when _T_1111 : node _T_1112 = eq(io.in.d.bits.opcode, opcode_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_92 node _T_1116 = eq(io.in.d.bits.param, param_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_93 node _T_1120 = eq(io.in.d.bits.size, size_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_94 node _T_1124 = eq(io.in.d.bits.source, source_1) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_95 node _T_1128 = eq(io.in.d.bits.sink, sink) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_96 node _T_1132 = eq(io.in.d.bits.denied, denied) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_97 node _T_1136 = and(io.in.d.ready, io.in.d.valid) node _T_1137 = and(_T_1136, d_first) when _T_1137 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1138 = and(io.in.a.valid, a_first_1) node _T_1139 = and(_T_1138, UInt<1>(0h1)) when _T_1139 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1140 = and(io.in.a.ready, io.in.a.valid) node _T_1141 = and(_T_1140, a_first_1) node _T_1142 = and(_T_1141, UInt<1>(0h1)) when _T_1142 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1143 = dshr(inflight, io.in.a.bits.source) node _T_1144 = bits(_T_1143, 0, 0) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1149 = and(io.in.d.valid, d_first_1) node _T_1150 = and(_T_1149, UInt<1>(0h1)) node _T_1151 = eq(d_release_ack, UInt<1>(0h0)) node _T_1152 = and(_T_1150, _T_1151) when _T_1152 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = and(_T_1153, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1158 = and(io.in.d.valid, d_first_1) node _T_1159 = and(_T_1158, UInt<1>(0h1)) node _T_1160 = eq(d_release_ack, UInt<1>(0h0)) node _T_1161 = and(_T_1159, _T_1160) when _T_1161 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1162 = dshr(inflight, io.in.d.bits.source) node _T_1163 = bits(_T_1162, 0, 0) node _T_1164 = or(_T_1163, same_cycle_resp) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1168 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1169 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1170 = or(_T_1168, _T_1169) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_100 node _T_1174 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1175 = asUInt(reset) node _T_1176 = eq(_T_1175, UInt<1>(0h0)) when _T_1176 : node _T_1177 = eq(_T_1174, UInt<1>(0h0)) when _T_1177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1174, UInt<1>(0h1), "") : assert_101 else : node _T_1178 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1179 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1180 = or(_T_1178, _T_1179) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_102 node _T_1184 = eq(io.in.d.bits.size, a_size_lookup) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_103 node _T_1188 = and(io.in.d.valid, d_first_1) node _T_1189 = and(_T_1188, a_first_1) node _T_1190 = and(_T_1189, io.in.a.valid) node _T_1191 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = eq(d_release_ack, UInt<1>(0h0)) node _T_1194 = and(_T_1192, _T_1193) when _T_1194 : node _T_1195 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1196 = or(_T_1195, io.in.a.ready) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_104 node _T_1200 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1201 = orr(a_set_wo_ready) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) node _T_1203 = or(_T_1200, _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_10 node _T_1207 = orr(inflight) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1210 = or(_T_1208, _T_1209) node _T_1211 = lt(watchdog, plusarg_reader.out) node _T_1212 = or(_T_1210, _T_1211) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1216 = and(io.in.a.ready, io.in.a.valid) node _T_1217 = and(io.in.d.ready, io.in.d.valid) node _T_1218 = or(_T_1216, _T_1217) when _T_1218 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1219 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1220 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1221 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = and(_T_1219, _T_1222) when _T_1223 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1224 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1225 = and(_T_1224, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1226 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1230 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1231 = bits(_T_1230, 0, 0) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1236 = and(io.in.d.valid, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1239 = and(io.in.d.ready, io.in.d.valid) node _T_1240 = and(_T_1239, d_first_2) node _T_1241 = and(_T_1240, UInt<1>(0h1)) node _T_1242 = and(_T_1241, d_release_ack_1) when _T_1242 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1243 = and(io.in.d.valid, d_first_2) node _T_1244 = and(_T_1243, UInt<1>(0h1)) node _T_1245 = and(_T_1244, d_release_ack_1) when _T_1245 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1246 = dshr(inflight_1, io.in.d.bits.source) node _T_1247 = bits(_T_1246, 0, 0) node _T_1248 = or(_T_1247, same_cycle_resp_1) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1252 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_109 else : node _T_1256 = eq(io.in.d.bits.size, c_size_lookup) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_110 node _T_1260 = and(io.in.d.valid, d_first_2) node _T_1261 = and(_T_1260, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1262 = and(_T_1261, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1263 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1264 = and(_T_1262, _T_1263) node _T_1265 = and(_T_1264, d_release_ack_1) node _T_1266 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1267 = and(_T_1265, _T_1266) when _T_1267 : node _T_1268 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1269 = or(_T_1268, _WIRE_27.ready) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_111 node _T_1273 = orr(c_set_wo_ready) when _T_1273 : node _T_1274 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(_T_1274, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1274, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_11 node _T_1278 = orr(inflight_1) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) node _T_1280 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1281 = or(_T_1279, _T_1280) node _T_1282 = lt(watchdog_1, plusarg_reader_1.out) node _T_1283 = or(_T_1281, _T_1282) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1287 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1288 = and(io.in.d.ready, io.in.d.valid) node _T_1289 = or(_T_1287, _T_1288) when _T_1289 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1216 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1216; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1216; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1289 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1289; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1289; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1289; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1142 = _T_1216 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1142 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1142 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1142 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1142 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1142 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1188 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1188 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1157 = _T_1289 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1157 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1157 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1157 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1260 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1260 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1242 = _T_1289 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1242 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1242 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1242 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SinkD_3 : input clock : Clock input reset : Reset output io : { resp : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, source : UInt<4>, flip way : UInt<4>, flip set : UInt<11>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<3>, mask : UInt<1>}}, bs_dat : { data : UInt<64>}, grant_req : { set : UInt<11>, way : UInt<4>}, flip grant_safe : UInt<1>} inst d_q of Queue2_TLBundleD_a32d64s4k3z3c_3 connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, io.d.valid connect d_q.io.enq.bits.corrupt, io.d.bits.corrupt connect d_q.io.enq.bits.data, io.d.bits.data connect d_q.io.enq.bits.denied, io.d.bits.denied connect d_q.io.enq.bits.sink, io.d.bits.sink connect d_q.io.enq.bits.source, io.d.bits.source connect d_q.io.enq.bits.size, io.d.bits.size connect d_q.io.enq.bits.param, io.d.bits.param connect d_q.io.enq.bits.opcode, io.d.bits.opcode connect io.d.ready, d_q.io.enq.ready node _T = and(d_q.io.deq.ready, d_q.io.deq.valid) node _r_beats1_decode_T = dshl(UInt<6>(0h3f), d_q.io.deq.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(d_q.io.deq.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node last = or(_r_last_T, _r_last_T_1) node r_3 = and(last, _T) node _r_count_T = not(r_counter1) node beat = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(first, r_beats1, r_counter1) connect r_counter, _r_counter_T node hasData = bits(d_q.io.deq.bits.opcode, 0, 0) reg io_source_r : UInt<4>, clock when d_q.io.deq.valid : connect io_source_r, d_q.io.deq.bits.source node _io_source_T = mux(d_q.io.deq.valid, d_q.io.deq.bits.source, io_source_r) connect io.source, _io_source_T connect io.grant_req.way, io.way connect io.grant_req.set, io.set node _io_resp_valid_T = or(first, last) node _io_resp_valid_T_1 = and(d_q.io.deq.ready, d_q.io.deq.valid) node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1) connect io.resp.valid, _io_resp_valid_T_2 node _q_io_deq_ready_T = eq(first, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, io.grant_safe) node _q_io_deq_ready_T_2 = and(io.bs_adr.ready, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 node _io_bs_adr_valid_T = eq(first, UInt<1>(0h0)) node _io_bs_adr_valid_T_1 = and(d_q.io.deq.valid, io.grant_safe) node _io_bs_adr_valid_T_2 = or(_io_bs_adr_valid_T, _io_bs_adr_valid_T_1) connect io.bs_adr.valid, _io_bs_adr_valid_T_2 node _T_1 = and(d_q.io.deq.valid, first) node _T_2 = eq(io.grant_safe, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(io.bs_adr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_adr.valid, _T_4) connect io.resp.bits.last, last connect io.resp.bits.opcode, d_q.io.deq.bits.opcode connect io.resp.bits.param, d_q.io.deq.bits.param connect io.resp.bits.source, d_q.io.deq.bits.source connect io.resp.bits.sink, d_q.io.deq.bits.sink connect io.resp.bits.denied, d_q.io.deq.bits.denied node _io_bs_adr_bits_noop_T = eq(d_q.io.deq.valid, UInt<1>(0h0)) node _io_bs_adr_bits_noop_T_1 = eq(hasData, UInt<1>(0h0)) node _io_bs_adr_bits_noop_T_2 = or(_io_bs_adr_bits_noop_T, _io_bs_adr_bits_noop_T_1) connect io.bs_adr.bits.noop, _io_bs_adr_bits_noop_T_2 connect io.bs_adr.bits.way, io.way connect io.bs_adr.bits.set, io.set node _io_bs_adr_bits_beat_T = add(beat, io.bs_adr.ready) node _io_bs_adr_bits_beat_T_1 = tail(_io_bs_adr_bits_beat_T, 1) reg io_bs_adr_bits_beat_r : UInt<3>, clock when d_q.io.deq.valid : connect io_bs_adr_bits_beat_r, _io_bs_adr_bits_beat_T_1 node _io_bs_adr_bits_beat_T_2 = mux(d_q.io.deq.valid, beat, io_bs_adr_bits_beat_r) connect io.bs_adr.bits.beat, _io_bs_adr_bits_beat_T_2 node _io_bs_adr_bits_mask_T = not(UInt<1>(0h0)) connect io.bs_adr.bits.mask, _io_bs_adr_bits_mask_T connect io.bs_dat.data, d_q.io.deq.bits.data node _T_6 = and(d_q.io.deq.valid, d_q.io.deq.bits.corrupt) node _T_7 = eq(d_q.io.deq.bits.denied, UInt<1>(0h0)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SinkD.scala:82 assert (!(d.valid && d.bits.corrupt && !d.bits.denied), \"Data poisoning unsupported\")\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert
module SinkD_3( // @[SinkD.scala:34:7] input clock, // @[SinkD.scala:34:7] input reset, // @[SinkD.scala:34:7] output io_resp_valid, // @[SinkD.scala:36:14] output io_resp_bits_last, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_opcode, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_param, // @[SinkD.scala:36:14] output [3:0] io_resp_bits_source, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_sink, // @[SinkD.scala:36:14] output io_resp_bits_denied, // @[SinkD.scala:36:14] output io_d_ready, // @[SinkD.scala:36:14] input io_d_valid, // @[SinkD.scala:36:14] input [2:0] io_d_bits_opcode, // @[SinkD.scala:36:14] input [1:0] io_d_bits_param, // @[SinkD.scala:36:14] input [2:0] io_d_bits_size, // @[SinkD.scala:36:14] input [3:0] io_d_bits_source, // @[SinkD.scala:36:14] input [2:0] io_d_bits_sink, // @[SinkD.scala:36:14] input io_d_bits_denied, // @[SinkD.scala:36:14] input [63:0] io_d_bits_data, // @[SinkD.scala:36:14] input io_d_bits_corrupt, // @[SinkD.scala:36:14] output [3:0] io_source, // @[SinkD.scala:36:14] input [3:0] io_way, // @[SinkD.scala:36:14] input [10:0] io_set, // @[SinkD.scala:36:14] input io_bs_adr_ready, // @[SinkD.scala:36:14] output io_bs_adr_valid, // @[SinkD.scala:36:14] output io_bs_adr_bits_noop, // @[SinkD.scala:36:14] output [3:0] io_bs_adr_bits_way, // @[SinkD.scala:36:14] output [10:0] io_bs_adr_bits_set, // @[SinkD.scala:36:14] output [2:0] io_bs_adr_bits_beat, // @[SinkD.scala:36:14] output [63:0] io_bs_dat_data, // @[SinkD.scala:36:14] output [10:0] io_grant_req_set, // @[SinkD.scala:36:14] output [3:0] io_grant_req_way, // @[SinkD.scala:36:14] input io_grant_safe // @[SinkD.scala:36:14] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire io_d_valid_0 = io_d_valid; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_opcode_0 = io_d_bits_opcode; // @[SinkD.scala:34:7] wire [1:0] io_d_bits_param_0 = io_d_bits_param; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_size_0 = io_d_bits_size; // @[SinkD.scala:34:7] wire [3:0] io_d_bits_source_0 = io_d_bits_source; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_sink_0 = io_d_bits_sink; // @[SinkD.scala:34:7] wire io_d_bits_denied_0 = io_d_bits_denied; // @[SinkD.scala:34:7] wire [63:0] io_d_bits_data_0 = io_d_bits_data; // @[SinkD.scala:34:7] wire io_d_bits_corrupt_0 = io_d_bits_corrupt; // @[SinkD.scala:34:7] wire [3:0] io_way_0 = io_way; // @[SinkD.scala:34:7] wire [10:0] io_set_0 = io_set; // @[SinkD.scala:34:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkD.scala:34:7] wire io_grant_safe_0 = io_grant_safe; // @[SinkD.scala:34:7] wire io_bs_adr_bits_mask = 1'h1; // @[SinkD.scala:34:7] wire _io_bs_adr_bits_mask_T = 1'h1; // @[SinkD.scala:79:26] wire _io_resp_valid_T_2; // @[SinkD.scala:62:36] wire last; // @[Edges.scala:232:33] wire [3:0] _io_source_T; // @[SinkD.scala:57:19] wire [3:0] io_bs_adr_bits_way_0 = io_way_0; // @[SinkD.scala:34:7] wire [3:0] io_grant_req_way_0 = io_way_0; // @[SinkD.scala:34:7] wire [10:0] io_bs_adr_bits_set_0 = io_set_0; // @[SinkD.scala:34:7] wire [10:0] io_grant_req_set_0 = io_set_0; // @[SinkD.scala:34:7] wire _io_bs_adr_valid_T_2; // @[SinkD.scala:64:29] wire _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:75:35] wire [2:0] _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:78:29] wire io_resp_bits_last_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_opcode_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_param_0; // @[SinkD.scala:34:7] wire [3:0] io_resp_bits_source_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_sink_0; // @[SinkD.scala:34:7] wire io_resp_bits_denied_0; // @[SinkD.scala:34:7] wire io_resp_valid_0; // @[SinkD.scala:34:7] wire io_d_ready_0; // @[SinkD.scala:34:7] wire io_bs_adr_bits_noop_0; // @[SinkD.scala:34:7] wire [2:0] io_bs_adr_bits_beat_0; // @[SinkD.scala:34:7] wire io_bs_adr_valid_0; // @[SinkD.scala:34:7] wire [63:0] io_bs_dat_data_0; // @[SinkD.scala:34:7] wire [3:0] io_source_0; // @[SinkD.scala:34:7] wire _q_io_deq_ready_T_2; // @[SinkD.scala:63:30] wire _io_resp_valid_T_1 = _q_io_deq_ready_T_2 & _d_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire r_beats1_opdata = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire hasData = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] r_counter; // @[Edges.scala:229:27] wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28] wire first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33] wire r_3 = last & _io_resp_valid_T_1; // @[Decoupled.scala:51:35] wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [3:0] io_source_r; // @[SinkD.scala:57:53] assign _io_source_T = _d_q_io_deq_valid ? _d_q_io_deq_bits_source : io_source_r; // @[Decoupled.scala:362:21] assign io_source_0 = _io_source_T; // @[SinkD.scala:34:7, :57:19] wire _io_resp_valid_T = first | last; // @[Edges.scala:231:25, :232:33] assign _io_resp_valid_T_2 = _io_resp_valid_T & _io_resp_valid_T_1; // @[Decoupled.scala:51:35] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[SinkD.scala:34:7, :62:36] wire _q_io_deq_ready_T = ~first; // @[Edges.scala:231:25] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T | io_grant_safe_0; // @[SinkD.scala:34:7, :63:{34,41}] assign _q_io_deq_ready_T_2 = io_bs_adr_ready_0 & _q_io_deq_ready_T_1; // @[SinkD.scala:34:7, :63:{30,41}] wire _io_bs_adr_valid_T = ~first; // @[Edges.scala:231:25] wire _io_bs_adr_valid_T_1 = _d_q_io_deq_valid & io_grant_safe_0; // @[Decoupled.scala:362:21] assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T | _io_bs_adr_valid_T_1; // @[SinkD.scala:64:{22,29,41}] assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SinkD.scala:34:7, :64:29] assign io_resp_bits_param_0 = {1'h0, _d_q_io_deq_bits_param}; // @[Decoupled.scala:362:21] wire _io_bs_adr_bits_noop_T = ~_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _io_bs_adr_bits_noop_T_1 = ~hasData; // @[Edges.scala:106:36] assign _io_bs_adr_bits_noop_T_2 = _io_bs_adr_bits_noop_T | _io_bs_adr_bits_noop_T_1; // @[SinkD.scala:75:{26,35,38}] assign io_bs_adr_bits_noop_0 = _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:34:7, :75:35] wire [3:0] _io_bs_adr_bits_beat_T = {1'h0, beat} + {3'h0, io_bs_adr_ready_0}; // @[Edges.scala:234:25] wire [2:0] _io_bs_adr_bits_beat_T_1 = _io_bs_adr_bits_beat_T[2:0]; // @[SinkD.scala:78:60] reg [2:0] io_bs_adr_bits_beat_r; // @[SinkD.scala:78:54] assign _io_bs_adr_bits_beat_T_2 = _d_q_io_deq_valid ? beat : io_bs_adr_bits_beat_r; // @[Decoupled.scala:362:21] assign io_bs_adr_bits_beat_0 = _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:34:7, :78:29]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<9>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 8, 0) node _source_ok_T = shr(io.in.a.bits.source, 9) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<9>(0h19f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits = bits(_uncommonBits_T, 8, 0) node _T_4 = shr(io.in.a.bits.source, 9) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<9>(0h19f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 8, 0) node _T_24 = shr(io.in.a.bits.source, 9) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<9>(0h19f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 8, 0) node _T_86 = shr(io.in.a.bits.source, 9) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<9>(0h19f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 8, 0) node _T_152 = shr(io.in.a.bits.source, 9) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<9>(0h19f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 8, 0) node _T_199 = shr(io.in.a.bits.source, 9) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<9>(0h19f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 8, 0) node _T_240 = shr(io.in.a.bits.source, 9) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<9>(0h19f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 8, 0) node _T_283 = shr(io.in.a.bits.source, 9) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<9>(0h19f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 8, 0) node _T_321 = shr(io.in.a.bits.source, 9) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<9>(0h19f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<9>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 8, 0) node _T_359 = shr(io.in.a.bits.source, 9) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<9>(0h19f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<9>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 8, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 9) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<9>(0h19f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<9>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<9>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<416>, clock, reset, UInt<416>(0h0) regreset inflight_opcodes : UInt<1664>, clock, reset, UInt<1664>(0h0) regreset inflight_sizes : UInt<1664>, clock, reset, UInt<1664>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<416> connect a_set, UInt<416>(0h0) wire a_set_wo_ready : UInt<416> connect a_set_wo_ready, UInt<416>(0h0) wire a_opcodes_set : UInt<1664> connect a_opcodes_set, UInt<1664>(0h0) wire a_sizes_set : UInt<1664> connect a_sizes_set, UInt<1664>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<416> connect d_clr, UInt<416>(0h0) wire d_clr_wo_ready : UInt<416> connect d_clr_wo_ready, UInt<416>(0h0) wire d_opcodes_clr : UInt<1664> connect d_opcodes_clr, UInt<1664>(0h0) wire d_sizes_clr : UInt<1664> connect d_sizes_clr, UInt<1664>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_44 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<416>, clock, reset, UInt<416>(0h0) regreset inflight_opcodes_1 : UInt<1664>, clock, reset, UInt<1664>(0h0) regreset inflight_sizes_1 : UInt<1664>, clock, reset, UInt<1664>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<9>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<9>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<416> connect c_set, UInt<416>(0h0) wire c_set_wo_ready : UInt<416> connect c_set_wo_ready, UInt<416>(0h0) wire c_opcodes_set : UInt<1664> connect c_opcodes_set, UInt<1664>(0h0) wire c_sizes_set : UInt<1664> connect c_sizes_set, UInt<1664>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<9>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<9>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<9>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<9>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<9>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<9>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<416> connect d_clr_1, UInt<416>(0h0) wire d_clr_wo_ready_1 : UInt<416> connect d_clr_wo_ready_1, UInt<416>(0h0) wire d_opcodes_clr_1 : UInt<1664> connect d_opcodes_clr_1, UInt<1664>(0h0) wire d_sizes_clr_1 : UInt<1664> connect d_sizes_clr_1, UInt<1664>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<9>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<9>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<9>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<9>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_45 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<9>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4097:0] _c_sizes_set_T_1 = 4098'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1663:0] c_opcodes_set = 1664'h0; // @[Monitor.scala:740:34] wire [1663:0] c_sizes_set = 1664'h0; // @[Monitor.scala:741:34] wire [415:0] c_set = 416'h0; // @[Monitor.scala:738:34] wire [415:0] c_set_wo_ready = 416'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 9'h1A0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [8:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [8:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 9'h1A0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [415:0] inflight; // @[Monitor.scala:614:27] reg [1663:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1663:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [415:0] a_set; // @[Monitor.scala:626:34] wire [415:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1663:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1663:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1663:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1663:0] _a_opcode_lookup_T_6 = {1660'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1663:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1663:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1663:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1663:0] _a_size_lookup_T_6 = {1660'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1663:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1663:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[415:0] : 416'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[415:0] : 416'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[1663:0] : 1664'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4097:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[1663:0] : 1664'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [415:0] d_clr; // @[Monitor.scala:664:34] wire [415:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1663:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1663:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[415:0] : 416'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[415:0] : 416'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[1663:0] : 1664'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[1663:0] : 1664'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [415:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [415:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [415:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1663:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1663:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1663:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1663:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1663:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1663:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [415:0] inflight_1; // @[Monitor.scala:726:35] wire [415:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1663:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1663:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1663:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1663:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1663:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1663:0] _c_opcode_lookup_T_6 = {1660'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1663:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1663:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1663:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1663:0] _c_size_lookup_T_6 = {1660'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1663:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1663:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [415:0] d_clr_1; // @[Monitor.scala:774:34] wire [415:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1663:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1663:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[415:0] : 416'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[415:0] : 416'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[1663:0] : 1664'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[1663:0] : 1664'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [415:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [415:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1663:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1663:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1663:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1663:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLFIFOFixer : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonIn_1.e.bits.sink invalidate anonIn_1.e.valid invalidate anonIn_1.e.ready invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.c.bits.corrupt invalidate anonIn_1.c.bits.data invalidate anonIn_1.c.bits.address invalidate anonIn_1.c.bits.source invalidate anonIn_1.c.bits.size invalidate anonIn_1.c.bits.param invalidate anonIn_1.c.bits.opcode invalidate anonIn_1.c.valid invalidate anonIn_1.c.ready invalidate anonIn_1.b.bits.corrupt invalidate anonIn_1.b.bits.data invalidate anonIn_1.b.bits.mask invalidate anonIn_1.b.bits.address invalidate anonIn_1.b.bits.source invalidate anonIn_1.b.bits.size invalidate anonIn_1.b.bits.param invalidate anonIn_1.b.bits.opcode invalidate anonIn_1.b.valid invalidate anonIn_1.b.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_2 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_3 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink connect monitor_1.io.in.e.valid, anonIn_1.e.valid connect monitor_1.io.in.e.ready, anonIn_1.e.ready connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode connect monitor_1.io.in.c.valid, anonIn_1.c.valid connect monitor_1.io.in.c.ready, anonIn_1.c.ready connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode connect monitor_1.io.in.b.valid, anonIn_1.b.valid connect monitor_1.io.in.b.ready, anonIn_1.b.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_anonOut.e.bits.sink invalidate x1_anonOut.e.valid invalidate x1_anonOut.e.ready invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.c.bits.corrupt invalidate x1_anonOut.c.bits.data invalidate x1_anonOut.c.bits.address invalidate x1_anonOut.c.bits.source invalidate x1_anonOut.c.bits.size invalidate x1_anonOut.c.bits.param invalidate x1_anonOut.c.bits.opcode invalidate x1_anonOut.c.valid invalidate x1_anonOut.c.ready invalidate x1_anonOut.b.bits.corrupt invalidate x1_anonOut.b.bits.data invalidate x1_anonOut.b.bits.mask invalidate x1_anonOut.b.bits.address invalidate x1_anonOut.b.bits.source invalidate x1_anonOut.b.bits.size invalidate x1_anonOut.b.bits.param invalidate x1_anonOut.b.bits.opcode invalidate x1_anonOut.b.valid invalidate x1_anonOut.b.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) node _a_notFIFO_T_1 = cvt(_a_notFIFO_T) node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<33>(0h8c000000))) node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2) node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_5 = xor(anonIn.a.bits.address, UInt<17>(0h10000)) node _a_notFIFO_T_6 = cvt(_a_notFIFO_T_5) node _a_notFIFO_T_7 = and(_a_notFIFO_T_6, asSInt(UInt<33>(0h8c011000))) node _a_notFIFO_T_8 = asSInt(_a_notFIFO_T_7) node _a_notFIFO_T_9 = eq(_a_notFIFO_T_8, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_10 = xor(anonIn.a.bits.address, UInt<28>(0hc000000)) node _a_notFIFO_T_11 = cvt(_a_notFIFO_T_10) node _a_notFIFO_T_12 = and(_a_notFIFO_T_11, asSInt(UInt<33>(0h8c000000))) node _a_notFIFO_T_13 = asSInt(_a_notFIFO_T_12) node _a_notFIFO_T_14 = eq(_a_notFIFO_T_13, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_15 = or(_a_notFIFO_T_4, _a_notFIFO_T_9) node _a_notFIFO_T_16 = or(_a_notFIFO_T_15, _a_notFIFO_T_14) node _a_notFIFO_T_17 = xor(anonIn.a.bits.address, UInt<28>(0h8000000)) node _a_notFIFO_T_18 = cvt(_a_notFIFO_T_17) node _a_notFIFO_T_19 = and(_a_notFIFO_T_18, asSInt(UInt<33>(0h8c010000))) node _a_notFIFO_T_20 = asSInt(_a_notFIFO_T_19) node _a_notFIFO_T_21 = eq(_a_notFIFO_T_20, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_22 = xor(anonIn.a.bits.address, UInt<32>(0h80000000)) node _a_notFIFO_T_23 = cvt(_a_notFIFO_T_22) node _a_notFIFO_T_24 = and(_a_notFIFO_T_23, asSInt(UInt<33>(0h80000000))) node _a_notFIFO_T_25 = asSInt(_a_notFIFO_T_24) node _a_notFIFO_T_26 = eq(_a_notFIFO_T_25, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_27 = or(_a_notFIFO_T_21, _a_notFIFO_T_26) node _a_notFIFO_T_28 = mux(_a_notFIFO_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _a_notFIFO_T_29 = mux(_a_notFIFO_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _a_notFIFO_T_30 = or(_a_notFIFO_T_28, _a_notFIFO_T_29) wire a_notFIFO : UInt<1> connect a_notFIFO, _a_notFIFO_T_30 node _a_id_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) node _a_id_T_1 = cvt(_a_id_T) node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<1>(0h0))) node _a_id_T_3 = asSInt(_a_id_T_2) node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0))) node a_noDomain = eq(UInt<1>(0h1), UInt<1>(0h0)) node _a_first_T = and(anonIn.a.ready, anonIn.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonIn.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T node _d_first_T = and(anonOut.d.ready, anonOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6)) node d_first = and(d_first_first, _d_first_T_1) wire _flight_WIRE : UInt<1>[17] connect _flight_WIRE[0], UInt<1>(0h0) connect _flight_WIRE[1], UInt<1>(0h0) connect _flight_WIRE[2], UInt<1>(0h0) connect _flight_WIRE[3], UInt<1>(0h0) connect _flight_WIRE[4], UInt<1>(0h0) connect _flight_WIRE[5], UInt<1>(0h0) connect _flight_WIRE[6], UInt<1>(0h0) connect _flight_WIRE[7], UInt<1>(0h0) connect _flight_WIRE[8], UInt<1>(0h0) connect _flight_WIRE[9], UInt<1>(0h0) connect _flight_WIRE[10], UInt<1>(0h0) connect _flight_WIRE[11], UInt<1>(0h0) connect _flight_WIRE[12], UInt<1>(0h0) connect _flight_WIRE[13], UInt<1>(0h0) connect _flight_WIRE[14], UInt<1>(0h0) connect _flight_WIRE[15], UInt<1>(0h0) connect _flight_WIRE[16], UInt<1>(0h0) regreset flight : UInt<1>[17], clock, reset, _flight_WIRE node _T = and(anonIn.a.ready, anonIn.a.valid) node _T_1 = and(a_first, _T) when _T_1 : node _flight_T = eq(a_notFIFO, UInt<1>(0h0)) connect flight[anonIn.a.bits.source], _flight_T node _T_2 = and(anonIn.d.ready, anonIn.d.valid) node _T_3 = and(d_first, _T_2) when _T_3 : connect flight[anonIn.d.bits.source], UInt<1>(0h0) connect anonOut.a, anonIn.a connect anonIn.d, anonOut.d node _anonOut_a_valid_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _anonOut_a_valid_T_1 = or(a_notFIFO, _anonOut_a_valid_T) node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1) connect anonOut.a.valid, _anonOut_a_valid_T_2 node _anonIn_a_ready_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _anonIn_a_ready_T_1 = or(a_notFIFO, _anonIn_a_ready_T) node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1) connect anonIn.a.ready, _anonIn_a_ready_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) node _T_4 = and(anonIn.a.valid, UInt<1>(0h0)) regreset SourceIdFIFOed : UInt<17>, clock, reset, UInt<17>(0h0) wire SourceIdSet : UInt<17> connect SourceIdSet, UInt<17>(0h0) wire SourceIdClear : UInt<17> connect SourceIdClear, UInt<17>(0h0) node _T_5 = and(anonIn.a.ready, anonIn.a.valid) node _T_6 = and(a_first, _T_5) node _T_7 = eq(a_notFIFO, UInt<1>(0h0)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source) connect SourceIdSet, _SourceIdSet_T node _T_9 = and(anonIn.d.ready, anonIn.d.valid) node _T_10 = and(d_first, _T_9) when _T_10 : node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source) connect SourceIdClear, _SourceIdClear_T node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet) connect SourceIdFIFOed, _SourceIdFIFOed_T node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<17>(0h1ffff), UInt<17>(0h0)) node allIDs_FIFOed = eq(SourceIdFIFOed, _allIDs_FIFOed_T) node _T_11 = or(flight[0], flight[1]) node _T_12 = or(_T_11, flight[2]) node _T_13 = or(_T_12, flight[3]) node _T_14 = or(_T_13, flight[4]) node _T_15 = or(_T_14, flight[5]) node _T_16 = or(_T_15, flight[6]) node _T_17 = or(_T_16, flight[7]) node _T_18 = or(_T_17, flight[8]) node _T_19 = or(_T_18, flight[9]) node _T_20 = or(_T_19, flight[10]) node _T_21 = or(_T_20, flight[11]) node _T_22 = or(_T_21, flight[12]) node _T_23 = or(_T_22, flight[13]) node _T_24 = or(_T_23, flight[14]) node _T_25 = or(_T_24, flight[15]) node _T_26 = or(_T_25, flight[16]) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = gt(SourceIdSet, UInt<1>(0h0)) node _T_29 = gt(SourceIdClear, UInt<1>(0h0)) node _a_notFIFO_T_31 = xor(anonIn_1.a.bits.address, UInt<1>(0h0)) node _a_notFIFO_T_32 = cvt(_a_notFIFO_T_31) node _a_notFIFO_T_33 = and(_a_notFIFO_T_32, asSInt(UInt<33>(0h8c000000))) node _a_notFIFO_T_34 = asSInt(_a_notFIFO_T_33) node _a_notFIFO_T_35 = eq(_a_notFIFO_T_34, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_36 = xor(anonIn_1.a.bits.address, UInt<17>(0h10000)) node _a_notFIFO_T_37 = cvt(_a_notFIFO_T_36) node _a_notFIFO_T_38 = and(_a_notFIFO_T_37, asSInt(UInt<33>(0h8c011000))) node _a_notFIFO_T_39 = asSInt(_a_notFIFO_T_38) node _a_notFIFO_T_40 = eq(_a_notFIFO_T_39, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_41 = xor(anonIn_1.a.bits.address, UInt<28>(0hc000000)) node _a_notFIFO_T_42 = cvt(_a_notFIFO_T_41) node _a_notFIFO_T_43 = and(_a_notFIFO_T_42, asSInt(UInt<33>(0h8c000000))) node _a_notFIFO_T_44 = asSInt(_a_notFIFO_T_43) node _a_notFIFO_T_45 = eq(_a_notFIFO_T_44, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_46 = or(_a_notFIFO_T_35, _a_notFIFO_T_40) node _a_notFIFO_T_47 = or(_a_notFIFO_T_46, _a_notFIFO_T_45) node _a_notFIFO_T_48 = xor(anonIn_1.a.bits.address, UInt<28>(0h8000000)) node _a_notFIFO_T_49 = cvt(_a_notFIFO_T_48) node _a_notFIFO_T_50 = and(_a_notFIFO_T_49, asSInt(UInt<33>(0h8c010000))) node _a_notFIFO_T_51 = asSInt(_a_notFIFO_T_50) node _a_notFIFO_T_52 = eq(_a_notFIFO_T_51, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_53 = xor(anonIn_1.a.bits.address, UInt<32>(0h80000000)) node _a_notFIFO_T_54 = cvt(_a_notFIFO_T_53) node _a_notFIFO_T_55 = and(_a_notFIFO_T_54, asSInt(UInt<33>(0h80000000))) node _a_notFIFO_T_56 = asSInt(_a_notFIFO_T_55) node _a_notFIFO_T_57 = eq(_a_notFIFO_T_56, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_58 = or(_a_notFIFO_T_52, _a_notFIFO_T_57) node _a_notFIFO_T_59 = mux(_a_notFIFO_T_47, UInt<1>(0h0), UInt<1>(0h0)) node _a_notFIFO_T_60 = mux(_a_notFIFO_T_58, UInt<1>(0h1), UInt<1>(0h0)) node _a_notFIFO_T_61 = or(_a_notFIFO_T_59, _a_notFIFO_T_60) wire a_notFIFO_1 : UInt<1> connect a_notFIFO_1, _a_notFIFO_T_61 node _a_id_T_5 = xor(anonIn_1.a.bits.address, UInt<1>(0h0)) node _a_id_T_6 = cvt(_a_id_T_5) node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<1>(0h0))) node _a_id_T_8 = asSInt(_a_id_T_7) node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0))) node a_noDomain_1 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _a_first_T_1 = and(anonIn_1.a.ready, anonIn_1.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), anonIn_1.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(anonIn_1.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_2 = and(x1_anonOut.d.ready, x1_anonOut.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), x1_anonOut.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(x1_anonOut.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_2) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_2 : node _d_first_counter_T_1 = mux(d_first_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 node _d_first_T_3 = neq(x1_anonOut.d.bits.opcode, UInt<3>(0h6)) node d_first_1 = and(d_first_first_1, _d_first_T_3) wire _flight_WIRE_1 : UInt<1>[24] connect _flight_WIRE_1[0], UInt<1>(0h0) connect _flight_WIRE_1[1], UInt<1>(0h0) connect _flight_WIRE_1[2], UInt<1>(0h0) connect _flight_WIRE_1[3], UInt<1>(0h0) connect _flight_WIRE_1[4], UInt<1>(0h0) connect _flight_WIRE_1[5], UInt<1>(0h0) connect _flight_WIRE_1[6], UInt<1>(0h0) connect _flight_WIRE_1[7], UInt<1>(0h0) connect _flight_WIRE_1[8], UInt<1>(0h0) connect _flight_WIRE_1[9], UInt<1>(0h0) connect _flight_WIRE_1[10], UInt<1>(0h0) connect _flight_WIRE_1[11], UInt<1>(0h0) connect _flight_WIRE_1[12], UInt<1>(0h0) connect _flight_WIRE_1[13], UInt<1>(0h0) connect _flight_WIRE_1[14], UInt<1>(0h0) connect _flight_WIRE_1[15], UInt<1>(0h0) connect _flight_WIRE_1[16], UInt<1>(0h0) connect _flight_WIRE_1[17], UInt<1>(0h0) connect _flight_WIRE_1[18], UInt<1>(0h0) connect _flight_WIRE_1[19], UInt<1>(0h0) connect _flight_WIRE_1[20], UInt<1>(0h0) connect _flight_WIRE_1[21], UInt<1>(0h0) connect _flight_WIRE_1[22], UInt<1>(0h0) connect _flight_WIRE_1[23], UInt<1>(0h0) regreset flight_1 : UInt<1>[24], clock, reset, _flight_WIRE_1 node _T_30 = and(anonIn_1.a.ready, anonIn_1.a.valid) node _T_31 = and(a_first_1, _T_30) when _T_31 : node _flight_T_1 = eq(a_notFIFO_1, UInt<1>(0h0)) connect flight_1[anonIn_1.a.bits.source], _flight_T_1 node _T_32 = and(anonIn_1.d.ready, anonIn_1.d.valid) node _T_33 = and(d_first_1, _T_32) when _T_33 : connect flight_1[anonIn_1.d.bits.source], UInt<1>(0h0) node _stalls_a_sel_uncommonBits_T = or(anonIn_1.a.bits.source, UInt<3>(0h0)) node stalls_a_sel_uncommonBits = bits(_stalls_a_sel_uncommonBits_T, 2, 0) node _stalls_a_sel_T = shr(anonIn_1.a.bits.source, 3) node _stalls_a_sel_T_1 = eq(_stalls_a_sel_T, UInt<1>(0h1)) node _stalls_a_sel_T_2 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits) node _stalls_a_sel_T_3 = and(_stalls_a_sel_T_1, _stalls_a_sel_T_2) node _stalls_a_sel_T_4 = leq(stalls_a_sel_uncommonBits, UInt<3>(0h7)) node stalls_a_sel = and(_stalls_a_sel_T_3, _stalls_a_sel_T_4) node _stalls_id_T = and(anonIn_1.a.ready, anonIn_1.a.valid) node _stalls_id_T_1 = and(_stalls_id_T, stalls_a_sel) node _stalls_id_T_2 = eq(a_notFIFO_1, UInt<1>(0h0)) node _stalls_id_T_3 = and(_stalls_id_T_1, _stalls_id_T_2) reg stalls_id : UInt<1>, clock when _stalls_id_T_3 : connect stalls_id, UInt<1>(0h1) node _stalls_T = and(stalls_a_sel, a_first_1) node _stalls_T_1 = or(flight_1[8], flight_1[9]) node _stalls_T_2 = or(_stalls_T_1, flight_1[10]) node _stalls_T_3 = or(_stalls_T_2, flight_1[11]) node _stalls_T_4 = or(_stalls_T_3, flight_1[12]) node _stalls_T_5 = or(_stalls_T_4, flight_1[13]) node _stalls_T_6 = or(_stalls_T_5, flight_1[14]) node _stalls_T_7 = or(_stalls_T_6, flight_1[15]) node _stalls_T_8 = and(_stalls_T, _stalls_T_7) node _stalls_T_9 = neq(stalls_id, UInt<1>(0h1)) node _stalls_T_10 = or(a_noDomain_1, _stalls_T_9) node stalls_0 = and(_stalls_T_8, _stalls_T_10) node stall = or(UInt<1>(0h0), stalls_0) connect x1_anonOut.a, anonIn_1.a connect anonIn_1.d, x1_anonOut.d node _anonOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _anonOut_a_valid_T_4 = or(a_notFIFO_1, _anonOut_a_valid_T_3) node _anonOut_a_valid_T_5 = and(anonIn_1.a.valid, _anonOut_a_valid_T_4) connect x1_anonOut.a.valid, _anonOut_a_valid_T_5 node _anonIn_a_ready_T_3 = eq(stall, UInt<1>(0h0)) node _anonIn_a_ready_T_4 = or(a_notFIFO_1, _anonIn_a_ready_T_3) node _anonIn_a_ready_T_5 = and(x1_anonOut.a.ready, _anonIn_a_ready_T_4) connect anonIn_1.a.ready, _anonIn_a_ready_T_5 connect anonIn_1.b, x1_anonOut.b connect x1_anonOut.c, anonIn_1.c connect x1_anonOut.e, anonIn_1.e node _T_34 = and(anonIn_1.a.valid, stall) regreset SourceIdFIFOed_1 : UInt<24>, clock, reset, UInt<24>(0h0) wire SourceIdSet_1 : UInt<24> connect SourceIdSet_1, UInt<24>(0h0) wire SourceIdClear_1 : UInt<24> connect SourceIdClear_1, UInt<24>(0h0) node _T_35 = and(anonIn_1.a.ready, anonIn_1.a.valid) node _T_36 = and(a_first_1, _T_35) node _T_37 = eq(a_notFIFO_1, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) when _T_38 : node _SourceIdSet_T_1 = dshl(UInt<1>(0h1), anonIn_1.a.bits.source) connect SourceIdSet_1, _SourceIdSet_T_1 node _T_39 = and(anonIn_1.d.ready, anonIn_1.d.valid) node _T_40 = and(d_first_1, _T_39) when _T_40 : node _SourceIdClear_T_1 = dshl(UInt<1>(0h1), anonIn_1.d.bits.source) connect SourceIdClear_1, _SourceIdClear_T_1 node _SourceIdFIFOed_T_1 = or(SourceIdFIFOed_1, SourceIdSet_1) connect SourceIdFIFOed_1, _SourceIdFIFOed_T_1 node _allIDs_FIFOed_T_1 = mux(UInt<1>(0h1), UInt<24>(0hffffff), UInt<24>(0h0)) node allIDs_FIFOed_1 = eq(SourceIdFIFOed_1, _allIDs_FIFOed_T_1) node _T_41 = or(flight_1[0], flight_1[1]) node _T_42 = or(_T_41, flight_1[2]) node _T_43 = or(_T_42, flight_1[3]) node _T_44 = or(_T_43, flight_1[4]) node _T_45 = or(_T_44, flight_1[5]) node _T_46 = or(_T_45, flight_1[6]) node _T_47 = or(_T_46, flight_1[7]) node _T_48 = or(_T_47, flight_1[8]) node _T_49 = or(_T_48, flight_1[9]) node _T_50 = or(_T_49, flight_1[10]) node _T_51 = or(_T_50, flight_1[11]) node _T_52 = or(_T_51, flight_1[12]) node _T_53 = or(_T_52, flight_1[13]) node _T_54 = or(_T_53, flight_1[14]) node _T_55 = or(_T_54, flight_1[15]) node _T_56 = or(_T_55, flight_1[16]) node _T_57 = or(_T_56, flight_1[17]) node _T_58 = or(_T_57, flight_1[18]) node _T_59 = or(_T_58, flight_1[19]) node _T_60 = or(_T_59, flight_1[20]) node _T_61 = or(_T_60, flight_1[21]) node _T_62 = or(_T_61, flight_1[22]) node _T_63 = or(_T_62, flight_1[23]) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = gt(SourceIdSet_1, UInt<1>(0h0)) node _T_66 = gt(SourceIdClear_1, UInt<1>(0h0))
module TLFIFOFixer( // @[FIFOFixer.scala:50:9] input clock, // @[FIFOFixer.scala:50:9] input reset, // @[FIFOFixer.scala:50:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_b_ready_0 = auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_c_valid_0 = auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_1_c_bits_opcode_0 = auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_1_c_bits_param_0 = auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_in_1_c_bits_size_0 = auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_in_1_c_bits_source_0 = auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_in_1_c_bits_address_0 = auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_1_c_bits_data_0 = auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_c_bits_corrupt_0 = auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_e_valid_0 = auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_1_e_bits_sink_0 = auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_b_valid_0 = auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_out_1_b_bits_param_0 = auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_out_1_b_bits_address_0 = auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_c_ready_0 = auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [16:0] _allIDs_FIFOed_T = 17'h1FFFF; // @[FIFOFixer.scala:127:48] wire [32:0] _a_id_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _a_id_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _a_id_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _a_id_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [23:0] _allIDs_FIFOed_T_1 = 24'hFFFFFF; // @[FIFOFixer.scala:127:48] wire [63:0] auto_anon_in_1_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] auto_anon_out_1_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] anonIn_1_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [63:0] x1_anonOut_b_bits_data = 64'h0; // @[Nodes.scala:27:25] wire [7:0] auto_anon_in_1_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] auto_anon_out_1_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] anonIn_1_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [7:0] x1_anonOut_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25] wire [4:0] auto_anon_in_1_b_bits_source = 5'h10; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_out_1_b_bits_source = 5'h10; // @[FIFOFixer.scala:50:9] wire [4:0] anonIn_1_b_bits_source = 5'h10; // @[MixedNode.scala:551:17] wire [4:0] x1_anonOut_b_bits_source = 5'h10; // @[MixedNode.scala:542:17] wire [3:0] auto_anon_in_1_b_bits_size = 4'h6; // @[Nodes.scala:27:25] wire [3:0] auto_anon_out_1_b_bits_size = 4'h6; // @[Nodes.scala:27:25] wire [3:0] anonIn_1_b_bits_size = 4'h6; // @[Nodes.scala:27:25] wire [3:0] x1_anonOut_b_bits_size = 4'h6; // @[Nodes.scala:27:25] wire [2:0] auto_anon_in_1_b_bits_opcode = 3'h6; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_b_bits_opcode = 3'h6; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire auto_anon_in_1_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _a_notFIFO_T_28 = 1'h0; // @[Mux.scala:30:73] wire a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29] wire _flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire _a_notFIFO_T_59 = 1'h0; // @[Mux.scala:30:73] wire a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29] wire _flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire _stalls_T_9 = 1'h0; // @[FIFOFixer.scala:88:71] wire _stalls_T_10 = 1'h0; // @[FIFOFixer.scala:88:65] wire stalls_0 = 1'h0; // @[FIFOFixer.scala:88:50] wire stall = 1'h0; // @[FIFOFixer.scala:91:45] wire auto_anon_in_1_e_ready = 1'h1; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_e_ready = 1'h1; // @[FIFOFixer.scala:50:9] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire _a_id_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire _anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire _anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire _anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire _a_id_T_9 = 1'h1; // @[Parameters.scala:137:59] wire _stalls_a_sel_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _stalls_a_sel_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50] wire _anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47] wire _anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50] wire _anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire anonIn_1_b_ready = auto_anon_in_1_b_ready_0; // @[FIFOFixer.scala:50:9] wire anonIn_1_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_1_c_ready; // @[MixedNode.scala:551:17] wire anonIn_1_c_valid = auto_anon_in_1_c_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_1_c_bits_opcode = auto_anon_in_1_c_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_1_c_bits_param = auto_anon_in_1_c_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] anonIn_1_c_bits_size = auto_anon_in_1_c_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] anonIn_1_c_bits_source = auto_anon_in_1_c_bits_source_0; // @[FIFOFixer.scala:50:9] wire [31:0] anonIn_1_c_bits_address = auto_anon_in_1_c_bits_address_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonIn_1_c_bits_data = auto_anon_in_1_c_bits_data_0; // @[FIFOFixer.scala:50:9] wire anonIn_1_c_bits_corrupt = auto_anon_in_1_c_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[FIFOFixer.scala:50:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_1_e_valid = auto_anon_in_1_e_valid_0; // @[FIFOFixer.scala:50:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_e_bits_sink = auto_anon_in_1_e_bits_sink_0; // @[FIFOFixer.scala:50:9] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[FIFOFixer.scala:50:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[FIFOFixer.scala:50:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_b_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_b_valid = auto_anon_out_1_b_valid_0; // @[FIFOFixer.scala:50:9] wire [1:0] x1_anonOut_b_bits_param = auto_anon_out_1_b_bits_param_0; // @[FIFOFixer.scala:50:9] wire [31:0] x1_anonOut_b_bits_address = auto_anon_out_1_b_bits_address_0; // @[FIFOFixer.scala:50:9] wire x1_anonOut_c_ready = auto_anon_out_1_c_ready_0; // @[FIFOFixer.scala:50:9] wire x1_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [2:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[FIFOFixer.scala:50:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[FIFOFixer.scala:50:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire x1_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[FIFOFixer.scala:50:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[FIFOFixer.scala:50:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_a_ready_0; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_in_1_b_bits_param_0; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_in_1_b_bits_address_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_b_valid_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_c_ready_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_in_1_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_d_bits_denied_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_1_d_valid_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_0_a_ready_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_in_0_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_0_d_bits_denied_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_0_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_out_1_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_out_1_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_out_1_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_a_valid_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_b_ready_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_c_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_c_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_out_1_c_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_out_1_c_bits_source_0; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_out_1_c_bits_address_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_1_c_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_c_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_c_valid_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_d_ready_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_1_e_bits_sink_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_1_e_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [3:0] auto_anon_out_0_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] auto_anon_out_0_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [31:0] auto_anon_out_0_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_0_a_valid_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_0_d_ready_0; // @[FIFOFixer.scala:50:9] wire _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[FIFOFixer.scala:50:9] wire _anonOut_a_valid_T_2 = anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] _a_notFIFO_T = anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] _a_id_T = anonIn_a_bits_address; // @[Parameters.scala:137:31] assign anonOut_a_bits_mask = anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign anonOut_d_ready = anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire _anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[FIFOFixer.scala:50:9] wire _anonOut_a_valid_T_5 = anonIn_1_a_valid; // @[FIFOFixer.scala:95:33] assign x1_anonOut_a_bits_opcode = anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_a_bits_param = anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_a_bits_size = anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_a_bits_source = anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [4:0] _stalls_a_sel_uncommonBits_T = anonIn_1_a_bits_source; // @[Parameters.scala:52:29] assign x1_anonOut_a_bits_address = anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] _a_notFIFO_T_31 = anonIn_1_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] _a_id_T_5 = anonIn_1_a_bits_address; // @[Parameters.scala:137:31] assign x1_anonOut_a_bits_mask = anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_a_bits_data = anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_b_ready = anonIn_1_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_in_1_b_valid_0 = anonIn_1_b_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_bits_param_0 = anonIn_1_b_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_bits_address_0 = anonIn_1_b_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_c_ready_0 = anonIn_1_c_ready; // @[FIFOFixer.scala:50:9] assign x1_anonOut_c_valid = anonIn_1_c_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_c_bits_opcode = anonIn_1_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_c_bits_param = anonIn_1_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_c_bits_size = anonIn_1_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_c_bits_source = anonIn_1_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_c_bits_address = anonIn_1_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_c_bits_data = anonIn_1_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_c_bits_corrupt = anonIn_1_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_d_ready = anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign x1_anonOut_e_valid = anonIn_1_e_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_anonOut_e_bits_sink = anonIn_1_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign _anonIn_a_ready_T_2 = anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign anonIn_d_valid = anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_corrupt = anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign _anonIn_a_ready_T_5 = x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_b_ready_0 = x1_anonOut_b_ready; // @[FIFOFixer.scala:50:9] assign anonIn_1_b_valid = x1_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_b_bits_param = x1_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_b_bits_address = x1_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_c_ready = x1_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_out_1_c_valid_0 = x1_anonOut_c_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_opcode_0 = x1_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_param_0 = x1_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_size_0 = x1_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_source_0 = x1_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_address_0 = x1_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_data_0 = x1_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_corrupt_0 = x1_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign anonIn_1_d_valid = x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_param = x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_size = x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_source = x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_sink = x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_data = x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign anonIn_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_out_1_e_valid_0 = x1_anonOut_e_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_e_bits_sink_0 = x1_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9] wire [32:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_2 = _a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_3 = _a_notFIFO_T_2; // @[Parameters.scala:137:46] wire _a_notFIFO_T_4 = _a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _a_notFIFO_T_5 = {anonIn_a_bits_address[31:17], anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_6 = {1'h0, _a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_7 = _a_notFIFO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_8 = _a_notFIFO_T_7; // @[Parameters.scala:137:46] wire _a_notFIFO_T_9 = _a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _a_notFIFO_T_10 = {anonIn_a_bits_address[31:28], anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_11 = {1'h0, _a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_12 = _a_notFIFO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_13 = _a_notFIFO_T_12; // @[Parameters.scala:137:46] wire _a_notFIFO_T_14 = _a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _a_notFIFO_T_15 = _a_notFIFO_T_4 | _a_notFIFO_T_9; // @[Parameters.scala:629:89] wire _a_notFIFO_T_16 = _a_notFIFO_T_15 | _a_notFIFO_T_14; // @[Parameters.scala:629:89] wire [31:0] _a_notFIFO_T_17 = {anonIn_a_bits_address[31:28], anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_18 = {1'h0, _a_notFIFO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_19 = _a_notFIFO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_20 = _a_notFIFO_T_19; // @[Parameters.scala:137:46] wire _a_notFIFO_T_21 = _a_notFIFO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _a_notFIFO_T_22 = anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_23 = {1'h0, _a_notFIFO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_24 = _a_notFIFO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_25 = _a_notFIFO_T_24; // @[Parameters.scala:137:46] wire _a_notFIFO_T_26 = _a_notFIFO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _a_notFIFO_T_27 = _a_notFIFO_T_21 | _a_notFIFO_T_26; // @[Parameters.scala:629:89] wire _a_notFIFO_T_29 = _a_notFIFO_T_27; // @[Mux.scala:30:73] wire _a_notFIFO_T_30 = _a_notFIFO_T_29; // @[Mux.scala:30:73] wire a_notFIFO = _a_notFIFO_T_30; // @[Mux.scala:30:73] wire [32:0] _a_id_T_1 = {1'h0, _a_id_T}; // @[Parameters.scala:137:{31,41}] wire _a_first_T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] _a_first_beats1_decode_T = 27'hFFF << anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] _d_first_beats1_decode_T = 27'hFFF << anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire d_first = d_first_first & _d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg flight_0; // @[FIFOFixer.scala:79:27] reg flight_1; // @[FIFOFixer.scala:79:27] reg flight_2; // @[FIFOFixer.scala:79:27] reg flight_3; // @[FIFOFixer.scala:79:27] reg flight_4; // @[FIFOFixer.scala:79:27] reg flight_5; // @[FIFOFixer.scala:79:27] reg flight_6; // @[FIFOFixer.scala:79:27] reg flight_7; // @[FIFOFixer.scala:79:27] reg flight_8; // @[FIFOFixer.scala:79:27] reg flight_9; // @[FIFOFixer.scala:79:27] reg flight_10; // @[FIFOFixer.scala:79:27] reg flight_11; // @[FIFOFixer.scala:79:27] reg flight_12; // @[FIFOFixer.scala:79:27] reg flight_13; // @[FIFOFixer.scala:79:27] reg flight_14; // @[FIFOFixer.scala:79:27] reg flight_15; // @[FIFOFixer.scala:79:27] reg flight_16; // @[FIFOFixer.scala:79:27] wire _flight_T = ~a_notFIFO; // @[Mux.scala:30:73] wire _T_9 = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] assign anonOut_a_valid = _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign anonIn_a_ready = _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [16:0] SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [16:0] SourceIdSet; // @[FIFOFixer.scala:116:36] wire [16:0] SourceIdClear; // @[FIFOFixer.scala:117:38] wire [31:0] _SourceIdSet_T = 32'h1 << anonIn_a_bits_source; // @[OneHot.scala:58:35] assign SourceIdSet = a_first & _a_first_T & ~a_notFIFO ? _SourceIdSet_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [31:0] _SourceIdClear_T = 32'h1 << anonIn_d_bits_source; // @[OneHot.scala:58:35] assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [16:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire allIDs_FIFOed = &SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] _a_notFIFO_T_32 = {1'h0, _a_notFIFO_T_31}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_33 = _a_notFIFO_T_32 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_34 = _a_notFIFO_T_33; // @[Parameters.scala:137:46] wire _a_notFIFO_T_35 = _a_notFIFO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _a_notFIFO_T_36 = {anonIn_1_a_bits_address[31:17], anonIn_1_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_37 = {1'h0, _a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_38 = _a_notFIFO_T_37 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_39 = _a_notFIFO_T_38; // @[Parameters.scala:137:46] wire _a_notFIFO_T_40 = _a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _a_notFIFO_T_41 = {anonIn_1_a_bits_address[31:28], anonIn_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_42 = {1'h0, _a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_43 = _a_notFIFO_T_42 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_44 = _a_notFIFO_T_43; // @[Parameters.scala:137:46] wire _a_notFIFO_T_45 = _a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _a_notFIFO_T_46 = _a_notFIFO_T_35 | _a_notFIFO_T_40; // @[Parameters.scala:629:89] wire _a_notFIFO_T_47 = _a_notFIFO_T_46 | _a_notFIFO_T_45; // @[Parameters.scala:629:89] wire [31:0] _a_notFIFO_T_48 = {anonIn_1_a_bits_address[31:28], anonIn_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_49 = {1'h0, _a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_50 = _a_notFIFO_T_49 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_51 = _a_notFIFO_T_50; // @[Parameters.scala:137:46] wire _a_notFIFO_T_52 = _a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _a_notFIFO_T_53 = anonIn_1_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _a_notFIFO_T_54 = {1'h0, _a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}] wire [32:0] _a_notFIFO_T_55 = _a_notFIFO_T_54 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _a_notFIFO_T_56 = _a_notFIFO_T_55; // @[Parameters.scala:137:46] wire _a_notFIFO_T_57 = _a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _a_notFIFO_T_58 = _a_notFIFO_T_52 | _a_notFIFO_T_57; // @[Parameters.scala:629:89] wire _a_notFIFO_T_60 = _a_notFIFO_T_58; // @[Mux.scala:30:73] wire _a_notFIFO_T_61 = _a_notFIFO_T_60; // @[Mux.scala:30:73] wire a_notFIFO_1 = _a_notFIFO_T_61; // @[Mux.scala:30:73] wire [32:0] _a_id_T_6 = {1'h0, _a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire _T_35 = anonIn_1_a_ready & anonIn_1_a_valid; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_35; // @[Decoupled.scala:51:35] wire _stalls_id_T; // @[Decoupled.scala:51:35] assign _stalls_id_T = _T_35; // @[Decoupled.scala:51:35] wire [26:0] _a_first_beats1_decode_T_3 = 27'hFFF << anonIn_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T_1 = anonIn_1_a_bits_opcode[2]; // @[Edges.scala:92:37] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T_2 = x1_anonOut_d_ready & x1_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] _d_first_beats1_decode_T_3 = 27'hFFF << x1_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata_1 = x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T_3 = x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire d_first_1 = d_first_first_1 & _d_first_T_3; // @[FIFOFixer.scala:75:{42,63}] reg flight_1_0; // @[FIFOFixer.scala:79:27] reg flight_1_1; // @[FIFOFixer.scala:79:27] reg flight_1_2; // @[FIFOFixer.scala:79:27] reg flight_1_3; // @[FIFOFixer.scala:79:27] reg flight_1_4; // @[FIFOFixer.scala:79:27] reg flight_1_5; // @[FIFOFixer.scala:79:27] reg flight_1_6; // @[FIFOFixer.scala:79:27] reg flight_1_7; // @[FIFOFixer.scala:79:27] reg flight_1_8; // @[FIFOFixer.scala:79:27] reg flight_1_9; // @[FIFOFixer.scala:79:27] reg flight_1_10; // @[FIFOFixer.scala:79:27] reg flight_1_11; // @[FIFOFixer.scala:79:27] reg flight_1_12; // @[FIFOFixer.scala:79:27] reg flight_1_13; // @[FIFOFixer.scala:79:27] reg flight_1_14; // @[FIFOFixer.scala:79:27] reg flight_1_15; // @[FIFOFixer.scala:79:27] reg flight_1_16; // @[FIFOFixer.scala:79:27] reg flight_1_17; // @[FIFOFixer.scala:79:27] reg flight_1_18; // @[FIFOFixer.scala:79:27] reg flight_1_19; // @[FIFOFixer.scala:79:27] reg flight_1_20; // @[FIFOFixer.scala:79:27] reg flight_1_21; // @[FIFOFixer.scala:79:27] reg flight_1_22; // @[FIFOFixer.scala:79:27] reg flight_1_23; // @[FIFOFixer.scala:79:27] wire _flight_T_1 = ~a_notFIFO_1; // @[Mux.scala:30:73] wire _T_39 = anonIn_1_d_ready & anonIn_1_d_valid; // @[Decoupled.scala:51:35] wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _stalls_a_sel_T = anonIn_1_a_bits_source[4:3]; // @[Parameters.scala:54:10] wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 2'h1; // @[Parameters.scala:54:{10,32}] wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1; // @[Parameters.scala:54:{32,67}] wire stalls_a_sel = _stalls_a_sel_T_3; // @[Parameters.scala:54:67, :56:48] wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel; // @[Decoupled.scala:51:35] wire _stalls_id_T_2 = ~a_notFIFO_1; // @[Mux.scala:30:73] wire _stalls_id_T_3 = _stalls_id_T_1 & _stalls_id_T_2; // @[FIFOFixer.scala:85:{47,56,59}] wire _stalls_T = stalls_a_sel & a_first_1; // @[FIFOFixer.scala:88:15] wire _stalls_T_1 = flight_1_8 | flight_1_9; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_2 = _stalls_T_1 | flight_1_10; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_3 = _stalls_T_2 | flight_1_11; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_4 = _stalls_T_3 | flight_1_12; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_5 = _stalls_T_4 | flight_1_13; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_6 = _stalls_T_5 | flight_1_14; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_7 = _stalls_T_6 | flight_1_15; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_8 = _stalls_T & _stalls_T_7; // @[FIFOFixer.scala:88:{15,26,44}] assign x1_anonOut_a_valid = _anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] assign anonIn_1_a_ready = _anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33] reg [23:0] SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35] wire [23:0] SourceIdSet_1; // @[FIFOFixer.scala:116:36] wire [23:0] SourceIdClear_1; // @[FIFOFixer.scala:117:38] wire [31:0] _SourceIdSet_T_1 = 32'h1 << anonIn_1_a_bits_source; // @[OneHot.scala:58:35] assign SourceIdSet_1 = a_first_1 & _T_35 & ~a_notFIFO_1 ? _SourceIdSet_T_1[23:0] : 24'h0; // @[OneHot.scala:58:35] wire [31:0] _SourceIdClear_T_1 = 32'h1 << anonIn_1_d_bits_source; // @[OneHot.scala:58:35] assign SourceIdClear_1 = d_first_1 & _T_39 ? _SourceIdClear_T_1[23:0] : 24'h0; // @[OneHot.scala:58:35] wire [23:0] _SourceIdFIFOed_T_1 = SourceIdFIFOed_1 | SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire allIDs_FIFOed_1 = &SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41] wire _T_1 = a_first & _a_first_T; // @[Decoupled.scala:51:35] wire _T_3 = d_first & _T_9; // @[Decoupled.scala:51:35] wire _T_31 = a_first_1 & _T_35; // @[Decoupled.scala:51:35] wire _T_33 = d_first_1 & _T_39; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[FIFOFixer.scala:50:9] if (reset) begin // @[FIFOFixer.scala:50:9] a_first_counter <= 9'h0; // @[Edges.scala:229:27] d_first_counter <= 9'h0; // @[Edges.scala:229:27] flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] SourceIdFIFOed <= 17'h0; // @[FIFOFixer.scala:115:35] a_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] d_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_2 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_3 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_4 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_5 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_6 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_7 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_8 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_9 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_10 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_11 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_12 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_13 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_14 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_15 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_16 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_17 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_18 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_19 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_20 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_21 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_22 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1_23 <= 1'h0; // @[FIFOFixer.scala:79:27] SourceIdFIFOed_1 <= 24'h0; // @[FIFOFixer.scala:115:35] end else begin // @[FIFOFixer.scala:50:9] if (_a_first_T) // @[Decoupled.scala:51:35] a_first_counter <= _a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (_d_first_T) // @[Decoupled.scala:51:35] d_first_counter <= _d_first_counter_T; // @[Edges.scala:229:27, :236:21] flight_0 <= ~(_T_3 & anonIn_d_bits_source == 5'h0) & (_T_1 & anonIn_a_bits_source == 5'h0 ? _flight_T : flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1 <= ~(_T_3 & anonIn_d_bits_source == 5'h1) & (_T_1 & anonIn_a_bits_source == 5'h1 ? _flight_T : flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_2 <= ~(_T_3 & anonIn_d_bits_source == 5'h2) & (_T_1 & anonIn_a_bits_source == 5'h2 ? _flight_T : flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_3 <= ~(_T_3 & anonIn_d_bits_source == 5'h3) & (_T_1 & anonIn_a_bits_source == 5'h3 ? _flight_T : flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_4 <= ~(_T_3 & anonIn_d_bits_source == 5'h4) & (_T_1 & anonIn_a_bits_source == 5'h4 ? _flight_T : flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_5 <= ~(_T_3 & anonIn_d_bits_source == 5'h5) & (_T_1 & anonIn_a_bits_source == 5'h5 ? _flight_T : flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_6 <= ~(_T_3 & anonIn_d_bits_source == 5'h6) & (_T_1 & anonIn_a_bits_source == 5'h6 ? _flight_T : flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_7 <= ~(_T_3 & anonIn_d_bits_source == 5'h7) & (_T_1 & anonIn_a_bits_source == 5'h7 ? _flight_T : flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_8 <= ~(_T_3 & anonIn_d_bits_source == 5'h8) & (_T_1 & anonIn_a_bits_source == 5'h8 ? _flight_T : flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_9 <= ~(_T_3 & anonIn_d_bits_source == 5'h9) & (_T_1 & anonIn_a_bits_source == 5'h9 ? _flight_T : flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_10 <= ~(_T_3 & anonIn_d_bits_source == 5'hA) & (_T_1 & anonIn_a_bits_source == 5'hA ? _flight_T : flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_11 <= ~(_T_3 & anonIn_d_bits_source == 5'hB) & (_T_1 & anonIn_a_bits_source == 5'hB ? _flight_T : flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_12 <= ~(_T_3 & anonIn_d_bits_source == 5'hC) & (_T_1 & anonIn_a_bits_source == 5'hC ? _flight_T : flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_13 <= ~(_T_3 & anonIn_d_bits_source == 5'hD) & (_T_1 & anonIn_a_bits_source == 5'hD ? _flight_T : flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_14 <= ~(_T_3 & anonIn_d_bits_source == 5'hE) & (_T_1 & anonIn_a_bits_source == 5'hE ? _flight_T : flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_15 <= ~(_T_3 & anonIn_d_bits_source == 5'hF) & (_T_1 & anonIn_a_bits_source == 5'hF ? _flight_T : flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_16 <= ~(_T_3 & anonIn_d_bits_source == 5'h10) & (_T_1 & anonIn_a_bits_source == 5'h10 ? _flight_T : flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] SourceIdFIFOed <= _SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (_a_first_T_1) // @[Decoupled.scala:51:35] a_first_counter_1 <= _a_first_counter_T_1; // @[Edges.scala:229:27, :236:21] if (_d_first_T_2) // @[Decoupled.scala:51:35] d_first_counter_1 <= _d_first_counter_T_1; // @[Edges.scala:229:27, :236:21] flight_1_0 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h0) & (_T_31 & anonIn_1_a_bits_source == 5'h0 ? _flight_T_1 : flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_1 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h1) & (_T_31 & anonIn_1_a_bits_source == 5'h1 ? _flight_T_1 : flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_2 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h2) & (_T_31 & anonIn_1_a_bits_source == 5'h2 ? _flight_T_1 : flight_1_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_3 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h3) & (_T_31 & anonIn_1_a_bits_source == 5'h3 ? _flight_T_1 : flight_1_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_4 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h4) & (_T_31 & anonIn_1_a_bits_source == 5'h4 ? _flight_T_1 : flight_1_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_5 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h5) & (_T_31 & anonIn_1_a_bits_source == 5'h5 ? _flight_T_1 : flight_1_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_6 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h6) & (_T_31 & anonIn_1_a_bits_source == 5'h6 ? _flight_T_1 : flight_1_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_7 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h7) & (_T_31 & anonIn_1_a_bits_source == 5'h7 ? _flight_T_1 : flight_1_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_8 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h8) & (_T_31 & anonIn_1_a_bits_source == 5'h8 ? _flight_T_1 : flight_1_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_9 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h9) & (_T_31 & anonIn_1_a_bits_source == 5'h9 ? _flight_T_1 : flight_1_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_10 <= ~(_T_33 & anonIn_1_d_bits_source == 5'hA) & (_T_31 & anonIn_1_a_bits_source == 5'hA ? _flight_T_1 : flight_1_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_11 <= ~(_T_33 & anonIn_1_d_bits_source == 5'hB) & (_T_31 & anonIn_1_a_bits_source == 5'hB ? _flight_T_1 : flight_1_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_12 <= ~(_T_33 & anonIn_1_d_bits_source == 5'hC) & (_T_31 & anonIn_1_a_bits_source == 5'hC ? _flight_T_1 : flight_1_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_13 <= ~(_T_33 & anonIn_1_d_bits_source == 5'hD) & (_T_31 & anonIn_1_a_bits_source == 5'hD ? _flight_T_1 : flight_1_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_14 <= ~(_T_33 & anonIn_1_d_bits_source == 5'hE) & (_T_31 & anonIn_1_a_bits_source == 5'hE ? _flight_T_1 : flight_1_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_15 <= ~(_T_33 & anonIn_1_d_bits_source == 5'hF) & (_T_31 & anonIn_1_a_bits_source == 5'hF ? _flight_T_1 : flight_1_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_16 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h10) & (_T_31 & anonIn_1_a_bits_source == 5'h10 ? _flight_T_1 : flight_1_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_17 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h11) & (_T_31 & anonIn_1_a_bits_source == 5'h11 ? _flight_T_1 : flight_1_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_18 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h12) & (_T_31 & anonIn_1_a_bits_source == 5'h12 ? _flight_T_1 : flight_1_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_19 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h13) & (_T_31 & anonIn_1_a_bits_source == 5'h13 ? _flight_T_1 : flight_1_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_20 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h14) & (_T_31 & anonIn_1_a_bits_source == 5'h14 ? _flight_T_1 : flight_1_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_21 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h15) & (_T_31 & anonIn_1_a_bits_source == 5'h15 ? _flight_T_1 : flight_1_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_22 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h16) & (_T_31 & anonIn_1_a_bits_source == 5'h16 ? _flight_T_1 : flight_1_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] flight_1_23 <= ~(_T_33 & anonIn_1_d_bits_source == 5'h17) & (_T_31 & anonIn_1_a_bits_source == 5'h17 ? _flight_T_1 : flight_1_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] SourceIdFIFOed_1 <= _SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) TLMonitor_2 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_3 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (anonIn_1_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (anonIn_1_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (anonIn_1_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (anonIn_1_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (anonIn_1_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (anonIn_1_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (anonIn_1_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (anonIn_1_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (anonIn_1_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (anonIn_1_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (anonIn_1_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (anonIn_1_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (anonIn_1_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_1_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_1_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_1_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_1_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_1_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (anonIn_1_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (anonIn_1_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_anon_in_1_a_ready = auto_anon_in_1_a_ready_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_valid = auto_anon_in_1_b_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_bits_param = auto_anon_in_1_b_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_b_bits_address = auto_anon_in_1_b_bits_address_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_c_ready = auto_anon_in_1_c_ready_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_valid = auto_anon_in_1_d_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_opcode = auto_anon_in_1_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_param = auto_anon_in_1_d_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_size = auto_anon_in_1_d_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_source = auto_anon_in_1_d_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_sink = auto_anon_in_1_d_bits_sink_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_denied = auto_anon_in_1_d_bits_denied_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_data = auto_anon_in_1_d_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_1_d_bits_corrupt = auto_anon_in_1_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_a_ready = auto_anon_in_0_a_ready_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_valid = auto_anon_in_0_d_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_opcode = auto_anon_in_0_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_param = auto_anon_in_0_d_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_size = auto_anon_in_0_d_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_source = auto_anon_in_0_d_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_sink = auto_anon_in_0_d_bits_sink_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_denied = auto_anon_in_0_d_bits_denied_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_data = auto_anon_in_0_d_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_0_d_bits_corrupt = auto_anon_in_0_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_valid = auto_anon_out_1_a_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_opcode = auto_anon_out_1_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_param = auto_anon_out_1_a_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_size = auto_anon_out_1_a_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_source = auto_anon_out_1_a_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_address = auto_anon_out_1_a_bits_address_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_mask = auto_anon_out_1_a_bits_mask_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_data = auto_anon_out_1_a_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_a_bits_corrupt = auto_anon_out_1_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_b_ready = auto_anon_out_1_b_ready_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_valid = auto_anon_out_1_c_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_opcode = auto_anon_out_1_c_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_param = auto_anon_out_1_c_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_size = auto_anon_out_1_c_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_source = auto_anon_out_1_c_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_address = auto_anon_out_1_c_bits_address_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_data = auto_anon_out_1_c_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_c_bits_corrupt = auto_anon_out_1_c_bits_corrupt_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_d_ready = auto_anon_out_1_d_ready_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_e_valid = auto_anon_out_1_e_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_1_e_bits_sink = auto_anon_out_1_e_bits_sink_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_valid = auto_anon_out_0_a_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_opcode = auto_anon_out_0_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_param = auto_anon_out_0_a_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_size = auto_anon_out_0_a_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_source = auto_anon_out_0_a_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_address = auto_anon_out_0_a_bits_address_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_mask = auto_anon_out_0_a_bits_mask_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_data = auto_anon_out_0_a_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_a_bits_corrupt = auto_anon_out_0_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_0_d_ready = auto_anon_out_0_d_ready_0; // @[FIFOFixer.scala:50:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s3k1z3u_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_57 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s3k1z3u_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s3k1z3u_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<3>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<3>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<3>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<3>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLBuffer_a28d64s3k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_57 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s3k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s3k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_134 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_134( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_360 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_360( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_118 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_118 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RoundRawFNToRecFN_e8_s24_118( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_118 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_448 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_192 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_448( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_192 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64_mulAddZ31_1 : input clock : Clock input reset : Reset output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} inst divSqrtRecF64ToRaw of DivSqrtRecF64ToRaw_mulAddZ31_1 connect divSqrtRecF64ToRaw.clock, clock connect divSqrtRecF64ToRaw.reset, reset connect io.inReady_div, divSqrtRecF64ToRaw.io.inReady_div connect io.inReady_sqrt, divSqrtRecF64ToRaw.io.inReady_sqrt connect divSqrtRecF64ToRaw.io.inValid, io.inValid connect divSqrtRecF64ToRaw.io.sqrtOp, io.sqrtOp connect divSqrtRecF64ToRaw.io.a, io.a connect divSqrtRecF64ToRaw.io.b, io.b connect divSqrtRecF64ToRaw.io.roundingMode, io.roundingMode connect io.usingMulAdd, divSqrtRecF64ToRaw.io.usingMulAdd connect io.latchMulAddA_0, divSqrtRecF64ToRaw.io.latchMulAddA_0 connect io.mulAddA_0, divSqrtRecF64ToRaw.io.mulAddA_0 connect io.latchMulAddB_0, divSqrtRecF64ToRaw.io.latchMulAddB_0 connect io.mulAddB_0, divSqrtRecF64ToRaw.io.mulAddB_0 connect io.mulAddC_2, divSqrtRecF64ToRaw.io.mulAddC_2 connect divSqrtRecF64ToRaw.io.mulAddResult_3, io.mulAddResult_3 connect io.outValid_div, divSqrtRecF64ToRaw.io.rawOutValid_div connect io.outValid_sqrt, divSqrtRecF64ToRaw.io.rawOutValid_sqrt inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_7 connect roundRawFNToRecFN.io.invalidExc, divSqrtRecF64ToRaw.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecF64ToRaw.io.infiniteExc connect roundRawFNToRecFN.io.in.sig, divSqrtRecF64ToRaw.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, divSqrtRecF64ToRaw.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, divSqrtRecF64ToRaw.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, divSqrtRecF64ToRaw.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, divSqrtRecF64ToRaw.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecF64ToRaw.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, divSqrtRecF64ToRaw.io.roundingModeOut connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags
module DivSqrtRecF64_mulAddZ31_1( // @[DivSqrtRecF64_mulAddZ31.scala:719:7] input clock, // @[DivSqrtRecF64_mulAddZ31.scala:719:7] input reset, // @[DivSqrtRecF64_mulAddZ31.scala:719:7] output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_outValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_outValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [64:0] io_out, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [4:0] io_exceptionFlags // @[DivSqrtRecF64_mulAddZ31.scala:721:16] ); wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_invalidExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_infiniteExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isNaN; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isInf; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isZero; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_sign; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_detectTininess = 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7, :721:16, :775:15] wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] DivSqrtRecF64ToRaw_mulAddZ31_1 divSqrtRecF64ToRaw ( // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .clock (clock), .reset (reset), .io_inReady_div (io_inReady_div_0), .io_inReady_sqrt (io_inReady_sqrt_0), .io_inValid (io_inValid_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_a (io_a_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_b (io_b_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_usingMulAdd (io_usingMulAdd_0), .io_latchMulAddA_0 (io_latchMulAddA_0_0), .io_mulAddA_0 (io_mulAddA_0_0), .io_latchMulAddB_0 (io_latchMulAddB_0_0), .io_mulAddB_0 (io_mulAddB_0_0), .io_mulAddC_2 (io_mulAddC_2_0), .io_mulAddResult_3 (io_mulAddResult_3_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_rawOutValid_div (io_outValid_div_0), .io_rawOutValid_sqrt (io_outValid_sqrt_0), .io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut), .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), .io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), .io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), .io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), .io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), .io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), .io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig) ); // @[DivSqrtRecF64_mulAddZ31.scala:751:36] RoundRawFNToRecFN_e11_s53_7 roundRawFNToRecFN ( // @[DivSqrtRecF64_mulAddZ31.scala:775:15] .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[DivSqrtRecF64_mulAddZ31.scala:775:15] assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_out = io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_149 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_405 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_149( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_405 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_69 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_34 = and(_T_32, _T_33) node _T_35 = or(UInt<1>(0h0), _T_34) node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_37 = cvt(_T_36) node _T_38 = and(_T_37, asSInt(UInt<17>(0h101c0))) node _T_39 = asSInt(_T_38) node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0))) node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<29>(0h100001c0))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = or(_T_40, _T_45) node _T_47 = and(_T_35, _T_46) node _T_48 = or(UInt<1>(0h0), _T_47) node _T_49 = and(_T_31, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_49, UInt<1>(0h1), "") : assert_2 node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_56 = and(_T_54, _T_55) node _T_57 = or(UInt<1>(0h0), _T_56) node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<17>(0h101c0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<29>(0h100001c0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _T_69 = and(_T_57, _T_68) node _T_70 = or(UInt<1>(0h0), _T_69) node _T_71 = and(_T_53, _T_70) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(is_aligned, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_85, UInt<1>(0h1), "") : assert_7 node _T_89 = not(io.in.a.bits.mask) node _T_90 = eq(_T_89, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_90, UInt<1>(0h1), "") : assert_8 node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_102 = shr(io.in.a.bits.source, 4) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = leq(UInt<1>(0h0), uncommonBits_2) node _T_105 = and(_T_103, _T_104) node _T_106 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_107 = and(_T_105, _T_106) node _T_108 = and(_T_101, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_112 = and(_T_110, _T_111) node _T_113 = or(UInt<1>(0h0), _T_112) node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<17>(0h101c0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<29>(0h100001c0))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = and(_T_113, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = and(_T_109, _T_126) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_127, UInt<1>(0h1), "") : assert_10 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h101c0))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<29>(0h100001c0))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = or(_T_140, _T_145) node _T_147 = and(_T_135, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = and(_T_131, _T_148) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_149, UInt<1>(0h1), "") : assert_11 node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_156, UInt<1>(0h1), "") : assert_13 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(is_aligned, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_163, UInt<1>(0h1), "") : assert_15 node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_167, UInt<1>(0h1), "") : assert_16 node _T_171 = not(io.in.a.bits.mask) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(_T_172, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_172, UInt<1>(0h1), "") : assert_17 node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_176, UInt<1>(0h1), "") : assert_18 node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_180 : node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_183 = and(_T_181, _T_182) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_184 = shr(io.in.a.bits.source, 4) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_3) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_189 = and(_T_187, _T_188) node _T_190 = and(_T_183, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_191, UInt<1>(0h1), "") : assert_19 node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h101c0))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<29>(0h100001c0))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_203, _T_208) node _T_210 = and(_T_198, _T_209) node _T_211 = or(UInt<1>(0h0), _T_210) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_211, UInt<1>(0h1), "") : assert_20 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(is_aligned, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_221, UInt<1>(0h1), "") : assert_23 node _T_225 = eq(io.in.a.bits.mask, mask) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_225, UInt<1>(0h1), "") : assert_24 node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_229, UInt<1>(0h1), "") : assert_25 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_4) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_247 = and(_T_245, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h101c0))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<29>(0h100001c0))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = or(_T_253, _T_258) node _T_260 = and(_T_248, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = and(_T_244, _T_261) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_262, UInt<1>(0h1), "") : assert_26 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(is_aligned, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_272, UInt<1>(0h1), "") : assert_29 node _T_276 = eq(io.in.a.bits.mask, mask) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_276, UInt<1>(0h1), "") : assert_30 node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_280 : node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_284 = shr(io.in.a.bits.source, 4) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_5) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_289 = and(_T_287, _T_288) node _T_290 = and(_T_283, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_294 = and(_T_292, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h101c0))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h100001c0))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(_T_291, _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_309, UInt<1>(0h1), "") : assert_31 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_319, UInt<1>(0h1), "") : assert_34 node _T_323 = not(mask) node _T_324 = and(io.in.a.bits.mask, _T_323) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_325, UInt<1>(0h1), "") : assert_35 node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_333 = shr(io.in.a.bits.source, 4) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_6) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_338 = and(_T_336, _T_337) node _T_339 = and(_T_332, _T_338) node _T_340 = or(UInt<1>(0h0), _T_339) node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h101c0))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<29>(0h100001c0))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = or(_T_346, _T_351) node _T_353 = and(_T_341, _T_352) node _T_354 = or(UInt<1>(0h0), _T_353) node _T_355 = and(_T_340, _T_354) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_355, UInt<1>(0h1), "") : assert_36 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(is_aligned, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_365, UInt<1>(0h1), "") : assert_39 node _T_369 = eq(io.in.a.bits.mask, mask) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_369, UInt<1>(0h1), "") : assert_40 node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_373 : node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_377 = shr(io.in.a.bits.source, 4) node _T_378 = eq(_T_377, UInt<1>(0h0)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_7) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_382 = and(_T_380, _T_381) node _T_383 = and(_T_376, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h101c0))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<29>(0h100001c0))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = or(_T_390, _T_395) node _T_397 = and(_T_385, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = and(_T_384, _T_398) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_399, UInt<1>(0h1), "") : assert_41 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(is_aligned, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_409, UInt<1>(0h1), "") : assert_44 node _T_413 = eq(io.in.a.bits.mask, mask) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_413, UInt<1>(0h1), "") : assert_45 node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_417 : node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_421 = shr(io.in.a.bits.source, 4) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_8) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_426 = and(_T_424, _T_425) node _T_427 = and(_T_420, _T_426) node _T_428 = or(UInt<1>(0h0), _T_427) node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<17>(0h101c0))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<29>(0h100001c0))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = or(_T_434, _T_439) node _T_441 = and(_T_429, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_T_428, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_443, UInt<1>(0h1), "") : assert_46 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(is_aligned, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_453, UInt<1>(0h1), "") : assert_49 node _T_457 = eq(io.in.a.bits.mask, mask) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_457, UInt<1>(0h1), "") : assert_50 node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_461, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_465, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_469 : node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_473, UInt<1>(0h1), "") : assert_54 node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_477, UInt<1>(0h1), "") : assert_55 node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_481, UInt<1>(0h1), "") : assert_56 node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_485, UInt<1>(0h1), "") : assert_57 node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(sink_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_496, UInt<1>(0h1), "") : assert_60 node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_500, UInt<1>(0h1), "") : assert_61 node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_504, UInt<1>(0h1), "") : assert_62 node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_508, UInt<1>(0h1), "") : assert_63 node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_513 = or(UInt<1>(0h1), _T_512) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_513, UInt<1>(0h1), "") : assert_64 node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_517 : node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(sink_ok, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_524, UInt<1>(0h1), "") : assert_67 node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_528, UInt<1>(0h1), "") : assert_68 node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_532, UInt<1>(0h1), "") : assert_69 node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_537 = or(_T_536, io.in.d.bits.corrupt) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_537, UInt<1>(0h1), "") : assert_70 node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_542 = or(UInt<1>(0h1), _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_542, UInt<1>(0h1), "") : assert_71 node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_546 : node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_550, UInt<1>(0h1), "") : assert_73 node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_554, UInt<1>(0h1), "") : assert_74 node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_559 = or(UInt<1>(0h1), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_559, UInt<1>(0h1), "") : assert_75 node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_563 : node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_567, UInt<1>(0h1), "") : assert_77 node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_572 = or(_T_571, io.in.d.bits.corrupt) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_572, UInt<1>(0h1), "") : assert_78 node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_577 = or(UInt<1>(0h1), _T_576) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_577, UInt<1>(0h1), "") : assert_79 node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_581 : node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_585, UInt<1>(0h1), "") : assert_81 node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_589, UInt<1>(0h1), "") : assert_82 node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_594 = or(UInt<1>(0h1), _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_594, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_598, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_602 = shr(io.in.b.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_9) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_9, UInt<4>(0h9)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_608, _T_613) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_614, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0) node _legal_source_T = shr(io.in.b.bits.source, 4) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h9)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) wire _legal_source_WIRE : UInt<1>[1] connect _legal_source_WIRE[0], _legal_source_T_5 node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source) node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_618 : node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h101c0))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<29>(0h100001c0))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_637, UInt<1>(0h1), "") : assert_86 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(address_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(legal_source, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(is_aligned_1, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_650, UInt<1>(0h1), "") : assert_90 node _T_654 = eq(io.in.b.bits.mask, mask_1) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_654, UInt<1>(0h1), "") : assert_91 node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_658, UInt<1>(0h1), "") : assert_92 node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_662 : node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h101c0))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<29>(0h100001c0))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = or(_T_671, _T_676) node _T_678 = and(_T_666, _T_677) node _T_679 = or(UInt<1>(0h0), _T_678) node _T_680 = and(UInt<1>(0h0), _T_679) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_680, UInt<1>(0h1), "") : assert_93 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(address_ok, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(legal_source, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(is_aligned_1, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_693, UInt<1>(0h1), "") : assert_97 node _T_697 = eq(io.in.b.bits.mask, mask_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_697, UInt<1>(0h1), "") : assert_98 node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_701, UInt<1>(0h1), "") : assert_99 node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_705 : node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_708 = and(_T_706, _T_707) node _T_709 = or(UInt<1>(0h0), _T_708) node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h101c0))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<29>(0h100001c0))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_714, _T_719) node _T_721 = and(_T_709, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = and(UInt<1>(0h0), _T_722) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_723, UInt<1>(0h1), "") : assert_100 node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(address_ok, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(legal_source, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned_1, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_736, UInt<1>(0h1), "") : assert_104 node _T_740 = eq(io.in.b.bits.mask, mask_1) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_740, UInt<1>(0h1), "") : assert_105 node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h101c0))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<29>(0h100001c0))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = or(_T_753, _T_758) node _T_760 = and(_T_748, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = and(UInt<1>(0h0), _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_762, UInt<1>(0h1), "") : assert_106 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(address_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(legal_source, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned_1, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_775, UInt<1>(0h1), "") : assert_110 node _T_779 = not(mask_1) node _T_780 = and(io.in.b.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_781, UInt<1>(0h1), "") : assert_111 node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h101c0))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h100001c0))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_794, _T_799) node _T_801 = and(_T_789, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = and(UInt<1>(0h0), _T_802) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_803, UInt<1>(0h1), "") : assert_112 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(address_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(legal_source, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned_1, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_816, UInt<1>(0h1), "") : assert_116 node _T_820 = eq(io.in.b.bits.mask, mask_1) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_820, UInt<1>(0h1), "") : assert_117 node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<17>(0h101c0))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<29>(0h100001c0))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = or(_T_833, _T_838) node _T_840 = and(_T_828, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = and(UInt<1>(0h0), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_842, UInt<1>(0h1), "") : assert_118 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(address_ok, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(legal_source, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(is_aligned_1, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_855, UInt<1>(0h1), "") : assert_122 node _T_859 = eq(io.in.b.bits.mask, mask_1) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_859, UInt<1>(0h1), "") : assert_123 node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_863 : node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_866 = and(_T_864, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<17>(0h101c0))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<29>(0h100001c0))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = or(_T_872, _T_877) node _T_879 = and(_T_867, _T_878) node _T_880 = or(UInt<1>(0h0), _T_879) node _T_881 = and(UInt<1>(0h0), _T_880) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_881, UInt<1>(0h1), "") : assert_124 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(address_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(legal_source, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_894 = eq(io.in.b.bits.mask, mask_1) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_894, UInt<1>(0h1), "") : assert_128 node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_898, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_902, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.c.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE_2 : UInt<1>[1] connect _source_ok_WIRE_2[0], _source_ok_T_17 node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_906 = shr(io.in.c.bits.source, 4) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_10) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_10, UInt<4>(0h9)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(_T_911, UInt<1>(0h0)) node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = or(_T_912, _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_918, UInt<1>(0h1), "") : assert_131 node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok_1, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133 node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_929, UInt<1>(0h1), "") : assert_134 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned_2, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_936, UInt<1>(0h1), "") : assert_136 node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_940, UInt<1>(0h1), "") : assert_137 node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(address_ok_1, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139 node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_951, UInt<1>(0h1), "") : assert_140 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned_2, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_958, UInt<1>(0h1), "") : assert_142 node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_962 : node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_966 = shr(io.in.c.bits.source, 4) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_11) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_11, UInt<4>(0h9)) node _T_971 = and(_T_969, _T_970) node _T_972 = and(_T_965, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h101c0))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h100001c0))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_989) node _T_991 = and(_T_973, _T_990) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_991, UInt<1>(0h1), "") : assert_143 node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h101c0))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h100001c0))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_1004, _T_1009) node _T_1011 = and(_T_999, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = and(_T_995, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145 node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148 node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149 node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_1039 = shr(io.in.c.bits.source, 4) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = leq(uncommonBits_12, UInt<4>(0h9)) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = and(_T_1038, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h101c0))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h100001c0))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = or(_T_1055, _T_1060) node _T_1062 = and(_T_1050, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1046, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150 node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(UInt<1>(0h0), _T_1071) node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h101c0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h100001c0))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = or(_T_1077, _T_1082) node _T_1084 = and(_T_1072, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = and(_T_1068, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152 node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153 node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155 node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1104 : node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(address_ok_1, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157 node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159 node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160 node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(address_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162 node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164 node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1136 : node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(address_ok_1, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168 node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1157 = eq(a_first, UInt<1>(0h0)) node _T_1158 = and(io.in.a.valid, _T_1157) when _T_1158 : node _T_1159 = eq(io.in.a.bits.opcode, opcode) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171 node _T_1163 = eq(io.in.a.bits.param, param) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172 node _T_1167 = eq(io.in.a.bits.size, size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173 node _T_1171 = eq(io.in.a.bits.source, source) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174 node _T_1175 = eq(io.in.a.bits.address, address) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175 node _T_1179 = and(io.in.a.ready, io.in.a.valid) node _T_1180 = and(_T_1179, a_first) when _T_1180 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1181 = eq(d_first, UInt<1>(0h0)) node _T_1182 = and(io.in.d.valid, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.bits.opcode, opcode_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176 node _T_1187 = eq(io.in.d.bits.param, param_1) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177 node _T_1191 = eq(io.in.d.bits.size, size_1) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178 node _T_1195 = eq(io.in.d.bits.source, source_1) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179 node _T_1199 = eq(io.in.d.bits.sink, sink) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180 node _T_1203 = eq(io.in.d.bits.denied, denied) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181 node _T_1207 = and(io.in.d.ready, io.in.d.valid) node _T_1208 = and(_T_1207, d_first) when _T_1208 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1209 = eq(b_first, UInt<1>(0h0)) node _T_1210 = and(io.in.b.valid, _T_1209) when _T_1210 : node _T_1211 = eq(io.in.b.bits.opcode, opcode_2) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182 node _T_1215 = eq(io.in.b.bits.param, param_2) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183 node _T_1219 = eq(io.in.b.bits.size, size_2) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184 node _T_1223 = eq(io.in.b.bits.source, source_2) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185 node _T_1227 = eq(io.in.b.bits.address, address_1) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186 node _T_1231 = and(io.in.b.ready, io.in.b.valid) node _T_1232 = and(_T_1231, b_first) when _T_1232 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1233 = eq(c_first, UInt<1>(0h0)) node _T_1234 = and(io.in.c.valid, _T_1233) when _T_1234 : node _T_1235 = eq(io.in.c.bits.opcode, opcode_3) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187 node _T_1239 = eq(io.in.c.bits.param, param_3) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188 node _T_1243 = eq(io.in.c.bits.size, size_3) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189 node _T_1247 = eq(io.in.c.bits.source, source_3) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190 node _T_1251 = eq(io.in.c.bits.address, address_2) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191 node _T_1255 = and(io.in.c.ready, io.in.c.valid) node _T_1256 = and(_T_1255, c_first) when _T_1256 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1257 = and(io.in.a.valid, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(_T_1259, a_first_1) node _T_1261 = and(_T_1260, UInt<1>(0h1)) when _T_1261 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1262 = dshr(inflight, io.in.a.bits.source) node _T_1263 = bits(_T_1262, 0, 0) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1268 = and(io.in.d.valid, d_first_1) node _T_1269 = and(_T_1268, UInt<1>(0h1)) node _T_1270 = eq(d_release_ack, UInt<1>(0h0)) node _T_1271 = and(_T_1269, _T_1270) when _T_1271 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1272 = and(io.in.d.ready, io.in.d.valid) node _T_1273 = and(_T_1272, d_first_1) node _T_1274 = and(_T_1273, UInt<1>(0h1)) node _T_1275 = eq(d_release_ack, UInt<1>(0h0)) node _T_1276 = and(_T_1274, _T_1275) when _T_1276 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1277 = and(io.in.d.valid, d_first_1) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = eq(d_release_ack, UInt<1>(0h0)) node _T_1280 = and(_T_1278, _T_1279) when _T_1280 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1281 = dshr(inflight, io.in.d.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = or(_T_1282, same_cycle_resp) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194 node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195 else : node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1299 = or(_T_1297, _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196 node _T_1303 = eq(io.in.d.bits.size, a_size_lookup) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197 node _T_1307 = and(io.in.d.valid, d_first_1) node _T_1308 = and(_T_1307, a_first_1) node _T_1309 = and(_T_1308, io.in.a.valid) node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = eq(d_release_ack, UInt<1>(0h0)) node _T_1313 = and(_T_1311, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1315 = or(_T_1314, io.in.a.ready) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198 node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1320 = orr(a_set_wo_ready) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) node _T_1322 = or(_T_1319, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_138 node _T_1326 = orr(inflight) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1329 = or(_T_1327, _T_1328) node _T_1330 = lt(watchdog, plusarg_reader.out) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(io.in.d.ready, io.in.d.valid) node _T_1337 = or(_T_1335, _T_1336) when _T_1337 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_1338 = and(io.in.c.valid, c_first_1) node _T_1339 = bits(io.in.c.bits.opcode, 2, 2) node _T_1340 = bits(io.in.c.bits.opcode, 1, 1) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = and(_T_1338, _T_1341) when _T_1342 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1343 = and(io.in.c.ready, io.in.c.valid) node _T_1344 = and(_T_1343, c_first_1) node _T_1345 = bits(io.in.c.bits.opcode, 2, 2) node _T_1346 = bits(io.in.c.bits.opcode, 1, 1) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = and(_T_1344, _T_1347) when _T_1348 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1349 = dshr(inflight_1, io.in.c.bits.source) node _T_1350 = bits(_T_1349, 0, 0) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1358 = and(io.in.d.ready, io.in.d.valid) node _T_1359 = and(_T_1358, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1362 = and(io.in.d.valid, d_first_2) node _T_1363 = and(_T_1362, UInt<1>(0h1)) node _T_1364 = and(_T_1363, d_release_ack_1) when _T_1364 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1365 = dshr(inflight_1, io.in.d.bits.source) node _T_1366 = bits(_T_1365, 0, 0) node _T_1367 = or(_T_1366, same_cycle_resp_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203 else : node _T_1375 = eq(io.in.d.bits.size, c_size_lookup) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204 node _T_1379 = and(io.in.d.valid, d_first_2) node _T_1380 = and(_T_1379, c_first_1) node _T_1381 = and(_T_1380, io.in.c.valid) node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = and(_T_1383, d_release_ack_1) node _T_1385 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1386 = and(_T_1384, _T_1385) when _T_1386 : node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1388 = or(_T_1387, io.in.c.ready) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205 node _T_1392 = orr(c_set_wo_ready) when _T_1392 : node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_139 node _T_1397 = orr(inflight_1) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = lt(watchdog_1, plusarg_reader_1.out) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1406 = and(io.in.c.ready, io.in.c.valid) node _T_1407 = and(io.in.d.ready, io.in.d.valid) node _T_1408 = or(_T_1406, _T_1407) when _T_1408 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = and(_T_1409, d_first_3) node _T_1411 = bits(io.in.d.bits.opcode, 2, 2) node _T_1412 = bits(io.in.d.bits.opcode, 1, 1) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) node _T_1414 = and(_T_1411, _T_1413) node _T_1415 = and(_T_1410, _T_1414) when _T_1415 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1416 = dshr(inflight_2, io.in.d.bits.sink) node _T_1417 = bits(_T_1416, 0, 0) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1422 = and(io.in.e.ready, io.in.e.valid) node _T_1423 = and(_T_1422, UInt<1>(0h1)) node _T_1424 = and(_T_1423, UInt<1>(0h1)) when _T_1424 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1425 = or(d_set, inflight_2) node _T_1426 = dshr(_T_1425, io.in.e.bits.sink) node _T_1427 = bits(_T_1426, 0, 0) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_140 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_141 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_69( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h0; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h0; // @[Misc.scala:202:34] wire [2:0] b_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _b_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _b_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire io_in_b_valid = 1'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _address_ok_T_4 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_T_9 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_WIRE_0 = 1'h0; // @[Parameters.scala:612:40] wire _address_ok_WIRE_1 = 1'h0; // @[Parameters.scala:612:40] wire address_ok = 1'h0; // @[Parameters.scala:636:64] wire mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_bit_1 = 1'h0; // @[Misc.scala:210:26] wire mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_9 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_10 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_11 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_12 = 1'h0; // @[Parameters.scala:54:10] wire _b_first_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_first_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _b_first_last_T = 1'h0; // @[Edges.scala:232:25] wire b_first_done = 1'h0; // @[Edges.scala:233:22] wire io_in_b_ready = 1'h1; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire is_aligned_1 = 1'h1; // @[Edges.scala:21:24] wire mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire b_first_beats1_opdata = 1'h1; // @[Edges.scala:97:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] b_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _b_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [31:0] io_in_b_bits_address = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _is_aligned_T_1 = 32'h0; // @[Edges.scala:21:16] wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] uncommonBits_9 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] legal_source_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [1:0] io_in_b_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h0; // @[OneHot.scala:64:49] wire [1:0] mask_lo_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [7:0] io_in_b_bits_mask = 8'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] _mask_sizeOH_T_5 = 3'h1; // @[OneHot.scala:65:27] wire [2:0] mask_sizeOH_1 = 3'h1; // @[Misc.scala:202:81] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [5:0] is_aligned_mask_1 = 6'h0; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h3F; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'h3F; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [7:0] mask_1 = 8'h1; // @[Misc.scala:222:10] wire [3:0] _mask_sizeOH_T_4 = 4'h1; // @[OneHot.scala:65:12] wire [3:0] mask_lo_1 = 4'h1; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h1; // @[Misc.scala:222:10] wire [32:0] _address_ok_T_6 = 33'h800000C0; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_7 = 33'h800000C0; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_8 = 33'h800000C0; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T_5 = 32'h800000C0; // @[Parameters.scala:137:31] wire [32:0] _address_ok_T_1 = 33'h80000C0; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_2 = 33'h80000C0; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_3 = 33'h80000C0; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T = 32'h80000C0; // @[Parameters.scala:137:31] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_1 = io_in_c_bits_address_0[27:0] ^ 28'h80000C0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h800000C0; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire _T_1335 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1335; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1335; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1409; // @[Decoupled.scala:51:35] wire [12:0] _GEN_2 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_2; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _T_1406 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1406; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1406; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_3 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_4 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1261 = _T_1335 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1261 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1261 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1261 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_5 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_5; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_5; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1261 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1261 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_6 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_6; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_6; // @[Monitor.scala:673:46, :783:46] wire _T_1307 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_7 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1307 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1276 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1276 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1276 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1276 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] c_set; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_8 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_8; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1348 = _T_1406 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1348 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1348 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1348 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _GEN_9 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [6:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_9; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_9; // @[Monitor.scala:767:79, :768:77] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1348 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [130:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1348 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1379 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1379 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1361 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1361 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1361 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1361 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [9:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_1415 = _T_1409 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_10 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_10; // @[OneHot.scala:58:35] assign d_set = _T_1415 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_11; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_127 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_127( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SynchronizerShiftReg_w1_d3 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = bits(io.d, 0, 0) inst output_chain of NonSyncResetSynchronizerPrimitiveShiftReg_d3 connect output_chain.clock, clock connect output_chain.reset, reset connect output_chain.io.d, _output_T wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module SynchronizerShiftReg_w1_d3( // @[SynchronizerReg.scala:169:7] input clock, // @[SynchronizerReg.scala:169:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .io_d (io_d), .io_q (io_q) ); // @[ShiftReg.scala:45:23] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_68 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<27>(0h4000000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<13>(0h1000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = or(_T_727, _T_732) node _T_759 = or(_T_758, _T_737) node _T_760 = or(_T_759, _T_742) node _T_761 = or(_T_760, _T_747) node _T_762 = or(_T_761, _T_752) node _T_763 = or(_T_762, _T_757) node _T_764 = and(_T_722, _T_763) node _T_765 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_766 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_773 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_774 = and(_T_772, _T_773) node _T_775 = or(UInt<1>(0h0), _T_774) node _T_776 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<17>(0h10000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<29>(0h10000000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = or(_T_780, _T_785) node _T_787 = and(_T_775, _T_786) node _T_788 = or(UInt<1>(0h0), _T_764) node _T_789 = or(_T_788, _T_771) node _T_790 = or(_T_789, _T_787) node _T_791 = and(_T_718, _T_790) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_791, UInt<1>(0h1), "") : assert_36 node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(source_ok, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(is_aligned, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_801 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_801, UInt<1>(0h1), "") : assert_39 node _T_805 = eq(io.in.a.bits.mask, mask) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_805, UInt<1>(0h1), "") : assert_40 node _T_809 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_809 : node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_811 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_812 = and(_T_810, _T_811) node _T_813 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_814 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_815 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_816 = or(_T_813, _T_814) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_812, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<14>(0h2000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<13>(0h1000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<18>(0h2f000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<17>(0h10000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<13>(0h1000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = or(_T_828, _T_833) node _T_860 = or(_T_859, _T_838) node _T_861 = or(_T_860, _T_843) node _T_862 = or(_T_861, _T_848) node _T_863 = or(_T_862, _T_853) node _T_864 = or(_T_863, _T_858) node _T_865 = and(_T_823, _T_864) node _T_866 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_867 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = and(_T_866, _T_871) node _T_873 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_874 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_875 = and(_T_873, _T_874) node _T_876 = or(UInt<1>(0h0), _T_875) node _T_877 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_878 = cvt(_T_877) node _T_879 = and(_T_878, asSInt(UInt<17>(0h10000))) node _T_880 = asSInt(_T_879) node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0))) node _T_882 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<29>(0h10000000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = or(_T_881, _T_886) node _T_888 = and(_T_876, _T_887) node _T_889 = or(UInt<1>(0h0), _T_865) node _T_890 = or(_T_889, _T_872) node _T_891 = or(_T_890, _T_888) node _T_892 = and(_T_819, _T_891) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_892, UInt<1>(0h1), "") : assert_41 node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(source_ok, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(is_aligned, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_902 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_902, UInt<1>(0h1), "") : assert_44 node _T_906 = eq(io.in.a.bits.mask, mask) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_906, UInt<1>(0h1), "") : assert_45 node _T_910 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_910 : node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_915 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_916 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_917 = or(_T_914, _T_915) node _T_918 = or(_T_917, _T_916) node _T_919 = and(_T_913, _T_918) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_922 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_923 = and(_T_921, _T_922) node _T_924 = or(UInt<1>(0h0), _T_923) node _T_925 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_926 = cvt(_T_925) node _T_927 = and(_T_926, asSInt(UInt<13>(0h1000))) node _T_928 = asSInt(_T_927) node _T_929 = eq(_T_928, asSInt(UInt<1>(0h0))) node _T_930 = and(_T_924, _T_929) node _T_931 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<14>(0h2000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<18>(0h2f000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<17>(0h10000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<27>(0h4000000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_963 = cvt(_T_962) node _T_964 = and(_T_963, asSInt(UInt<13>(0h1000))) node _T_965 = asSInt(_T_964) node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0))) node _T_967 = or(_T_936, _T_941) node _T_968 = or(_T_967, _T_946) node _T_969 = or(_T_968, _T_951) node _T_970 = or(_T_969, _T_956) node _T_971 = or(_T_970, _T_961) node _T_972 = or(_T_971, _T_966) node _T_973 = and(_T_931, _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h10000))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h10000000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_930) node _T_991 = or(_T_990, _T_973) node _T_992 = or(_T_991, _T_989) node _T_993 = and(_T_920, _T_992) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_993, UInt<1>(0h1), "") : assert_46 node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(source_ok, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(is_aligned, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1003 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_49 node _T_1007 = eq(io.in.a.bits.mask, mask) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_50 node _T_1011 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1015 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<7>(0h40)) node _T_1019 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1023 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_54 node _T_1027 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_55 node _T_1031 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_56 node _T_1035 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_57 node _T_1039 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1039 : node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(source_ok_1, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(sink_ok, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1046 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_60 node _T_1050 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_61 node _T_1054 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_62 node _T_1058 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_63 node _T_1062 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1063 = or(UInt<1>(0h1), _T_1062) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_64 node _T_1067 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1067 : node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(source_ok_1, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(sink_ok, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1074 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_67 node _T_1078 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_68 node _T_1082 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_69 node _T_1086 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1087 = or(_T_1086, io.in.d.bits.corrupt) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_70 node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1092 = or(UInt<1>(0h1), _T_1091) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_71 node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1096 : node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(source_ok_1, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_73 node _T_1104 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_74 node _T_1108 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1109 = or(UInt<1>(0h1), _T_1108) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_75 node _T_1113 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok_1, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1117 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_77 node _T_1121 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1122 = or(_T_1121, io.in.d.bits.corrupt) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_78 node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1127 = or(UInt<1>(0h1), _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_79 node _T_1131 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1131 : node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(source_ok_1, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1135 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_81 node _T_1139 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_82 node _T_1143 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1144 = or(UInt<1>(0h1), _T_1143) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1148 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_84 node _T_1152 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) node _T_1154 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1155 = cvt(_T_1154) node _T_1156 = and(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = asSInt(_T_1156) node _T_1158 = eq(_T_1157, asSInt(UInt<1>(0h0))) node _T_1159 = or(_T_1153, _T_1158) node _T_1160 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) node _T_1162 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = or(_T_1161, _T_1166) node _T_1168 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) node _T_1170 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1171 = cvt(_T_1170) node _T_1172 = and(_T_1171, asSInt(UInt<1>(0h0))) node _T_1173 = asSInt(_T_1172) node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0))) node _T_1175 = or(_T_1169, _T_1174) node _T_1176 = and(_T_1159, _T_1167) node _T_1177 = and(_T_1176, _T_1175) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h100c0))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<17>(0h100c0))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<17>(0h100c0))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h100c0))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<27>(0h4000000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_66 = cvt(_address_ok_T_65) node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<13>(0h1000))) node _address_ok_T_68 = asSInt(_address_ok_T_67) node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0))) node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[18] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 connect _address_ok_WIRE[13], _address_ok_T_69 connect _address_ok_WIRE[14], _address_ok_T_74 connect _address_ok_WIRE[15], _address_ok_T_79 connect _address_ok_WIRE[16], _address_ok_T_84 connect _address_ok_WIRE[17], _address_ok_T_89 node _address_ok_T_90 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[2]) node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[3]) node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[4]) node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[5]) node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[6]) node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[7]) node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[8]) node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[9]) node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[10]) node _address_ok_T_100 = or(_address_ok_T_99, _address_ok_WIRE[11]) node _address_ok_T_101 = or(_address_ok_T_100, _address_ok_WIRE[12]) node _address_ok_T_102 = or(_address_ok_T_101, _address_ok_WIRE[13]) node _address_ok_T_103 = or(_address_ok_T_102, _address_ok_WIRE[14]) node _address_ok_T_104 = or(_address_ok_T_103, _address_ok_WIRE[15]) node _address_ok_T_105 = or(_address_ok_T_104, _address_ok_WIRE[16]) node address_ok = or(_address_ok_T_105, _address_ok_WIRE[17]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1181 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1181 : node _T_1182 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1183 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1184 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1182 connect _WIRE_4[1], _T_1183 connect _WIRE_4[2], _T_1184 node _T_1185 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1186 = mux(_WIRE_4[0], _T_1185, UInt<1>(0h0)) node _T_1187 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1188 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1189 = or(_T_1186, _T_1187) node _T_1190 = or(_T_1189, _T_1188) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1190 node _T_1191 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1192 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = or(UInt<1>(0h0), _T_1193) node _T_1195 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<14>(0h2000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<13>(0h1000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<18>(0h2f000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<13>(0h1000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<17>(0h10000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<27>(0h4000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<13>(0h1000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<29>(0h10000000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = or(_T_1199, _T_1204) node _T_1246 = or(_T_1245, _T_1209) node _T_1247 = or(_T_1246, _T_1214) node _T_1248 = or(_T_1247, _T_1219) node _T_1249 = or(_T_1248, _T_1224) node _T_1250 = or(_T_1249, _T_1229) node _T_1251 = or(_T_1250, _T_1234) node _T_1252 = or(_T_1251, _T_1239) node _T_1253 = or(_T_1252, _T_1244) node _T_1254 = and(_T_1194, _T_1253) node _T_1255 = or(UInt<1>(0h0), _T_1254) node _T_1256 = and(_WIRE_5, _T_1255) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_86 node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(address_ok, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(legal_source, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1269 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_90 node _T_1273 = eq(io.in.b.bits.mask, mask_1) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_91 node _T_1277 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_92 node _T_1281 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1281 : node _T_1282 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1283 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1284 = and(_T_1282, _T_1283) node _T_1285 = or(UInt<1>(0h0), _T_1284) node _T_1286 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<14>(0h2000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<13>(0h1000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<18>(0h2f000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<13>(0h1000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<17>(0h10000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<27>(0h4000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1327 = cvt(_T_1326) node _T_1328 = and(_T_1327, asSInt(UInt<13>(0h1000))) node _T_1329 = asSInt(_T_1328) node _T_1330 = eq(_T_1329, asSInt(UInt<1>(0h0))) node _T_1331 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1332 = cvt(_T_1331) node _T_1333 = and(_T_1332, asSInt(UInt<29>(0h10000000))) node _T_1334 = asSInt(_T_1333) node _T_1335 = eq(_T_1334, asSInt(UInt<1>(0h0))) node _T_1336 = or(_T_1290, _T_1295) node _T_1337 = or(_T_1336, _T_1300) node _T_1338 = or(_T_1337, _T_1305) node _T_1339 = or(_T_1338, _T_1310) node _T_1340 = or(_T_1339, _T_1315) node _T_1341 = or(_T_1340, _T_1320) node _T_1342 = or(_T_1341, _T_1325) node _T_1343 = or(_T_1342, _T_1330) node _T_1344 = or(_T_1343, _T_1335) node _T_1345 = and(_T_1285, _T_1344) node _T_1346 = or(UInt<1>(0h0), _T_1345) node _T_1347 = and(UInt<1>(0h0), _T_1346) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_93 node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(address_ok, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(legal_source, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1360 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_97 node _T_1364 = eq(io.in.b.bits.mask, mask_1) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_98 node _T_1368 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_99 node _T_1372 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1372 : node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1375 = and(_T_1373, _T_1374) node _T_1376 = or(UInt<1>(0h0), _T_1375) node _T_1377 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<14>(0h2000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<13>(0h1000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<18>(0h2f000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<13>(0h1000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<17>(0h10000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<27>(0h4000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1418 = cvt(_T_1417) node _T_1419 = and(_T_1418, asSInt(UInt<13>(0h1000))) node _T_1420 = asSInt(_T_1419) node _T_1421 = eq(_T_1420, asSInt(UInt<1>(0h0))) node _T_1422 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1423 = cvt(_T_1422) node _T_1424 = and(_T_1423, asSInt(UInt<29>(0h10000000))) node _T_1425 = asSInt(_T_1424) node _T_1426 = eq(_T_1425, asSInt(UInt<1>(0h0))) node _T_1427 = or(_T_1381, _T_1386) node _T_1428 = or(_T_1427, _T_1391) node _T_1429 = or(_T_1428, _T_1396) node _T_1430 = or(_T_1429, _T_1401) node _T_1431 = or(_T_1430, _T_1406) node _T_1432 = or(_T_1431, _T_1411) node _T_1433 = or(_T_1432, _T_1416) node _T_1434 = or(_T_1433, _T_1421) node _T_1435 = or(_T_1434, _T_1426) node _T_1436 = and(_T_1376, _T_1435) node _T_1437 = or(UInt<1>(0h0), _T_1436) node _T_1438 = and(UInt<1>(0h0), _T_1437) node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(_T_1438, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1438, UInt<1>(0h1), "") : assert_100 node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(address_ok, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1445 = asUInt(reset) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) when _T_1446 : node _T_1447 = eq(legal_source, UInt<1>(0h0)) when _T_1447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1451 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_104 node _T_1455 = eq(io.in.b.bits.mask, mask_1) node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(_T_1455, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1455, UInt<1>(0h1), "") : assert_105 node _T_1459 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1459 : node _T_1460 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1461 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1462 = and(_T_1460, _T_1461) node _T_1463 = or(UInt<1>(0h0), _T_1462) node _T_1464 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<14>(0h2000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<13>(0h1000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<18>(0h2f000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<13>(0h1000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<17>(0h10000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<27>(0h4000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1505 = cvt(_T_1504) node _T_1506 = and(_T_1505, asSInt(UInt<13>(0h1000))) node _T_1507 = asSInt(_T_1506) node _T_1508 = eq(_T_1507, asSInt(UInt<1>(0h0))) node _T_1509 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1510 = cvt(_T_1509) node _T_1511 = and(_T_1510, asSInt(UInt<29>(0h10000000))) node _T_1512 = asSInt(_T_1511) node _T_1513 = eq(_T_1512, asSInt(UInt<1>(0h0))) node _T_1514 = or(_T_1468, _T_1473) node _T_1515 = or(_T_1514, _T_1478) node _T_1516 = or(_T_1515, _T_1483) node _T_1517 = or(_T_1516, _T_1488) node _T_1518 = or(_T_1517, _T_1493) node _T_1519 = or(_T_1518, _T_1498) node _T_1520 = or(_T_1519, _T_1503) node _T_1521 = or(_T_1520, _T_1508) node _T_1522 = or(_T_1521, _T_1513) node _T_1523 = and(_T_1463, _T_1522) node _T_1524 = or(UInt<1>(0h0), _T_1523) node _T_1525 = and(UInt<1>(0h0), _T_1524) node _T_1526 = asUInt(reset) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) when _T_1527 : node _T_1528 = eq(_T_1525, UInt<1>(0h0)) when _T_1528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1525, UInt<1>(0h1), "") : assert_106 node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(address_ok, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(legal_source, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1538 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_110 node _T_1542 = not(mask_1) node _T_1543 = and(io.in.b.bits.mask, _T_1542) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_111 node _T_1548 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1548 : node _T_1549 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1550 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1551 = and(_T_1549, _T_1550) node _T_1552 = or(UInt<1>(0h0), _T_1551) node _T_1553 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<14>(0h2000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<13>(0h1000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<18>(0h2f000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<13>(0h1000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<17>(0h10000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<27>(0h4000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1594 = cvt(_T_1593) node _T_1595 = and(_T_1594, asSInt(UInt<13>(0h1000))) node _T_1596 = asSInt(_T_1595) node _T_1597 = eq(_T_1596, asSInt(UInt<1>(0h0))) node _T_1598 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1599 = cvt(_T_1598) node _T_1600 = and(_T_1599, asSInt(UInt<29>(0h10000000))) node _T_1601 = asSInt(_T_1600) node _T_1602 = eq(_T_1601, asSInt(UInt<1>(0h0))) node _T_1603 = or(_T_1557, _T_1562) node _T_1604 = or(_T_1603, _T_1567) node _T_1605 = or(_T_1604, _T_1572) node _T_1606 = or(_T_1605, _T_1577) node _T_1607 = or(_T_1606, _T_1582) node _T_1608 = or(_T_1607, _T_1587) node _T_1609 = or(_T_1608, _T_1592) node _T_1610 = or(_T_1609, _T_1597) node _T_1611 = or(_T_1610, _T_1602) node _T_1612 = and(_T_1552, _T_1611) node _T_1613 = or(UInt<1>(0h0), _T_1612) node _T_1614 = and(UInt<1>(0h0), _T_1613) node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(_T_1614, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1614, UInt<1>(0h1), "") : assert_112 node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(address_ok, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(legal_source, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1624 = asUInt(reset) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1627 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_116 node _T_1631 = eq(io.in.b.bits.mask, mask_1) node _T_1632 = asUInt(reset) node _T_1633 = eq(_T_1632, UInt<1>(0h0)) when _T_1633 : node _T_1634 = eq(_T_1631, UInt<1>(0h0)) when _T_1634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1631, UInt<1>(0h1), "") : assert_117 node _T_1635 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1635 : node _T_1636 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1637 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1638 = and(_T_1636, _T_1637) node _T_1639 = or(UInt<1>(0h0), _T_1638) node _T_1640 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<14>(0h2000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<13>(0h1000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<18>(0h2f000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<13>(0h1000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<17>(0h10000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<27>(0h4000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<13>(0h1000))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1686 = cvt(_T_1685) node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h10000000))) node _T_1688 = asSInt(_T_1687) node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0))) node _T_1690 = or(_T_1644, _T_1649) node _T_1691 = or(_T_1690, _T_1654) node _T_1692 = or(_T_1691, _T_1659) node _T_1693 = or(_T_1692, _T_1664) node _T_1694 = or(_T_1693, _T_1669) node _T_1695 = or(_T_1694, _T_1674) node _T_1696 = or(_T_1695, _T_1679) node _T_1697 = or(_T_1696, _T_1684) node _T_1698 = or(_T_1697, _T_1689) node _T_1699 = and(_T_1639, _T_1698) node _T_1700 = or(UInt<1>(0h0), _T_1699) node _T_1701 = and(UInt<1>(0h0), _T_1700) node _T_1702 = asUInt(reset) node _T_1703 = eq(_T_1702, UInt<1>(0h0)) when _T_1703 : node _T_1704 = eq(_T_1701, UInt<1>(0h0)) when _T_1704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1701, UInt<1>(0h1), "") : assert_118 node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(address_ok, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(legal_source, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1711 = asUInt(reset) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) when _T_1712 : node _T_1713 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1714 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_122 node _T_1718 = eq(io.in.b.bits.mask, mask_1) node _T_1719 = asUInt(reset) node _T_1720 = eq(_T_1719, UInt<1>(0h0)) when _T_1720 : node _T_1721 = eq(_T_1718, UInt<1>(0h0)) when _T_1721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1718, UInt<1>(0h1), "") : assert_123 node _T_1722 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1722 : node _T_1723 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1724 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1725 = and(_T_1723, _T_1724) node _T_1726 = or(UInt<1>(0h0), _T_1725) node _T_1727 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<14>(0h2000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<13>(0h1000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<18>(0h2f000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<13>(0h1000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<17>(0h10000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<27>(0h4000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1768 = cvt(_T_1767) node _T_1769 = and(_T_1768, asSInt(UInt<13>(0h1000))) node _T_1770 = asSInt(_T_1769) node _T_1771 = eq(_T_1770, asSInt(UInt<1>(0h0))) node _T_1772 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1773 = cvt(_T_1772) node _T_1774 = and(_T_1773, asSInt(UInt<29>(0h10000000))) node _T_1775 = asSInt(_T_1774) node _T_1776 = eq(_T_1775, asSInt(UInt<1>(0h0))) node _T_1777 = or(_T_1731, _T_1736) node _T_1778 = or(_T_1777, _T_1741) node _T_1779 = or(_T_1778, _T_1746) node _T_1780 = or(_T_1779, _T_1751) node _T_1781 = or(_T_1780, _T_1756) node _T_1782 = or(_T_1781, _T_1761) node _T_1783 = or(_T_1782, _T_1766) node _T_1784 = or(_T_1783, _T_1771) node _T_1785 = or(_T_1784, _T_1776) node _T_1786 = and(_T_1726, _T_1785) node _T_1787 = or(UInt<1>(0h0), _T_1786) node _T_1788 = and(UInt<1>(0h0), _T_1787) node _T_1789 = asUInt(reset) node _T_1790 = eq(_T_1789, UInt<1>(0h0)) when _T_1790 : node _T_1791 = eq(_T_1788, UInt<1>(0h0)) when _T_1791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1788, UInt<1>(0h1), "") : assert_124 node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(address_ok, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(legal_source, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1798 = asUInt(reset) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) when _T_1799 : node _T_1800 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1801 = eq(io.in.b.bits.mask, mask_1) node _T_1802 = asUInt(reset) node _T_1803 = eq(_T_1802, UInt<1>(0h0)) when _T_1803 : node _T_1804 = eq(_T_1801, UInt<1>(0h0)) when _T_1804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1801, UInt<1>(0h1), "") : assert_128 node _T_1805 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(_T_1805, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1805, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1809 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_106 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_107 = cvt(_address_ok_T_106) node _address_ok_T_108 = and(_address_ok_T_107, asSInt(UInt<13>(0h1000))) node _address_ok_T_109 = asSInt(_address_ok_T_108) node _address_ok_T_110 = eq(_address_ok_T_109, asSInt(UInt<1>(0h0))) node _address_ok_T_111 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_112 = cvt(_address_ok_T_111) node _address_ok_T_113 = and(_address_ok_T_112, asSInt(UInt<13>(0h1000))) node _address_ok_T_114 = asSInt(_address_ok_T_113) node _address_ok_T_115 = eq(_address_ok_T_114, asSInt(UInt<1>(0h0))) node _address_ok_T_116 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_117 = cvt(_address_ok_T_116) node _address_ok_T_118 = and(_address_ok_T_117, asSInt(UInt<13>(0h1000))) node _address_ok_T_119 = asSInt(_address_ok_T_118) node _address_ok_T_120 = eq(_address_ok_T_119, asSInt(UInt<1>(0h0))) node _address_ok_T_121 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_122 = cvt(_address_ok_T_121) node _address_ok_T_123 = and(_address_ok_T_122, asSInt(UInt<17>(0h10000))) node _address_ok_T_124 = asSInt(_address_ok_T_123) node _address_ok_T_125 = eq(_address_ok_T_124, asSInt(UInt<1>(0h0))) node _address_ok_T_126 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_127 = cvt(_address_ok_T_126) node _address_ok_T_128 = and(_address_ok_T_127, asSInt(UInt<13>(0h1000))) node _address_ok_T_129 = asSInt(_address_ok_T_128) node _address_ok_T_130 = eq(_address_ok_T_129, asSInt(UInt<1>(0h0))) node _address_ok_T_131 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_132 = cvt(_address_ok_T_131) node _address_ok_T_133 = and(_address_ok_T_132, asSInt(UInt<13>(0h1000))) node _address_ok_T_134 = asSInt(_address_ok_T_133) node _address_ok_T_135 = eq(_address_ok_T_134, asSInt(UInt<1>(0h0))) node _address_ok_T_136 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_137 = cvt(_address_ok_T_136) node _address_ok_T_138 = and(_address_ok_T_137, asSInt(UInt<17>(0h10000))) node _address_ok_T_139 = asSInt(_address_ok_T_138) node _address_ok_T_140 = eq(_address_ok_T_139, asSInt(UInt<1>(0h0))) node _address_ok_T_141 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_142 = cvt(_address_ok_T_141) node _address_ok_T_143 = and(_address_ok_T_142, asSInt(UInt<13>(0h1000))) node _address_ok_T_144 = asSInt(_address_ok_T_143) node _address_ok_T_145 = eq(_address_ok_T_144, asSInt(UInt<1>(0h0))) node _address_ok_T_146 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_147 = cvt(_address_ok_T_146) node _address_ok_T_148 = and(_address_ok_T_147, asSInt(UInt<17>(0h100c0))) node _address_ok_T_149 = asSInt(_address_ok_T_148) node _address_ok_T_150 = eq(_address_ok_T_149, asSInt(UInt<1>(0h0))) node _address_ok_T_151 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _address_ok_T_152 = cvt(_address_ok_T_151) node _address_ok_T_153 = and(_address_ok_T_152, asSInt(UInt<17>(0h100c0))) node _address_ok_T_154 = asSInt(_address_ok_T_153) node _address_ok_T_155 = eq(_address_ok_T_154, asSInt(UInt<1>(0h0))) node _address_ok_T_156 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _address_ok_T_157 = cvt(_address_ok_T_156) node _address_ok_T_158 = and(_address_ok_T_157, asSInt(UInt<17>(0h100c0))) node _address_ok_T_159 = asSInt(_address_ok_T_158) node _address_ok_T_160 = eq(_address_ok_T_159, asSInt(UInt<1>(0h0))) node _address_ok_T_161 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_162 = cvt(_address_ok_T_161) node _address_ok_T_163 = and(_address_ok_T_162, asSInt(UInt<17>(0h100c0))) node _address_ok_T_164 = asSInt(_address_ok_T_163) node _address_ok_T_165 = eq(_address_ok_T_164, asSInt(UInt<1>(0h0))) node _address_ok_T_166 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_167 = cvt(_address_ok_T_166) node _address_ok_T_168 = and(_address_ok_T_167, asSInt(UInt<27>(0h4000000))) node _address_ok_T_169 = asSInt(_address_ok_T_168) node _address_ok_T_170 = eq(_address_ok_T_169, asSInt(UInt<1>(0h0))) node _address_ok_T_171 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_172 = cvt(_address_ok_T_171) node _address_ok_T_173 = and(_address_ok_T_172, asSInt(UInt<13>(0h1000))) node _address_ok_T_174 = asSInt(_address_ok_T_173) node _address_ok_T_175 = eq(_address_ok_T_174, asSInt(UInt<1>(0h0))) node _address_ok_T_176 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_177 = cvt(_address_ok_T_176) node _address_ok_T_178 = and(_address_ok_T_177, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_179 = asSInt(_address_ok_T_178) node _address_ok_T_180 = eq(_address_ok_T_179, asSInt(UInt<1>(0h0))) node _address_ok_T_181 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _address_ok_T_182 = cvt(_address_ok_T_181) node _address_ok_T_183 = and(_address_ok_T_182, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_184 = asSInt(_address_ok_T_183) node _address_ok_T_185 = eq(_address_ok_T_184, asSInt(UInt<1>(0h0))) node _address_ok_T_186 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _address_ok_T_187 = cvt(_address_ok_T_186) node _address_ok_T_188 = and(_address_ok_T_187, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_189 = asSInt(_address_ok_T_188) node _address_ok_T_190 = eq(_address_ok_T_189, asSInt(UInt<1>(0h0))) node _address_ok_T_191 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_192 = cvt(_address_ok_T_191) node _address_ok_T_193 = and(_address_ok_T_192, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_194 = asSInt(_address_ok_T_193) node _address_ok_T_195 = eq(_address_ok_T_194, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[18] connect _address_ok_WIRE_1[0], _address_ok_T_110 connect _address_ok_WIRE_1[1], _address_ok_T_115 connect _address_ok_WIRE_1[2], _address_ok_T_120 connect _address_ok_WIRE_1[3], _address_ok_T_125 connect _address_ok_WIRE_1[4], _address_ok_T_130 connect _address_ok_WIRE_1[5], _address_ok_T_135 connect _address_ok_WIRE_1[6], _address_ok_T_140 connect _address_ok_WIRE_1[7], _address_ok_T_145 connect _address_ok_WIRE_1[8], _address_ok_T_150 connect _address_ok_WIRE_1[9], _address_ok_T_155 connect _address_ok_WIRE_1[10], _address_ok_T_160 connect _address_ok_WIRE_1[11], _address_ok_T_165 connect _address_ok_WIRE_1[12], _address_ok_T_170 connect _address_ok_WIRE_1[13], _address_ok_T_175 connect _address_ok_WIRE_1[14], _address_ok_T_180 connect _address_ok_WIRE_1[15], _address_ok_T_185 connect _address_ok_WIRE_1[16], _address_ok_T_190 connect _address_ok_WIRE_1[17], _address_ok_T_195 node _address_ok_T_196 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[2]) node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[3]) node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[4]) node _address_ok_T_200 = or(_address_ok_T_199, _address_ok_WIRE_1[5]) node _address_ok_T_201 = or(_address_ok_T_200, _address_ok_WIRE_1[6]) node _address_ok_T_202 = or(_address_ok_T_201, _address_ok_WIRE_1[7]) node _address_ok_T_203 = or(_address_ok_T_202, _address_ok_WIRE_1[8]) node _address_ok_T_204 = or(_address_ok_T_203, _address_ok_WIRE_1[9]) node _address_ok_T_205 = or(_address_ok_T_204, _address_ok_WIRE_1[10]) node _address_ok_T_206 = or(_address_ok_T_205, _address_ok_WIRE_1[11]) node _address_ok_T_207 = or(_address_ok_T_206, _address_ok_WIRE_1[12]) node _address_ok_T_208 = or(_address_ok_T_207, _address_ok_WIRE_1[13]) node _address_ok_T_209 = or(_address_ok_T_208, _address_ok_WIRE_1[14]) node _address_ok_T_210 = or(_address_ok_T_209, _address_ok_WIRE_1[15]) node _address_ok_T_211 = or(_address_ok_T_210, _address_ok_WIRE_1[16]) node address_ok_1 = or(_address_ok_T_211, _address_ok_WIRE_1[17]) node _T_1813 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) node _T_1815 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1816 = cvt(_T_1815) node _T_1817 = and(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = asSInt(_T_1817) node _T_1819 = eq(_T_1818, asSInt(UInt<1>(0h0))) node _T_1820 = or(_T_1814, _T_1819) node _T_1821 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1822 = eq(_T_1821, UInt<1>(0h0)) node _T_1823 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1824 = cvt(_T_1823) node _T_1825 = and(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = asSInt(_T_1825) node _T_1827 = eq(_T_1826, asSInt(UInt<1>(0h0))) node _T_1828 = or(_T_1822, _T_1827) node _T_1829 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) node _T_1831 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1832 = cvt(_T_1831) node _T_1833 = and(_T_1832, asSInt(UInt<1>(0h0))) node _T_1834 = asSInt(_T_1833) node _T_1835 = eq(_T_1834, asSInt(UInt<1>(0h0))) node _T_1836 = or(_T_1830, _T_1835) node _T_1837 = and(_T_1820, _T_1828) node _T_1838 = and(_T_1837, _T_1836) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_131 node _T_1842 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1842 : node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(address_ok_1, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1846 = asUInt(reset) node _T_1847 = eq(_T_1846, UInt<1>(0h0)) when _T_1847 : node _T_1848 = eq(source_ok_2, UInt<1>(0h0)) when _T_1848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1849 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(_T_1849, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1849, UInt<1>(0h1), "") : assert_134 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1856 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(_T_1856, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1856, UInt<1>(0h1), "") : assert_136 node _T_1860 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_137 node _T_1864 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1864 : node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(address_ok_1, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(source_ok_2, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1871 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(_T_1871, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1871, UInt<1>(0h1), "") : assert_140 node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1878 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1879 = asUInt(reset) node _T_1880 = eq(_T_1879, UInt<1>(0h0)) when _T_1880 : node _T_1881 = eq(_T_1878, UInt<1>(0h0)) when _T_1881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1878, UInt<1>(0h1), "") : assert_142 node _T_1882 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1882 : node _T_1883 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1884 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1885 = and(_T_1883, _T_1884) node _T_1886 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1887 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1888 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1889 = or(_T_1886, _T_1887) node _T_1890 = or(_T_1889, _T_1888) node _T_1891 = and(_T_1885, _T_1890) node _T_1892 = or(UInt<1>(0h0), _T_1891) node _T_1893 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1894 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<14>(0h2000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<13>(0h1000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<18>(0h2f000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<17>(0h10000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1925 = cvt(_T_1924) node _T_1926 = and(_T_1925, asSInt(UInt<27>(0h4000000))) node _T_1927 = asSInt(_T_1926) node _T_1928 = eq(_T_1927, asSInt(UInt<1>(0h0))) node _T_1929 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1930 = cvt(_T_1929) node _T_1931 = and(_T_1930, asSInt(UInt<13>(0h1000))) node _T_1932 = asSInt(_T_1931) node _T_1933 = eq(_T_1932, asSInt(UInt<1>(0h0))) node _T_1934 = or(_T_1898, _T_1903) node _T_1935 = or(_T_1934, _T_1908) node _T_1936 = or(_T_1935, _T_1913) node _T_1937 = or(_T_1936, _T_1918) node _T_1938 = or(_T_1937, _T_1923) node _T_1939 = or(_T_1938, _T_1928) node _T_1940 = or(_T_1939, _T_1933) node _T_1941 = and(_T_1893, _T_1940) node _T_1942 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1943 = or(UInt<1>(0h0), _T_1942) node _T_1944 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1945 = cvt(_T_1944) node _T_1946 = and(_T_1945, asSInt(UInt<17>(0h10000))) node _T_1947 = asSInt(_T_1946) node _T_1948 = eq(_T_1947, asSInt(UInt<1>(0h0))) node _T_1949 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1950 = cvt(_T_1949) node _T_1951 = and(_T_1950, asSInt(UInt<29>(0h10000000))) node _T_1952 = asSInt(_T_1951) node _T_1953 = eq(_T_1952, asSInt(UInt<1>(0h0))) node _T_1954 = or(_T_1948, _T_1953) node _T_1955 = and(_T_1943, _T_1954) node _T_1956 = or(UInt<1>(0h0), _T_1941) node _T_1957 = or(_T_1956, _T_1955) node _T_1958 = and(_T_1892, _T_1957) node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(_T_1958, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1958, UInt<1>(0h1), "") : assert_143 node _T_1962 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1963 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1964 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1962 connect _WIRE_6[1], _T_1963 connect _WIRE_6[2], _T_1964 node _T_1965 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1966 = mux(_WIRE_6[0], _T_1965, UInt<1>(0h0)) node _T_1967 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1968 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1969 = or(_T_1966, _T_1967) node _T_1970 = or(_T_1969, _T_1968) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1970 node _T_1971 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1972 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1973 = and(_T_1971, _T_1972) node _T_1974 = or(UInt<1>(0h0), _T_1973) node _T_1975 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<14>(0h2000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<13>(0h1000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<18>(0h2f000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<13>(0h1000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<17>(0h10000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<27>(0h4000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2016 = cvt(_T_2015) node _T_2017 = and(_T_2016, asSInt(UInt<13>(0h1000))) node _T_2018 = asSInt(_T_2017) node _T_2019 = eq(_T_2018, asSInt(UInt<1>(0h0))) node _T_2020 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2021 = cvt(_T_2020) node _T_2022 = and(_T_2021, asSInt(UInt<29>(0h10000000))) node _T_2023 = asSInt(_T_2022) node _T_2024 = eq(_T_2023, asSInt(UInt<1>(0h0))) node _T_2025 = or(_T_1979, _T_1984) node _T_2026 = or(_T_2025, _T_1989) node _T_2027 = or(_T_2026, _T_1994) node _T_2028 = or(_T_2027, _T_1999) node _T_2029 = or(_T_2028, _T_2004) node _T_2030 = or(_T_2029, _T_2009) node _T_2031 = or(_T_2030, _T_2014) node _T_2032 = or(_T_2031, _T_2019) node _T_2033 = or(_T_2032, _T_2024) node _T_2034 = and(_T_1974, _T_2033) node _T_2035 = or(UInt<1>(0h0), _T_2034) node _T_2036 = and(_WIRE_7, _T_2035) node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(_T_2036, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2036, UInt<1>(0h1), "") : assert_144 node _T_2040 = asUInt(reset) node _T_2041 = eq(_T_2040, UInt<1>(0h0)) when _T_2041 : node _T_2042 = eq(source_ok_2, UInt<1>(0h0)) when _T_2042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2043 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(_T_2043, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2043, UInt<1>(0h1), "") : assert_146 node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2050 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_148 node _T_2054 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_149 node _T_2058 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2058 : node _T_2059 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2060 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2061 = and(_T_2059, _T_2060) node _T_2062 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2063 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2064 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2065 = or(_T_2062, _T_2063) node _T_2066 = or(_T_2065, _T_2064) node _T_2067 = and(_T_2061, _T_2066) node _T_2068 = or(UInt<1>(0h0), _T_2067) node _T_2069 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2070 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<14>(0h2000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<13>(0h1000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<18>(0h2f000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<17>(0h10000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2101 = cvt(_T_2100) node _T_2102 = and(_T_2101, asSInt(UInt<27>(0h4000000))) node _T_2103 = asSInt(_T_2102) node _T_2104 = eq(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2106 = cvt(_T_2105) node _T_2107 = and(_T_2106, asSInt(UInt<13>(0h1000))) node _T_2108 = asSInt(_T_2107) node _T_2109 = eq(_T_2108, asSInt(UInt<1>(0h0))) node _T_2110 = or(_T_2074, _T_2079) node _T_2111 = or(_T_2110, _T_2084) node _T_2112 = or(_T_2111, _T_2089) node _T_2113 = or(_T_2112, _T_2094) node _T_2114 = or(_T_2113, _T_2099) node _T_2115 = or(_T_2114, _T_2104) node _T_2116 = or(_T_2115, _T_2109) node _T_2117 = and(_T_2069, _T_2116) node _T_2118 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2119 = or(UInt<1>(0h0), _T_2118) node _T_2120 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2121 = cvt(_T_2120) node _T_2122 = and(_T_2121, asSInt(UInt<17>(0h10000))) node _T_2123 = asSInt(_T_2122) node _T_2124 = eq(_T_2123, asSInt(UInt<1>(0h0))) node _T_2125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2126 = cvt(_T_2125) node _T_2127 = and(_T_2126, asSInt(UInt<29>(0h10000000))) node _T_2128 = asSInt(_T_2127) node _T_2129 = eq(_T_2128, asSInt(UInt<1>(0h0))) node _T_2130 = or(_T_2124, _T_2129) node _T_2131 = and(_T_2119, _T_2130) node _T_2132 = or(UInt<1>(0h0), _T_2117) node _T_2133 = or(_T_2132, _T_2131) node _T_2134 = and(_T_2068, _T_2133) node _T_2135 = asUInt(reset) node _T_2136 = eq(_T_2135, UInt<1>(0h0)) when _T_2136 : node _T_2137 = eq(_T_2134, UInt<1>(0h0)) when _T_2137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2134, UInt<1>(0h1), "") : assert_150 node _T_2138 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2139 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2140 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2138 connect _WIRE_8[1], _T_2139 connect _WIRE_8[2], _T_2140 node _T_2141 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2142 = mux(_WIRE_8[0], _T_2141, UInt<1>(0h0)) node _T_2143 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2144 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2145 = or(_T_2142, _T_2143) node _T_2146 = or(_T_2145, _T_2144) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2146 node _T_2147 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2148 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2149 = and(_T_2147, _T_2148) node _T_2150 = or(UInt<1>(0h0), _T_2149) node _T_2151 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<14>(0h2000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<13>(0h1000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<18>(0h2f000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<13>(0h1000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<17>(0h10000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<27>(0h4000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2192 = cvt(_T_2191) node _T_2193 = and(_T_2192, asSInt(UInt<13>(0h1000))) node _T_2194 = asSInt(_T_2193) node _T_2195 = eq(_T_2194, asSInt(UInt<1>(0h0))) node _T_2196 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2197 = cvt(_T_2196) node _T_2198 = and(_T_2197, asSInt(UInt<29>(0h10000000))) node _T_2199 = asSInt(_T_2198) node _T_2200 = eq(_T_2199, asSInt(UInt<1>(0h0))) node _T_2201 = or(_T_2155, _T_2160) node _T_2202 = or(_T_2201, _T_2165) node _T_2203 = or(_T_2202, _T_2170) node _T_2204 = or(_T_2203, _T_2175) node _T_2205 = or(_T_2204, _T_2180) node _T_2206 = or(_T_2205, _T_2185) node _T_2207 = or(_T_2206, _T_2190) node _T_2208 = or(_T_2207, _T_2195) node _T_2209 = or(_T_2208, _T_2200) node _T_2210 = and(_T_2150, _T_2209) node _T_2211 = or(UInt<1>(0h0), _T_2210) node _T_2212 = and(_WIRE_9, _T_2211) node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(_T_2212, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2212, UInt<1>(0h1), "") : assert_151 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(source_ok_2, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2219 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_153 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2226 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_155 node _T_2230 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2230 : node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(address_ok_1, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(source_ok_2, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2237 = asUInt(reset) node _T_2238 = eq(_T_2237, UInt<1>(0h0)) when _T_2238 : node _T_2239 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2240 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(_T_2240, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2240, UInt<1>(0h1), "") : assert_159 node _T_2244 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(_T_2244, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2244, UInt<1>(0h1), "") : assert_160 node _T_2248 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2248 : node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(address_ok_1, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(source_ok_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2255 = asUInt(reset) node _T_2256 = eq(_T_2255, UInt<1>(0h0)) when _T_2256 : node _T_2257 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2258 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(_T_2258, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2258, UInt<1>(0h1), "") : assert_164 node _T_2262 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2262 : node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(address_ok_1, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2266 = asUInt(reset) node _T_2267 = eq(_T_2266, UInt<1>(0h0)) when _T_2267 : node _T_2268 = eq(source_ok_2, UInt<1>(0h0)) when _T_2268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2269 = asUInt(reset) node _T_2270 = eq(_T_2269, UInt<1>(0h0)) when _T_2270 : node _T_2271 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2272 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2273 = asUInt(reset) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(_T_2272, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2272, UInt<1>(0h1), "") : assert_168 node _T_2276 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<7>(0h40)) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2283 = eq(a_first, UInt<1>(0h0)) node _T_2284 = and(io.in.a.valid, _T_2283) when _T_2284 : node _T_2285 = eq(io.in.a.bits.opcode, opcode) node _T_2286 = asUInt(reset) node _T_2287 = eq(_T_2286, UInt<1>(0h0)) when _T_2287 : node _T_2288 = eq(_T_2285, UInt<1>(0h0)) when _T_2288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2285, UInt<1>(0h1), "") : assert_171 node _T_2289 = eq(io.in.a.bits.param, param) node _T_2290 = asUInt(reset) node _T_2291 = eq(_T_2290, UInt<1>(0h0)) when _T_2291 : node _T_2292 = eq(_T_2289, UInt<1>(0h0)) when _T_2292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2289, UInt<1>(0h1), "") : assert_172 node _T_2293 = eq(io.in.a.bits.size, size) node _T_2294 = asUInt(reset) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) when _T_2295 : node _T_2296 = eq(_T_2293, UInt<1>(0h0)) when _T_2296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2293, UInt<1>(0h1), "") : assert_173 node _T_2297 = eq(io.in.a.bits.source, source) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(_T_2297, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2297, UInt<1>(0h1), "") : assert_174 node _T_2301 = eq(io.in.a.bits.address, address) node _T_2302 = asUInt(reset) node _T_2303 = eq(_T_2302, UInt<1>(0h0)) when _T_2303 : node _T_2304 = eq(_T_2301, UInt<1>(0h0)) when _T_2304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2301, UInt<1>(0h1), "") : assert_175 node _T_2305 = and(io.in.a.ready, io.in.a.valid) node _T_2306 = and(_T_2305, a_first) when _T_2306 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2307 = eq(d_first, UInt<1>(0h0)) node _T_2308 = and(io.in.d.valid, _T_2307) when _T_2308 : node _T_2309 = eq(io.in.d.bits.opcode, opcode_1) node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(_T_2309, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2309, UInt<1>(0h1), "") : assert_176 node _T_2313 = eq(io.in.d.bits.param, param_1) node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : node _T_2316 = eq(_T_2313, UInt<1>(0h0)) when _T_2316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2313, UInt<1>(0h1), "") : assert_177 node _T_2317 = eq(io.in.d.bits.size, size_1) node _T_2318 = asUInt(reset) node _T_2319 = eq(_T_2318, UInt<1>(0h0)) when _T_2319 : node _T_2320 = eq(_T_2317, UInt<1>(0h0)) when _T_2320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2317, UInt<1>(0h1), "") : assert_178 node _T_2321 = eq(io.in.d.bits.source, source_1) node _T_2322 = asUInt(reset) node _T_2323 = eq(_T_2322, UInt<1>(0h0)) when _T_2323 : node _T_2324 = eq(_T_2321, UInt<1>(0h0)) when _T_2324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2321, UInt<1>(0h1), "") : assert_179 node _T_2325 = eq(io.in.d.bits.sink, sink) node _T_2326 = asUInt(reset) node _T_2327 = eq(_T_2326, UInt<1>(0h0)) when _T_2327 : node _T_2328 = eq(_T_2325, UInt<1>(0h0)) when _T_2328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2325, UInt<1>(0h1), "") : assert_180 node _T_2329 = eq(io.in.d.bits.denied, denied) node _T_2330 = asUInt(reset) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) when _T_2331 : node _T_2332 = eq(_T_2329, UInt<1>(0h0)) when _T_2332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2329, UInt<1>(0h1), "") : assert_181 node _T_2333 = and(io.in.d.ready, io.in.d.valid) node _T_2334 = and(_T_2333, d_first) when _T_2334 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2335 = eq(b_first, UInt<1>(0h0)) node _T_2336 = and(io.in.b.valid, _T_2335) when _T_2336 : node _T_2337 = eq(io.in.b.bits.opcode, opcode_2) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_182 node _T_2341 = eq(io.in.b.bits.param, param_2) node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(_T_2341, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2341, UInt<1>(0h1), "") : assert_183 node _T_2345 = eq(io.in.b.bits.size, size_2) node _T_2346 = asUInt(reset) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) when _T_2347 : node _T_2348 = eq(_T_2345, UInt<1>(0h0)) when _T_2348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2345, UInt<1>(0h1), "") : assert_184 node _T_2349 = eq(io.in.b.bits.source, source_2) node _T_2350 = asUInt(reset) node _T_2351 = eq(_T_2350, UInt<1>(0h0)) when _T_2351 : node _T_2352 = eq(_T_2349, UInt<1>(0h0)) when _T_2352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2349, UInt<1>(0h1), "") : assert_185 node _T_2353 = eq(io.in.b.bits.address, address_1) node _T_2354 = asUInt(reset) node _T_2355 = eq(_T_2354, UInt<1>(0h0)) when _T_2355 : node _T_2356 = eq(_T_2353, UInt<1>(0h0)) when _T_2356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2353, UInt<1>(0h1), "") : assert_186 node _T_2357 = and(io.in.b.ready, io.in.b.valid) node _T_2358 = and(_T_2357, b_first) when _T_2358 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2359 = eq(c_first, UInt<1>(0h0)) node _T_2360 = and(io.in.c.valid, _T_2359) when _T_2360 : node _T_2361 = eq(io.in.c.bits.opcode, opcode_3) node _T_2362 = asUInt(reset) node _T_2363 = eq(_T_2362, UInt<1>(0h0)) when _T_2363 : node _T_2364 = eq(_T_2361, UInt<1>(0h0)) when _T_2364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2361, UInt<1>(0h1), "") : assert_187 node _T_2365 = eq(io.in.c.bits.param, param_3) node _T_2366 = asUInt(reset) node _T_2367 = eq(_T_2366, UInt<1>(0h0)) when _T_2367 : node _T_2368 = eq(_T_2365, UInt<1>(0h0)) when _T_2368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2365, UInt<1>(0h1), "") : assert_188 node _T_2369 = eq(io.in.c.bits.size, size_3) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_189 node _T_2373 = eq(io.in.c.bits.source, source_3) node _T_2374 = asUInt(reset) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) when _T_2375 : node _T_2376 = eq(_T_2373, UInt<1>(0h0)) when _T_2376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2373, UInt<1>(0h1), "") : assert_190 node _T_2377 = eq(io.in.c.bits.address, address_2) node _T_2378 = asUInt(reset) node _T_2379 = eq(_T_2378, UInt<1>(0h0)) when _T_2379 : node _T_2380 = eq(_T_2377, UInt<1>(0h0)) when _T_2380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2377, UInt<1>(0h1), "") : assert_191 node _T_2381 = and(io.in.c.ready, io.in.c.valid) node _T_2382 = and(_T_2381, c_first) when _T_2382 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2383 = and(io.in.a.valid, a_first_1) node _T_2384 = and(_T_2383, UInt<1>(0h1)) when _T_2384 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2385 = and(io.in.a.ready, io.in.a.valid) node _T_2386 = and(_T_2385, a_first_1) node _T_2387 = and(_T_2386, UInt<1>(0h1)) when _T_2387 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2388 = dshr(inflight, io.in.a.bits.source) node _T_2389 = bits(_T_2388, 0, 0) node _T_2390 = eq(_T_2389, UInt<1>(0h0)) node _T_2391 = asUInt(reset) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) when _T_2392 : node _T_2393 = eq(_T_2390, UInt<1>(0h0)) when _T_2393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2390, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2394 = and(io.in.d.valid, d_first_1) node _T_2395 = and(_T_2394, UInt<1>(0h1)) node _T_2396 = eq(d_release_ack, UInt<1>(0h0)) node _T_2397 = and(_T_2395, _T_2396) when _T_2397 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2398 = and(io.in.d.ready, io.in.d.valid) node _T_2399 = and(_T_2398, d_first_1) node _T_2400 = and(_T_2399, UInt<1>(0h1)) node _T_2401 = eq(d_release_ack, UInt<1>(0h0)) node _T_2402 = and(_T_2400, _T_2401) when _T_2402 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2403 = and(io.in.d.valid, d_first_1) node _T_2404 = and(_T_2403, UInt<1>(0h1)) node _T_2405 = eq(d_release_ack, UInt<1>(0h0)) node _T_2406 = and(_T_2404, _T_2405) when _T_2406 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2407 = dshr(inflight, io.in.d.bits.source) node _T_2408 = bits(_T_2407, 0, 0) node _T_2409 = or(_T_2408, same_cycle_resp) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_194 node _T_2419 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_195 else : node _T_2423 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2424 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2425 = or(_T_2423, _T_2424) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_196 node _T_2429 = eq(io.in.d.bits.size, a_size_lookup) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_197 node _T_2433 = and(io.in.d.valid, d_first_1) node _T_2434 = and(_T_2433, a_first_1) node _T_2435 = and(_T_2434, io.in.a.valid) node _T_2436 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = eq(d_release_ack, UInt<1>(0h0)) node _T_2439 = and(_T_2437, _T_2438) when _T_2439 : node _T_2440 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2441 = or(_T_2440, io.in.a.ready) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_198 node _T_2445 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2446 = orr(a_set_wo_ready) node _T_2447 = eq(_T_2446, UInt<1>(0h0)) node _T_2448 = or(_T_2445, _T_2447) node _T_2449 = asUInt(reset) node _T_2450 = eq(_T_2449, UInt<1>(0h0)) when _T_2450 : node _T_2451 = eq(_T_2448, UInt<1>(0h0)) when _T_2451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2448, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_169 node _T_2452 = orr(inflight) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) node _T_2454 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2455 = or(_T_2453, _T_2454) node _T_2456 = lt(watchdog, plusarg_reader.out) node _T_2457 = or(_T_2455, _T_2456) node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(_T_2457, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2457, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2461 = and(io.in.a.ready, io.in.a.valid) node _T_2462 = and(io.in.d.ready, io.in.d.valid) node _T_2463 = or(_T_2461, _T_2462) when _T_2463 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2464 = and(io.in.c.valid, c_first_1) node _T_2465 = bits(io.in.c.bits.opcode, 2, 2) node _T_2466 = bits(io.in.c.bits.opcode, 1, 1) node _T_2467 = and(_T_2465, _T_2466) node _T_2468 = and(_T_2464, _T_2467) when _T_2468 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2469 = and(io.in.c.ready, io.in.c.valid) node _T_2470 = and(_T_2469, c_first_1) node _T_2471 = bits(io.in.c.bits.opcode, 2, 2) node _T_2472 = bits(io.in.c.bits.opcode, 1, 1) node _T_2473 = and(_T_2471, _T_2472) node _T_2474 = and(_T_2470, _T_2473) when _T_2474 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2475 = dshr(inflight_1, io.in.c.bits.source) node _T_2476 = bits(_T_2475, 0, 0) node _T_2477 = eq(_T_2476, UInt<1>(0h0)) node _T_2478 = asUInt(reset) node _T_2479 = eq(_T_2478, UInt<1>(0h0)) when _T_2479 : node _T_2480 = eq(_T_2477, UInt<1>(0h0)) when _T_2480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2477, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2481 = and(io.in.d.valid, d_first_2) node _T_2482 = and(_T_2481, UInt<1>(0h1)) node _T_2483 = and(_T_2482, d_release_ack_1) when _T_2483 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2484 = and(io.in.d.ready, io.in.d.valid) node _T_2485 = and(_T_2484, d_first_2) node _T_2486 = and(_T_2485, UInt<1>(0h1)) node _T_2487 = and(_T_2486, d_release_ack_1) when _T_2487 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2488 = and(io.in.d.valid, d_first_2) node _T_2489 = and(_T_2488, UInt<1>(0h1)) node _T_2490 = and(_T_2489, d_release_ack_1) when _T_2490 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2491 = dshr(inflight_1, io.in.d.bits.source) node _T_2492 = bits(_T_2491, 0, 0) node _T_2493 = or(_T_2492, same_cycle_resp_1) node _T_2494 = asUInt(reset) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) when _T_2495 : node _T_2496 = eq(_T_2493, UInt<1>(0h0)) when _T_2496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2493, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2497 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2498 = asUInt(reset) node _T_2499 = eq(_T_2498, UInt<1>(0h0)) when _T_2499 : node _T_2500 = eq(_T_2497, UInt<1>(0h0)) when _T_2500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2497, UInt<1>(0h1), "") : assert_203 else : node _T_2501 = eq(io.in.d.bits.size, c_size_lookup) node _T_2502 = asUInt(reset) node _T_2503 = eq(_T_2502, UInt<1>(0h0)) when _T_2503 : node _T_2504 = eq(_T_2501, UInt<1>(0h0)) when _T_2504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2501, UInt<1>(0h1), "") : assert_204 node _T_2505 = and(io.in.d.valid, d_first_2) node _T_2506 = and(_T_2505, c_first_1) node _T_2507 = and(_T_2506, io.in.c.valid) node _T_2508 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2509 = and(_T_2507, _T_2508) node _T_2510 = and(_T_2509, d_release_ack_1) node _T_2511 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2512 = and(_T_2510, _T_2511) when _T_2512 : node _T_2513 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2514 = or(_T_2513, io.in.c.ready) node _T_2515 = asUInt(reset) node _T_2516 = eq(_T_2515, UInt<1>(0h0)) when _T_2516 : node _T_2517 = eq(_T_2514, UInt<1>(0h0)) when _T_2517 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2514, UInt<1>(0h1), "") : assert_205 node _T_2518 = orr(c_set_wo_ready) when _T_2518 : node _T_2519 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_170 node _T_2523 = orr(inflight_1) node _T_2524 = eq(_T_2523, UInt<1>(0h0)) node _T_2525 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2526 = or(_T_2524, _T_2525) node _T_2527 = lt(watchdog_1, plusarg_reader_1.out) node _T_2528 = or(_T_2526, _T_2527) node _T_2529 = asUInt(reset) node _T_2530 = eq(_T_2529, UInt<1>(0h0)) when _T_2530 : node _T_2531 = eq(_T_2528, UInt<1>(0h0)) when _T_2531 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2528, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2532 = and(io.in.c.ready, io.in.c.valid) node _T_2533 = and(io.in.d.ready, io.in.d.valid) node _T_2534 = or(_T_2532, _T_2533) when _T_2534 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<64> connect d_set, UInt<64>(0h0) node _T_2535 = and(io.in.d.ready, io.in.d.valid) node _T_2536 = and(_T_2535, d_first_3) node _T_2537 = bits(io.in.d.bits.opcode, 2, 2) node _T_2538 = bits(io.in.d.bits.opcode, 1, 1) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) node _T_2540 = and(_T_2537, _T_2539) node _T_2541 = and(_T_2536, _T_2540) when _T_2541 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2542 = dshr(inflight_2, io.in.d.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = eq(_T_2543, UInt<1>(0h0)) node _T_2545 = asUInt(reset) node _T_2546 = eq(_T_2545, UInt<1>(0h0)) when _T_2546 : node _T_2547 = eq(_T_2544, UInt<1>(0h0)) when _T_2547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2544, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<64> connect e_clr, UInt<64>(0h0) node _T_2548 = and(io.in.e.ready, io.in.e.valid) node _T_2549 = and(_T_2548, UInt<1>(0h1)) node _T_2550 = and(_T_2549, UInt<1>(0h1)) when _T_2550 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2551 = or(d_set, inflight_2) node _T_2552 = dshr(_T_2551, io.in.e.bits.sink) node _T_2553 = bits(_T_2552, 0, 0) node _T_2554 = asUInt(reset) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) when _T_2555 : node _T_2556 = eq(_T_2553, UInt<1>(0h0)) when _T_2556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2553, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_68( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [5:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [7:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [5:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [7:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [7:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire [3:0] _GEN_1 = {2'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [3:0] _GEN_4 = {2'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [3:0] _GEN_6 = {2'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [63:0] inflight_2; // @[Monitor.scala:828:27] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [63:0] _GEN_9 = {58'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [63:0] d_set = _GEN_8 ? 64'h1 << _GEN_9 : 64'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [63:0] _GEN_11 = {58'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module BTB : input clock : Clock input reset : Reset output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<48>}}, resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<48>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}}, flip btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<48>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<48>, target : UInt<48>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<48>, cfiType : UInt<2>}}, flip bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<48>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, flip bht_advance : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<48>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}}, flip ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<48>}}, ras_head : { valid : UInt<1>, bits : UInt<48>}, flip flush : UInt<1>} reg idxs : UInt<13>[28], clock reg idxPages : UInt<3>[28], clock reg tgts : UInt<13>[28], clock reg tgtPages : UInt<3>[28], clock reg pages : UInt<34>[6], clock regreset pageValid : UInt<6>, clock, reset, UInt<6>(0h0) node _pagesMasked_T = bits(pageValid, 0, 0) node _pagesMasked_T_1 = bits(pageValid, 1, 1) node _pagesMasked_T_2 = bits(pageValid, 2, 2) node _pagesMasked_T_3 = bits(pageValid, 3, 3) node _pagesMasked_T_4 = bits(pageValid, 4, 4) node _pagesMasked_T_5 = bits(pageValid, 5, 5) node pagesMasked_0 = mux(_pagesMasked_T, pages[0], UInt<1>(0h0)) node pagesMasked_1 = mux(_pagesMasked_T_1, pages[1], UInt<1>(0h0)) node pagesMasked_2 = mux(_pagesMasked_T_2, pages[2], UInt<1>(0h0)) node pagesMasked_3 = mux(_pagesMasked_T_3, pages[3], UInt<1>(0h0)) node pagesMasked_4 = mux(_pagesMasked_T_4, pages[4], UInt<1>(0h0)) node pagesMasked_5 = mux(_pagesMasked_T_5, pages[5], UInt<1>(0h0)) regreset isValid : UInt<28>, clock, reset, UInt<28>(0h0) reg cfiType : UInt<2>[28], clock reg brIdx : UInt<1>[28], clock regreset r_btb_update_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect r_btb_update_pipe_v, io.btb_update.valid reg r_btb_update_pipe_b : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<48>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<48>, target : UInt<48>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<48>, cfiType : UInt<2>}, clock when io.btb_update.valid : connect r_btb_update_pipe_b, io.btb_update.bits wire r_btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<48>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<48>, target : UInt<48>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<48>, cfiType : UInt<2>}} connect r_btb_update.valid, r_btb_update_pipe_v connect r_btb_update.bits, r_btb_update_pipe_b node pageHit_p = shr(io.req.bits.addr, 14) node _pageHit_T = eq(pages[0], pageHit_p) node _pageHit_T_1 = eq(pages[1], pageHit_p) node _pageHit_T_2 = eq(pages[2], pageHit_p) node _pageHit_T_3 = eq(pages[3], pageHit_p) node _pageHit_T_4 = eq(pages[4], pageHit_p) node _pageHit_T_5 = eq(pages[5], pageHit_p) node pageHit_lo_hi = cat(_pageHit_T_2, _pageHit_T_1) node pageHit_lo = cat(pageHit_lo_hi, _pageHit_T) node pageHit_hi_hi = cat(_pageHit_T_5, _pageHit_T_4) node pageHit_hi = cat(pageHit_hi_hi, _pageHit_T_3) node _pageHit_T_6 = cat(pageHit_hi, pageHit_lo) node pageHit = and(pageValid, _pageHit_T_6) node idxHit_idx = bits(io.req.bits.addr, 13, 1) node _idxHit_T = eq(idxs[0], idxHit_idx) node _idxHit_T_1 = eq(idxs[1], idxHit_idx) node _idxHit_T_2 = eq(idxs[2], idxHit_idx) node _idxHit_T_3 = eq(idxs[3], idxHit_idx) node _idxHit_T_4 = eq(idxs[4], idxHit_idx) node _idxHit_T_5 = eq(idxs[5], idxHit_idx) node _idxHit_T_6 = eq(idxs[6], idxHit_idx) node _idxHit_T_7 = eq(idxs[7], idxHit_idx) node _idxHit_T_8 = eq(idxs[8], idxHit_idx) node _idxHit_T_9 = eq(idxs[9], idxHit_idx) node _idxHit_T_10 = eq(idxs[10], idxHit_idx) node _idxHit_T_11 = eq(idxs[11], idxHit_idx) node _idxHit_T_12 = eq(idxs[12], idxHit_idx) node _idxHit_T_13 = eq(idxs[13], idxHit_idx) node _idxHit_T_14 = eq(idxs[14], idxHit_idx) node _idxHit_T_15 = eq(idxs[15], idxHit_idx) node _idxHit_T_16 = eq(idxs[16], idxHit_idx) node _idxHit_T_17 = eq(idxs[17], idxHit_idx) node _idxHit_T_18 = eq(idxs[18], idxHit_idx) node _idxHit_T_19 = eq(idxs[19], idxHit_idx) node _idxHit_T_20 = eq(idxs[20], idxHit_idx) node _idxHit_T_21 = eq(idxs[21], idxHit_idx) node _idxHit_T_22 = eq(idxs[22], idxHit_idx) node _idxHit_T_23 = eq(idxs[23], idxHit_idx) node _idxHit_T_24 = eq(idxs[24], idxHit_idx) node _idxHit_T_25 = eq(idxs[25], idxHit_idx) node _idxHit_T_26 = eq(idxs[26], idxHit_idx) node _idxHit_T_27 = eq(idxs[27], idxHit_idx) node idxHit_lo_lo_lo_hi = cat(_idxHit_T_2, _idxHit_T_1) node idxHit_lo_lo_lo = cat(idxHit_lo_lo_lo_hi, _idxHit_T) node idxHit_lo_lo_hi_lo = cat(_idxHit_T_4, _idxHit_T_3) node idxHit_lo_lo_hi_hi = cat(_idxHit_T_6, _idxHit_T_5) node idxHit_lo_lo_hi = cat(idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo) node idxHit_lo_lo = cat(idxHit_lo_lo_hi, idxHit_lo_lo_lo) node idxHit_lo_hi_lo_hi = cat(_idxHit_T_9, _idxHit_T_8) node idxHit_lo_hi_lo = cat(idxHit_lo_hi_lo_hi, _idxHit_T_7) node idxHit_lo_hi_hi_lo = cat(_idxHit_T_11, _idxHit_T_10) node idxHit_lo_hi_hi_hi = cat(_idxHit_T_13, _idxHit_T_12) node idxHit_lo_hi_hi = cat(idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo) node idxHit_lo_hi = cat(idxHit_lo_hi_hi, idxHit_lo_hi_lo) node idxHit_lo = cat(idxHit_lo_hi, idxHit_lo_lo) node idxHit_hi_lo_lo_hi = cat(_idxHit_T_16, _idxHit_T_15) node idxHit_hi_lo_lo = cat(idxHit_hi_lo_lo_hi, _idxHit_T_14) node idxHit_hi_lo_hi_lo = cat(_idxHit_T_18, _idxHit_T_17) node idxHit_hi_lo_hi_hi = cat(_idxHit_T_20, _idxHit_T_19) node idxHit_hi_lo_hi = cat(idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo) node idxHit_hi_lo = cat(idxHit_hi_lo_hi, idxHit_hi_lo_lo) node idxHit_hi_hi_lo_hi = cat(_idxHit_T_23, _idxHit_T_22) node idxHit_hi_hi_lo = cat(idxHit_hi_hi_lo_hi, _idxHit_T_21) node idxHit_hi_hi_hi_lo = cat(_idxHit_T_25, _idxHit_T_24) node idxHit_hi_hi_hi_hi = cat(_idxHit_T_27, _idxHit_T_26) node idxHit_hi_hi_hi = cat(idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo) node idxHit_hi_hi = cat(idxHit_hi_hi_hi, idxHit_hi_hi_lo) node idxHit_hi = cat(idxHit_hi_hi, idxHit_hi_lo) node _idxHit_T_28 = cat(idxHit_hi, idxHit_lo) node idxHit = and(_idxHit_T_28, isValid) node updatePageHit_p = shr(r_btb_update.bits.pc, 14) node _updatePageHit_T = eq(pages[0], updatePageHit_p) node _updatePageHit_T_1 = eq(pages[1], updatePageHit_p) node _updatePageHit_T_2 = eq(pages[2], updatePageHit_p) node _updatePageHit_T_3 = eq(pages[3], updatePageHit_p) node _updatePageHit_T_4 = eq(pages[4], updatePageHit_p) node _updatePageHit_T_5 = eq(pages[5], updatePageHit_p) node updatePageHit_lo_hi = cat(_updatePageHit_T_2, _updatePageHit_T_1) node updatePageHit_lo = cat(updatePageHit_lo_hi, _updatePageHit_T) node updatePageHit_hi_hi = cat(_updatePageHit_T_5, _updatePageHit_T_4) node updatePageHit_hi = cat(updatePageHit_hi_hi, _updatePageHit_T_3) node _updatePageHit_T_6 = cat(updatePageHit_hi, updatePageHit_lo) node updatePageHit = and(pageValid, _updatePageHit_T_6) node updateHit = lt(r_btb_update.bits.prediction.entry, UInt<5>(0h1c)) node useUpdatePageHit = orr(updatePageHit) node usePageHit = orr(pageHit) node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>(0h0)) regreset nextPageRepl : UInt<3>, clock, reset, UInt<3>(0h0) node _idxPageRepl_T = bits(pageHit, 4, 0) node _idxPageRepl_T_1 = bits(pageHit, 5, 5) node _idxPageRepl_T_2 = cat(_idxPageRepl_T, _idxPageRepl_T_1) node _idxPageRepl_T_3 = dshl(UInt<1>(0h1), nextPageRepl) node _idxPageRepl_T_4 = mux(usePageHit, UInt<1>(0h0), _idxPageRepl_T_3) node idxPageRepl = or(_idxPageRepl_T_2, _idxPageRepl_T_4) node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) node idxPageUpdate_hi = bits(idxPageUpdateOH, 7, 4) node idxPageUpdate_lo = bits(idxPageUpdateOH, 3, 0) node _idxPageUpdate_T = orr(idxPageUpdate_hi) node _idxPageUpdate_T_1 = or(idxPageUpdate_hi, idxPageUpdate_lo) node idxPageUpdate_hi_1 = bits(_idxPageUpdate_T_1, 3, 2) node idxPageUpdate_lo_1 = bits(_idxPageUpdate_T_1, 1, 0) node _idxPageUpdate_T_2 = orr(idxPageUpdate_hi_1) node _idxPageUpdate_T_3 = or(idxPageUpdate_hi_1, idxPageUpdate_lo_1) node _idxPageUpdate_T_4 = bits(_idxPageUpdate_T_3, 1, 1) node _idxPageUpdate_T_5 = cat(_idxPageUpdate_T_2, _idxPageUpdate_T_4) node idxPageUpdate = cat(_idxPageUpdate_T, _idxPageUpdate_T_5) node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>(0h0)) node _samePage_T = shr(r_btb_update.bits.pc, 14) node _samePage_T_1 = shr(io.req.bits.addr, 14) node samePage = eq(_samePage_T, _samePage_T_1) node _doTgtPageRepl_T = eq(samePage, UInt<1>(0h0)) node _doTgtPageRepl_T_1 = eq(usePageHit, UInt<1>(0h0)) node doTgtPageRepl = and(_doTgtPageRepl_T, _doTgtPageRepl_T_1) node _tgtPageRepl_T = bits(idxPageUpdateOH, 4, 0) node _tgtPageRepl_T_1 = bits(idxPageUpdateOH, 5, 5) node _tgtPageRepl_T_2 = cat(_tgtPageRepl_T, _tgtPageRepl_T_1) node tgtPageRepl = mux(samePage, idxPageUpdateOH, _tgtPageRepl_T_2) node _tgtPageUpdate_T = mux(usePageHit, UInt<1>(0h0), tgtPageRepl) node _tgtPageUpdate_T_1 = or(pageHit, _tgtPageUpdate_T) node tgtPageUpdate_hi = bits(_tgtPageUpdate_T_1, 7, 4) node tgtPageUpdate_lo = bits(_tgtPageUpdate_T_1, 3, 0) node _tgtPageUpdate_T_2 = orr(tgtPageUpdate_hi) node _tgtPageUpdate_T_3 = or(tgtPageUpdate_hi, tgtPageUpdate_lo) node tgtPageUpdate_hi_1 = bits(_tgtPageUpdate_T_3, 3, 2) node tgtPageUpdate_lo_1 = bits(_tgtPageUpdate_T_3, 1, 0) node _tgtPageUpdate_T_4 = orr(tgtPageUpdate_hi_1) node _tgtPageUpdate_T_5 = or(tgtPageUpdate_hi_1, tgtPageUpdate_lo_1) node _tgtPageUpdate_T_6 = bits(_tgtPageUpdate_T_5, 1, 1) node _tgtPageUpdate_T_7 = cat(_tgtPageUpdate_T_4, _tgtPageUpdate_T_6) node tgtPageUpdate = cat(_tgtPageUpdate_T_2, _tgtPageUpdate_T_7) node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>(0h0)) node _T = or(doIdxPageRepl, doTgtPageRepl) node _T_1 = and(r_btb_update.valid, _T) when _T_1 : node both = and(doIdxPageRepl, doTgtPageRepl) node _next_T = mux(both, UInt<2>(0h2), UInt<1>(0h1)) node _next_T_1 = add(nextPageRepl, _next_T) node next = tail(_next_T_1, 1) node _nextPageRepl_T = geq(next, UInt<3>(0h6)) node _nextPageRepl_T_1 = bits(next, 0, 0) node _nextPageRepl_T_2 = mux(_nextPageRepl_T, _nextPageRepl_T_1, next) connect nextPageRepl, _nextPageRepl_T_2 regreset state_reg : UInt<27>, clock, reset, UInt<27>(0h0) node waddr_left_subtree_older = bits(state_reg, 26, 26) node waddr_left_subtree_state = bits(state_reg, 25, 15) node waddr_right_subtree_state = bits(state_reg, 14, 0) node waddr_left_subtree_older_1 = bits(waddr_left_subtree_state, 10, 10) node waddr_left_subtree_state_1 = bits(waddr_left_subtree_state, 9, 7) node waddr_right_subtree_state_1 = bits(waddr_left_subtree_state, 6, 0) node waddr_left_subtree_older_2 = bits(waddr_left_subtree_state_1, 2, 2) node waddr_left_subtree_state_2 = bits(waddr_left_subtree_state_1, 1, 1) node waddr_right_subtree_state_2 = bits(waddr_left_subtree_state_1, 0, 0) node _waddr_T = bits(waddr_left_subtree_state_2, 0, 0) node _waddr_T_1 = bits(waddr_right_subtree_state_2, 0, 0) node _waddr_T_2 = mux(waddr_left_subtree_older_2, _waddr_T, _waddr_T_1) node _waddr_T_3 = cat(waddr_left_subtree_older_2, _waddr_T_2) node waddr_left_subtree_older_3 = bits(waddr_right_subtree_state_1, 6, 6) node waddr_left_subtree_state_3 = bits(waddr_right_subtree_state_1, 5, 3) node waddr_right_subtree_state_3 = bits(waddr_right_subtree_state_1, 2, 0) node waddr_left_subtree_older_4 = bits(waddr_left_subtree_state_3, 2, 2) node waddr_left_subtree_state_4 = bits(waddr_left_subtree_state_3, 1, 1) node waddr_right_subtree_state_4 = bits(waddr_left_subtree_state_3, 0, 0) node _waddr_T_4 = bits(waddr_left_subtree_state_4, 0, 0) node _waddr_T_5 = bits(waddr_right_subtree_state_4, 0, 0) node _waddr_T_6 = mux(waddr_left_subtree_older_4, _waddr_T_4, _waddr_T_5) node _waddr_T_7 = cat(waddr_left_subtree_older_4, _waddr_T_6) node waddr_left_subtree_older_5 = bits(waddr_right_subtree_state_3, 2, 2) node waddr_left_subtree_state_5 = bits(waddr_right_subtree_state_3, 1, 1) node waddr_right_subtree_state_5 = bits(waddr_right_subtree_state_3, 0, 0) node _waddr_T_8 = bits(waddr_left_subtree_state_5, 0, 0) node _waddr_T_9 = bits(waddr_right_subtree_state_5, 0, 0) node _waddr_T_10 = mux(waddr_left_subtree_older_5, _waddr_T_8, _waddr_T_9) node _waddr_T_11 = cat(waddr_left_subtree_older_5, _waddr_T_10) node _waddr_T_12 = mux(waddr_left_subtree_older_3, _waddr_T_7, _waddr_T_11) node _waddr_T_13 = cat(waddr_left_subtree_older_3, _waddr_T_12) node _waddr_T_14 = mux(waddr_left_subtree_older_1, _waddr_T_3, _waddr_T_13) node _waddr_T_15 = cat(waddr_left_subtree_older_1, _waddr_T_14) node waddr_left_subtree_older_6 = bits(waddr_right_subtree_state, 14, 14) node waddr_left_subtree_state_6 = bits(waddr_right_subtree_state, 13, 7) node waddr_right_subtree_state_6 = bits(waddr_right_subtree_state, 6, 0) node waddr_left_subtree_older_7 = bits(waddr_left_subtree_state_6, 6, 6) node waddr_left_subtree_state_7 = bits(waddr_left_subtree_state_6, 5, 3) node waddr_right_subtree_state_7 = bits(waddr_left_subtree_state_6, 2, 0) node waddr_left_subtree_older_8 = bits(waddr_left_subtree_state_7, 2, 2) node waddr_left_subtree_state_8 = bits(waddr_left_subtree_state_7, 1, 1) node waddr_right_subtree_state_8 = bits(waddr_left_subtree_state_7, 0, 0) node _waddr_T_16 = bits(waddr_left_subtree_state_8, 0, 0) node _waddr_T_17 = bits(waddr_right_subtree_state_8, 0, 0) node _waddr_T_18 = mux(waddr_left_subtree_older_8, _waddr_T_16, _waddr_T_17) node _waddr_T_19 = cat(waddr_left_subtree_older_8, _waddr_T_18) node waddr_left_subtree_older_9 = bits(waddr_right_subtree_state_7, 2, 2) node waddr_left_subtree_state_9 = bits(waddr_right_subtree_state_7, 1, 1) node waddr_right_subtree_state_9 = bits(waddr_right_subtree_state_7, 0, 0) node _waddr_T_20 = bits(waddr_left_subtree_state_9, 0, 0) node _waddr_T_21 = bits(waddr_right_subtree_state_9, 0, 0) node _waddr_T_22 = mux(waddr_left_subtree_older_9, _waddr_T_20, _waddr_T_21) node _waddr_T_23 = cat(waddr_left_subtree_older_9, _waddr_T_22) node _waddr_T_24 = mux(waddr_left_subtree_older_7, _waddr_T_19, _waddr_T_23) node _waddr_T_25 = cat(waddr_left_subtree_older_7, _waddr_T_24) node waddr_left_subtree_older_10 = bits(waddr_right_subtree_state_6, 6, 6) node waddr_left_subtree_state_10 = bits(waddr_right_subtree_state_6, 5, 3) node waddr_right_subtree_state_10 = bits(waddr_right_subtree_state_6, 2, 0) node waddr_left_subtree_older_11 = bits(waddr_left_subtree_state_10, 2, 2) node waddr_left_subtree_state_11 = bits(waddr_left_subtree_state_10, 1, 1) node waddr_right_subtree_state_11 = bits(waddr_left_subtree_state_10, 0, 0) node _waddr_T_26 = bits(waddr_left_subtree_state_11, 0, 0) node _waddr_T_27 = bits(waddr_right_subtree_state_11, 0, 0) node _waddr_T_28 = mux(waddr_left_subtree_older_11, _waddr_T_26, _waddr_T_27) node _waddr_T_29 = cat(waddr_left_subtree_older_11, _waddr_T_28) node waddr_left_subtree_older_12 = bits(waddr_right_subtree_state_10, 2, 2) node waddr_left_subtree_state_12 = bits(waddr_right_subtree_state_10, 1, 1) node waddr_right_subtree_state_12 = bits(waddr_right_subtree_state_10, 0, 0) node _waddr_T_30 = bits(waddr_left_subtree_state_12, 0, 0) node _waddr_T_31 = bits(waddr_right_subtree_state_12, 0, 0) node _waddr_T_32 = mux(waddr_left_subtree_older_12, _waddr_T_30, _waddr_T_31) node _waddr_T_33 = cat(waddr_left_subtree_older_12, _waddr_T_32) node _waddr_T_34 = mux(waddr_left_subtree_older_10, _waddr_T_29, _waddr_T_33) node _waddr_T_35 = cat(waddr_left_subtree_older_10, _waddr_T_34) node _waddr_T_36 = mux(waddr_left_subtree_older_6, _waddr_T_25, _waddr_T_35) node _waddr_T_37 = cat(waddr_left_subtree_older_6, _waddr_T_36) node _waddr_T_38 = mux(waddr_left_subtree_older, _waddr_T_15, _waddr_T_37) node _waddr_T_39 = cat(waddr_left_subtree_older, _waddr_T_38) node waddr = mux(updateHit, r_btb_update.bits.prediction.entry, _waddr_T_39) regreset r_resp_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect r_resp_pipe_v, io.resp.valid reg r_resp_pipe_b : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<48>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock when io.resp.valid : connect r_resp_pipe_b.bht.value, io.resp.bits.bht.value connect r_resp_pipe_b.bht.history, io.resp.bits.bht.history connect r_resp_pipe_b.entry, io.resp.bits.entry connect r_resp_pipe_b.target, io.resp.bits.target connect r_resp_pipe_b.bridx, io.resp.bits.bridx connect r_resp_pipe_b.mask, io.resp.bits.mask connect r_resp_pipe_b.taken, io.resp.bits.taken connect r_resp_pipe_b.cfiType, io.resp.bits.cfiType wire r_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<48>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}} connect r_resp.valid, r_resp_pipe_v connect r_resp.bits, r_resp_pipe_b node _T_2 = and(r_resp.valid, r_resp.bits.taken) node _T_3 = or(_T_2, r_btb_update.valid) when _T_3 : node _T_4 = mux(r_btb_update.valid, waddr, r_resp.bits.entry) node state_reg_touch_way_sized = bits(_T_4, 4, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 4, 4) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg, 25, 15) node state_reg_right_subtree_state = bits(state_reg, 14, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 3, 0) node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 3, 3) node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 9, 7) node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 6, 0) node _state_reg_T_1 = bits(_state_reg_T, 1, 0) node _state_reg_set_left_older_T_2 = bits(_state_reg_T_1, 1, 1) node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) node state_reg_left_subtree_state_2 = bits(state_reg_left_subtree_state_1, 1, 1) node state_reg_right_subtree_state_2 = bits(state_reg_left_subtree_state_1, 0, 0) node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_3 = bits(_state_reg_T_2, 0, 0) node _state_reg_T_4 = eq(_state_reg_T_3, UInt<1>(0h0)) node _state_reg_T_5 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_4) node _state_reg_T_6 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_7 = bits(_state_reg_T_6, 0, 0) node _state_reg_T_8 = eq(_state_reg_T_7, UInt<1>(0h0)) node _state_reg_T_9 = mux(state_reg_set_left_older_2, _state_reg_T_8, state_reg_right_subtree_state_2) node state_reg_hi = cat(state_reg_set_left_older_2, _state_reg_T_5) node _state_reg_T_10 = cat(state_reg_hi, _state_reg_T_9) node _state_reg_T_11 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_10) node _state_reg_T_12 = bits(_state_reg_T, 2, 0) node _state_reg_set_left_older_T_3 = bits(_state_reg_T_12, 2, 2) node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) node state_reg_left_subtree_state_3 = bits(state_reg_right_subtree_state_1, 5, 3) node state_reg_right_subtree_state_3 = bits(state_reg_right_subtree_state_1, 2, 0) node _state_reg_T_13 = bits(_state_reg_T_12, 1, 0) node _state_reg_set_left_older_T_4 = bits(_state_reg_T_13, 1, 1) node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0)) node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1) node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0) node _state_reg_T_14 = bits(_state_reg_T_13, 0, 0) node _state_reg_T_15 = bits(_state_reg_T_14, 0, 0) node _state_reg_T_16 = eq(_state_reg_T_15, UInt<1>(0h0)) node _state_reg_T_17 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_16) node _state_reg_T_18 = bits(_state_reg_T_13, 0, 0) node _state_reg_T_19 = bits(_state_reg_T_18, 0, 0) node _state_reg_T_20 = eq(_state_reg_T_19, UInt<1>(0h0)) node _state_reg_T_21 = mux(state_reg_set_left_older_4, _state_reg_T_20, state_reg_right_subtree_state_4) node state_reg_hi_1 = cat(state_reg_set_left_older_4, _state_reg_T_17) node _state_reg_T_22 = cat(state_reg_hi_1, _state_reg_T_21) node _state_reg_T_23 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_22) node _state_reg_T_24 = bits(_state_reg_T_12, 1, 0) node _state_reg_set_left_older_T_5 = bits(_state_reg_T_24, 1, 1) node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0)) node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1) node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0) node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0) node _state_reg_T_26 = bits(_state_reg_T_25, 0, 0) node _state_reg_T_27 = eq(_state_reg_T_26, UInt<1>(0h0)) node _state_reg_T_28 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_27) node _state_reg_T_29 = bits(_state_reg_T_24, 0, 0) node _state_reg_T_30 = bits(_state_reg_T_29, 0, 0) node _state_reg_T_31 = eq(_state_reg_T_30, UInt<1>(0h0)) node _state_reg_T_32 = mux(state_reg_set_left_older_5, _state_reg_T_31, state_reg_right_subtree_state_5) node state_reg_hi_2 = cat(state_reg_set_left_older_5, _state_reg_T_28) node _state_reg_T_33 = cat(state_reg_hi_2, _state_reg_T_32) node _state_reg_T_34 = mux(state_reg_set_left_older_3, _state_reg_T_33, state_reg_right_subtree_state_3) node state_reg_hi_3 = cat(state_reg_set_left_older_3, _state_reg_T_23) node _state_reg_T_35 = cat(state_reg_hi_3, _state_reg_T_34) node _state_reg_T_36 = mux(state_reg_set_left_older_1, _state_reg_T_35, state_reg_right_subtree_state_1) node state_reg_hi_4 = cat(state_reg_set_left_older_1, _state_reg_T_11) node _state_reg_T_37 = cat(state_reg_hi_4, _state_reg_T_36) node _state_reg_T_38 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_37) node _state_reg_T_39 = bits(state_reg_touch_way_sized, 3, 0) node _state_reg_set_left_older_T_6 = bits(_state_reg_T_39, 3, 3) node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0)) node state_reg_left_subtree_state_6 = bits(state_reg_right_subtree_state, 13, 7) node state_reg_right_subtree_state_6 = bits(state_reg_right_subtree_state, 6, 0) node _state_reg_T_40 = bits(_state_reg_T_39, 2, 0) node _state_reg_set_left_older_T_7 = bits(_state_reg_T_40, 2, 2) node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0)) node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 5, 3) node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 2, 0) node _state_reg_T_41 = bits(_state_reg_T_40, 1, 0) node _state_reg_set_left_older_T_8 = bits(_state_reg_T_41, 1, 1) node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0)) node state_reg_left_subtree_state_8 = bits(state_reg_left_subtree_state_7, 1, 1) node state_reg_right_subtree_state_8 = bits(state_reg_left_subtree_state_7, 0, 0) node _state_reg_T_42 = bits(_state_reg_T_41, 0, 0) node _state_reg_T_43 = bits(_state_reg_T_42, 0, 0) node _state_reg_T_44 = eq(_state_reg_T_43, UInt<1>(0h0)) node _state_reg_T_45 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_44) node _state_reg_T_46 = bits(_state_reg_T_41, 0, 0) node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_48 = eq(_state_reg_T_47, UInt<1>(0h0)) node _state_reg_T_49 = mux(state_reg_set_left_older_8, _state_reg_T_48, state_reg_right_subtree_state_8) node state_reg_hi_5 = cat(state_reg_set_left_older_8, _state_reg_T_45) node _state_reg_T_50 = cat(state_reg_hi_5, _state_reg_T_49) node _state_reg_T_51 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_50) node _state_reg_T_52 = bits(_state_reg_T_40, 1, 0) node _state_reg_set_left_older_T_9 = bits(_state_reg_T_52, 1, 1) node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0)) node state_reg_left_subtree_state_9 = bits(state_reg_right_subtree_state_7, 1, 1) node state_reg_right_subtree_state_9 = bits(state_reg_right_subtree_state_7, 0, 0) node _state_reg_T_53 = bits(_state_reg_T_52, 0, 0) node _state_reg_T_54 = bits(_state_reg_T_53, 0, 0) node _state_reg_T_55 = eq(_state_reg_T_54, UInt<1>(0h0)) node _state_reg_T_56 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_55) node _state_reg_T_57 = bits(_state_reg_T_52, 0, 0) node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_59 = eq(_state_reg_T_58, UInt<1>(0h0)) node _state_reg_T_60 = mux(state_reg_set_left_older_9, _state_reg_T_59, state_reg_right_subtree_state_9) node state_reg_hi_6 = cat(state_reg_set_left_older_9, _state_reg_T_56) node _state_reg_T_61 = cat(state_reg_hi_6, _state_reg_T_60) node _state_reg_T_62 = mux(state_reg_set_left_older_7, _state_reg_T_61, state_reg_right_subtree_state_7) node state_reg_hi_7 = cat(state_reg_set_left_older_7, _state_reg_T_51) node _state_reg_T_63 = cat(state_reg_hi_7, _state_reg_T_62) node _state_reg_T_64 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_63) node _state_reg_T_65 = bits(_state_reg_T_39, 2, 0) node _state_reg_set_left_older_T_10 = bits(_state_reg_T_65, 2, 2) node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0)) node state_reg_left_subtree_state_10 = bits(state_reg_right_subtree_state_6, 5, 3) node state_reg_right_subtree_state_10 = bits(state_reg_right_subtree_state_6, 2, 0) node _state_reg_T_66 = bits(_state_reg_T_65, 1, 0) node _state_reg_set_left_older_T_11 = bits(_state_reg_T_66, 1, 1) node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0)) node state_reg_left_subtree_state_11 = bits(state_reg_left_subtree_state_10, 1, 1) node state_reg_right_subtree_state_11 = bits(state_reg_left_subtree_state_10, 0, 0) node _state_reg_T_67 = bits(_state_reg_T_66, 0, 0) node _state_reg_T_68 = bits(_state_reg_T_67, 0, 0) node _state_reg_T_69 = eq(_state_reg_T_68, UInt<1>(0h0)) node _state_reg_T_70 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_69) node _state_reg_T_71 = bits(_state_reg_T_66, 0, 0) node _state_reg_T_72 = bits(_state_reg_T_71, 0, 0) node _state_reg_T_73 = eq(_state_reg_T_72, UInt<1>(0h0)) node _state_reg_T_74 = mux(state_reg_set_left_older_11, _state_reg_T_73, state_reg_right_subtree_state_11) node state_reg_hi_8 = cat(state_reg_set_left_older_11, _state_reg_T_70) node _state_reg_T_75 = cat(state_reg_hi_8, _state_reg_T_74) node _state_reg_T_76 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_75) node _state_reg_T_77 = bits(_state_reg_T_65, 1, 0) node _state_reg_set_left_older_T_12 = bits(_state_reg_T_77, 1, 1) node state_reg_set_left_older_12 = eq(_state_reg_set_left_older_T_12, UInt<1>(0h0)) node state_reg_left_subtree_state_12 = bits(state_reg_right_subtree_state_10, 1, 1) node state_reg_right_subtree_state_12 = bits(state_reg_right_subtree_state_10, 0, 0) node _state_reg_T_78 = bits(_state_reg_T_77, 0, 0) node _state_reg_T_79 = bits(_state_reg_T_78, 0, 0) node _state_reg_T_80 = eq(_state_reg_T_79, UInt<1>(0h0)) node _state_reg_T_81 = mux(state_reg_set_left_older_12, state_reg_left_subtree_state_12, _state_reg_T_80) node _state_reg_T_82 = bits(_state_reg_T_77, 0, 0) node _state_reg_T_83 = bits(_state_reg_T_82, 0, 0) node _state_reg_T_84 = eq(_state_reg_T_83, UInt<1>(0h0)) node _state_reg_T_85 = mux(state_reg_set_left_older_12, _state_reg_T_84, state_reg_right_subtree_state_12) node state_reg_hi_9 = cat(state_reg_set_left_older_12, _state_reg_T_81) node _state_reg_T_86 = cat(state_reg_hi_9, _state_reg_T_85) node _state_reg_T_87 = mux(state_reg_set_left_older_10, _state_reg_T_86, state_reg_right_subtree_state_10) node state_reg_hi_10 = cat(state_reg_set_left_older_10, _state_reg_T_76) node _state_reg_T_88 = cat(state_reg_hi_10, _state_reg_T_87) node _state_reg_T_89 = mux(state_reg_set_left_older_6, _state_reg_T_88, state_reg_right_subtree_state_6) node state_reg_hi_11 = cat(state_reg_set_left_older_6, _state_reg_T_64) node _state_reg_T_90 = cat(state_reg_hi_11, _state_reg_T_89) node _state_reg_T_91 = mux(state_reg_set_left_older, _state_reg_T_90, state_reg_right_subtree_state) node state_reg_hi_12 = cat(state_reg_set_left_older, _state_reg_T_38) node _state_reg_T_92 = cat(state_reg_hi_12, _state_reg_T_91) connect state_reg, _state_reg_T_92 when r_btb_update.valid : node mask = dshl(UInt<1>(0h1), waddr) node _idxs_T = bits(r_btb_update.bits.pc, 13, 1) connect idxs[waddr], _idxs_T node _tgts_T = bits(io.req.bits.addr, 13, 1) connect tgts[waddr], _tgts_T node _idxPages_T = add(idxPageUpdate, UInt<1>(0h1)) connect idxPages[waddr], _idxPages_T connect tgtPages[waddr], tgtPageUpdate connect cfiType[waddr], r_btb_update.bits.cfiType node _isValid_T = or(isValid, mask) node _isValid_T_1 = not(mask) node _isValid_T_2 = and(isValid, _isValid_T_1) node _isValid_T_3 = mux(r_btb_update.bits.isValid, _isValid_T, _isValid_T_2) connect isValid, _isValid_T_3 node _brIdx_T = shr(r_btb_update.bits.br_pc, 1) connect brIdx[waddr], _brIdx_T node _idxWritesEven_T = bits(idxPageUpdate, 0, 0) node idxWritesEven = eq(_idxWritesEven_T, UInt<1>(0h0)) node _T_5 = mux(idxWritesEven, idxPageReplEn, tgtPageReplEn) node _T_6 = shr(r_btb_update.bits.pc, 14) node _T_7 = shr(io.req.bits.addr, 14) node _T_8 = mux(idxWritesEven, _T_6, _T_7) node _T_9 = bits(_T_5, 0, 0) when _T_9 : connect pages[0], _T_8 node _T_10 = bits(_T_5, 2, 2) when _T_10 : connect pages[2], _T_8 node _T_11 = bits(_T_5, 4, 4) when _T_11 : connect pages[4], _T_8 node _T_12 = mux(idxWritesEven, tgtPageReplEn, idxPageReplEn) node _T_13 = shr(io.req.bits.addr, 14) node _T_14 = shr(r_btb_update.bits.pc, 14) node _T_15 = mux(idxWritesEven, _T_13, _T_14) node _T_16 = bits(_T_12, 1, 1) when _T_16 : connect pages[1], _T_15 node _T_17 = bits(_T_12, 3, 3) when _T_17 : connect pages[3], _T_15 node _T_18 = bits(_T_12, 5, 5) when _T_18 : connect pages[5], _T_15 node _pageValid_T = or(pageValid, tgtPageReplEn) node _pageValid_T_1 = or(_pageValid_T, idxPageReplEn) connect pageValid, _pageValid_T_1 node _io_resp_valid_T = shl(pageHit, 1) node _io_resp_valid_T_1 = bits(idxHit, 0, 0) node _io_resp_valid_T_2 = bits(idxHit, 1, 1) node _io_resp_valid_T_3 = bits(idxHit, 2, 2) node _io_resp_valid_T_4 = bits(idxHit, 3, 3) node _io_resp_valid_T_5 = bits(idxHit, 4, 4) node _io_resp_valid_T_6 = bits(idxHit, 5, 5) node _io_resp_valid_T_7 = bits(idxHit, 6, 6) node _io_resp_valid_T_8 = bits(idxHit, 7, 7) node _io_resp_valid_T_9 = bits(idxHit, 8, 8) node _io_resp_valid_T_10 = bits(idxHit, 9, 9) node _io_resp_valid_T_11 = bits(idxHit, 10, 10) node _io_resp_valid_T_12 = bits(idxHit, 11, 11) node _io_resp_valid_T_13 = bits(idxHit, 12, 12) node _io_resp_valid_T_14 = bits(idxHit, 13, 13) node _io_resp_valid_T_15 = bits(idxHit, 14, 14) node _io_resp_valid_T_16 = bits(idxHit, 15, 15) node _io_resp_valid_T_17 = bits(idxHit, 16, 16) node _io_resp_valid_T_18 = bits(idxHit, 17, 17) node _io_resp_valid_T_19 = bits(idxHit, 18, 18) node _io_resp_valid_T_20 = bits(idxHit, 19, 19) node _io_resp_valid_T_21 = bits(idxHit, 20, 20) node _io_resp_valid_T_22 = bits(idxHit, 21, 21) node _io_resp_valid_T_23 = bits(idxHit, 22, 22) node _io_resp_valid_T_24 = bits(idxHit, 23, 23) node _io_resp_valid_T_25 = bits(idxHit, 24, 24) node _io_resp_valid_T_26 = bits(idxHit, 25, 25) node _io_resp_valid_T_27 = bits(idxHit, 26, 26) node _io_resp_valid_T_28 = bits(idxHit, 27, 27) node _io_resp_valid_T_29 = mux(_io_resp_valid_T_1, idxPages[0], UInt<1>(0h0)) node _io_resp_valid_T_30 = mux(_io_resp_valid_T_2, idxPages[1], UInt<1>(0h0)) node _io_resp_valid_T_31 = mux(_io_resp_valid_T_3, idxPages[2], UInt<1>(0h0)) node _io_resp_valid_T_32 = mux(_io_resp_valid_T_4, idxPages[3], UInt<1>(0h0)) node _io_resp_valid_T_33 = mux(_io_resp_valid_T_5, idxPages[4], UInt<1>(0h0)) node _io_resp_valid_T_34 = mux(_io_resp_valid_T_6, idxPages[5], UInt<1>(0h0)) node _io_resp_valid_T_35 = mux(_io_resp_valid_T_7, idxPages[6], UInt<1>(0h0)) node _io_resp_valid_T_36 = mux(_io_resp_valid_T_8, idxPages[7], UInt<1>(0h0)) node _io_resp_valid_T_37 = mux(_io_resp_valid_T_9, idxPages[8], UInt<1>(0h0)) node _io_resp_valid_T_38 = mux(_io_resp_valid_T_10, idxPages[9], UInt<1>(0h0)) node _io_resp_valid_T_39 = mux(_io_resp_valid_T_11, idxPages[10], UInt<1>(0h0)) node _io_resp_valid_T_40 = mux(_io_resp_valid_T_12, idxPages[11], UInt<1>(0h0)) node _io_resp_valid_T_41 = mux(_io_resp_valid_T_13, idxPages[12], UInt<1>(0h0)) node _io_resp_valid_T_42 = mux(_io_resp_valid_T_14, idxPages[13], UInt<1>(0h0)) node _io_resp_valid_T_43 = mux(_io_resp_valid_T_15, idxPages[14], UInt<1>(0h0)) node _io_resp_valid_T_44 = mux(_io_resp_valid_T_16, idxPages[15], UInt<1>(0h0)) node _io_resp_valid_T_45 = mux(_io_resp_valid_T_17, idxPages[16], UInt<1>(0h0)) node _io_resp_valid_T_46 = mux(_io_resp_valid_T_18, idxPages[17], UInt<1>(0h0)) node _io_resp_valid_T_47 = mux(_io_resp_valid_T_19, idxPages[18], UInt<1>(0h0)) node _io_resp_valid_T_48 = mux(_io_resp_valid_T_20, idxPages[19], UInt<1>(0h0)) node _io_resp_valid_T_49 = mux(_io_resp_valid_T_21, idxPages[20], UInt<1>(0h0)) node _io_resp_valid_T_50 = mux(_io_resp_valid_T_22, idxPages[21], UInt<1>(0h0)) node _io_resp_valid_T_51 = mux(_io_resp_valid_T_23, idxPages[22], UInt<1>(0h0)) node _io_resp_valid_T_52 = mux(_io_resp_valid_T_24, idxPages[23], UInt<1>(0h0)) node _io_resp_valid_T_53 = mux(_io_resp_valid_T_25, idxPages[24], UInt<1>(0h0)) node _io_resp_valid_T_54 = mux(_io_resp_valid_T_26, idxPages[25], UInt<1>(0h0)) node _io_resp_valid_T_55 = mux(_io_resp_valid_T_27, idxPages[26], UInt<1>(0h0)) node _io_resp_valid_T_56 = mux(_io_resp_valid_T_28, idxPages[27], UInt<1>(0h0)) node _io_resp_valid_T_57 = or(_io_resp_valid_T_29, _io_resp_valid_T_30) node _io_resp_valid_T_58 = or(_io_resp_valid_T_57, _io_resp_valid_T_31) node _io_resp_valid_T_59 = or(_io_resp_valid_T_58, _io_resp_valid_T_32) node _io_resp_valid_T_60 = or(_io_resp_valid_T_59, _io_resp_valid_T_33) node _io_resp_valid_T_61 = or(_io_resp_valid_T_60, _io_resp_valid_T_34) node _io_resp_valid_T_62 = or(_io_resp_valid_T_61, _io_resp_valid_T_35) node _io_resp_valid_T_63 = or(_io_resp_valid_T_62, _io_resp_valid_T_36) node _io_resp_valid_T_64 = or(_io_resp_valid_T_63, _io_resp_valid_T_37) node _io_resp_valid_T_65 = or(_io_resp_valid_T_64, _io_resp_valid_T_38) node _io_resp_valid_T_66 = or(_io_resp_valid_T_65, _io_resp_valid_T_39) node _io_resp_valid_T_67 = or(_io_resp_valid_T_66, _io_resp_valid_T_40) node _io_resp_valid_T_68 = or(_io_resp_valid_T_67, _io_resp_valid_T_41) node _io_resp_valid_T_69 = or(_io_resp_valid_T_68, _io_resp_valid_T_42) node _io_resp_valid_T_70 = or(_io_resp_valid_T_69, _io_resp_valid_T_43) node _io_resp_valid_T_71 = or(_io_resp_valid_T_70, _io_resp_valid_T_44) node _io_resp_valid_T_72 = or(_io_resp_valid_T_71, _io_resp_valid_T_45) node _io_resp_valid_T_73 = or(_io_resp_valid_T_72, _io_resp_valid_T_46) node _io_resp_valid_T_74 = or(_io_resp_valid_T_73, _io_resp_valid_T_47) node _io_resp_valid_T_75 = or(_io_resp_valid_T_74, _io_resp_valid_T_48) node _io_resp_valid_T_76 = or(_io_resp_valid_T_75, _io_resp_valid_T_49) node _io_resp_valid_T_77 = or(_io_resp_valid_T_76, _io_resp_valid_T_50) node _io_resp_valid_T_78 = or(_io_resp_valid_T_77, _io_resp_valid_T_51) node _io_resp_valid_T_79 = or(_io_resp_valid_T_78, _io_resp_valid_T_52) node _io_resp_valid_T_80 = or(_io_resp_valid_T_79, _io_resp_valid_T_53) node _io_resp_valid_T_81 = or(_io_resp_valid_T_80, _io_resp_valid_T_54) node _io_resp_valid_T_82 = or(_io_resp_valid_T_81, _io_resp_valid_T_55) node _io_resp_valid_T_83 = or(_io_resp_valid_T_82, _io_resp_valid_T_56) wire _io_resp_valid_WIRE : UInt<3> connect _io_resp_valid_WIRE, _io_resp_valid_T_83 node _io_resp_valid_T_84 = dshr(_io_resp_valid_T, _io_resp_valid_WIRE) node _io_resp_valid_T_85 = bits(_io_resp_valid_T_84, 0, 0) connect io.resp.valid, _io_resp_valid_T_85 connect io.resp.bits.taken, UInt<1>(0h1) node _io_resp_bits_target_T = bits(idxHit, 0, 0) node _io_resp_bits_target_T_1 = bits(idxHit, 1, 1) node _io_resp_bits_target_T_2 = bits(idxHit, 2, 2) node _io_resp_bits_target_T_3 = bits(idxHit, 3, 3) node _io_resp_bits_target_T_4 = bits(idxHit, 4, 4) node _io_resp_bits_target_T_5 = bits(idxHit, 5, 5) node _io_resp_bits_target_T_6 = bits(idxHit, 6, 6) node _io_resp_bits_target_T_7 = bits(idxHit, 7, 7) node _io_resp_bits_target_T_8 = bits(idxHit, 8, 8) node _io_resp_bits_target_T_9 = bits(idxHit, 9, 9) node _io_resp_bits_target_T_10 = bits(idxHit, 10, 10) node _io_resp_bits_target_T_11 = bits(idxHit, 11, 11) node _io_resp_bits_target_T_12 = bits(idxHit, 12, 12) node _io_resp_bits_target_T_13 = bits(idxHit, 13, 13) node _io_resp_bits_target_T_14 = bits(idxHit, 14, 14) node _io_resp_bits_target_T_15 = bits(idxHit, 15, 15) node _io_resp_bits_target_T_16 = bits(idxHit, 16, 16) node _io_resp_bits_target_T_17 = bits(idxHit, 17, 17) node _io_resp_bits_target_T_18 = bits(idxHit, 18, 18) node _io_resp_bits_target_T_19 = bits(idxHit, 19, 19) node _io_resp_bits_target_T_20 = bits(idxHit, 20, 20) node _io_resp_bits_target_T_21 = bits(idxHit, 21, 21) node _io_resp_bits_target_T_22 = bits(idxHit, 22, 22) node _io_resp_bits_target_T_23 = bits(idxHit, 23, 23) node _io_resp_bits_target_T_24 = bits(idxHit, 24, 24) node _io_resp_bits_target_T_25 = bits(idxHit, 25, 25) node _io_resp_bits_target_T_26 = bits(idxHit, 26, 26) node _io_resp_bits_target_T_27 = bits(idxHit, 27, 27) node _io_resp_bits_target_T_28 = mux(_io_resp_bits_target_T, tgtPages[0], UInt<1>(0h0)) node _io_resp_bits_target_T_29 = mux(_io_resp_bits_target_T_1, tgtPages[1], UInt<1>(0h0)) node _io_resp_bits_target_T_30 = mux(_io_resp_bits_target_T_2, tgtPages[2], UInt<1>(0h0)) node _io_resp_bits_target_T_31 = mux(_io_resp_bits_target_T_3, tgtPages[3], UInt<1>(0h0)) node _io_resp_bits_target_T_32 = mux(_io_resp_bits_target_T_4, tgtPages[4], UInt<1>(0h0)) node _io_resp_bits_target_T_33 = mux(_io_resp_bits_target_T_5, tgtPages[5], UInt<1>(0h0)) node _io_resp_bits_target_T_34 = mux(_io_resp_bits_target_T_6, tgtPages[6], UInt<1>(0h0)) node _io_resp_bits_target_T_35 = mux(_io_resp_bits_target_T_7, tgtPages[7], UInt<1>(0h0)) node _io_resp_bits_target_T_36 = mux(_io_resp_bits_target_T_8, tgtPages[8], UInt<1>(0h0)) node _io_resp_bits_target_T_37 = mux(_io_resp_bits_target_T_9, tgtPages[9], UInt<1>(0h0)) node _io_resp_bits_target_T_38 = mux(_io_resp_bits_target_T_10, tgtPages[10], UInt<1>(0h0)) node _io_resp_bits_target_T_39 = mux(_io_resp_bits_target_T_11, tgtPages[11], UInt<1>(0h0)) node _io_resp_bits_target_T_40 = mux(_io_resp_bits_target_T_12, tgtPages[12], UInt<1>(0h0)) node _io_resp_bits_target_T_41 = mux(_io_resp_bits_target_T_13, tgtPages[13], UInt<1>(0h0)) node _io_resp_bits_target_T_42 = mux(_io_resp_bits_target_T_14, tgtPages[14], UInt<1>(0h0)) node _io_resp_bits_target_T_43 = mux(_io_resp_bits_target_T_15, tgtPages[15], UInt<1>(0h0)) node _io_resp_bits_target_T_44 = mux(_io_resp_bits_target_T_16, tgtPages[16], UInt<1>(0h0)) node _io_resp_bits_target_T_45 = mux(_io_resp_bits_target_T_17, tgtPages[17], UInt<1>(0h0)) node _io_resp_bits_target_T_46 = mux(_io_resp_bits_target_T_18, tgtPages[18], UInt<1>(0h0)) node _io_resp_bits_target_T_47 = mux(_io_resp_bits_target_T_19, tgtPages[19], UInt<1>(0h0)) node _io_resp_bits_target_T_48 = mux(_io_resp_bits_target_T_20, tgtPages[20], UInt<1>(0h0)) node _io_resp_bits_target_T_49 = mux(_io_resp_bits_target_T_21, tgtPages[21], UInt<1>(0h0)) node _io_resp_bits_target_T_50 = mux(_io_resp_bits_target_T_22, tgtPages[22], UInt<1>(0h0)) node _io_resp_bits_target_T_51 = mux(_io_resp_bits_target_T_23, tgtPages[23], UInt<1>(0h0)) node _io_resp_bits_target_T_52 = mux(_io_resp_bits_target_T_24, tgtPages[24], UInt<1>(0h0)) node _io_resp_bits_target_T_53 = mux(_io_resp_bits_target_T_25, tgtPages[25], UInt<1>(0h0)) node _io_resp_bits_target_T_54 = mux(_io_resp_bits_target_T_26, tgtPages[26], UInt<1>(0h0)) node _io_resp_bits_target_T_55 = mux(_io_resp_bits_target_T_27, tgtPages[27], UInt<1>(0h0)) node _io_resp_bits_target_T_56 = or(_io_resp_bits_target_T_28, _io_resp_bits_target_T_29) node _io_resp_bits_target_T_57 = or(_io_resp_bits_target_T_56, _io_resp_bits_target_T_30) node _io_resp_bits_target_T_58 = or(_io_resp_bits_target_T_57, _io_resp_bits_target_T_31) node _io_resp_bits_target_T_59 = or(_io_resp_bits_target_T_58, _io_resp_bits_target_T_32) node _io_resp_bits_target_T_60 = or(_io_resp_bits_target_T_59, _io_resp_bits_target_T_33) node _io_resp_bits_target_T_61 = or(_io_resp_bits_target_T_60, _io_resp_bits_target_T_34) node _io_resp_bits_target_T_62 = or(_io_resp_bits_target_T_61, _io_resp_bits_target_T_35) node _io_resp_bits_target_T_63 = or(_io_resp_bits_target_T_62, _io_resp_bits_target_T_36) node _io_resp_bits_target_T_64 = or(_io_resp_bits_target_T_63, _io_resp_bits_target_T_37) node _io_resp_bits_target_T_65 = or(_io_resp_bits_target_T_64, _io_resp_bits_target_T_38) node _io_resp_bits_target_T_66 = or(_io_resp_bits_target_T_65, _io_resp_bits_target_T_39) node _io_resp_bits_target_T_67 = or(_io_resp_bits_target_T_66, _io_resp_bits_target_T_40) node _io_resp_bits_target_T_68 = or(_io_resp_bits_target_T_67, _io_resp_bits_target_T_41) node _io_resp_bits_target_T_69 = or(_io_resp_bits_target_T_68, _io_resp_bits_target_T_42) node _io_resp_bits_target_T_70 = or(_io_resp_bits_target_T_69, _io_resp_bits_target_T_43) node _io_resp_bits_target_T_71 = or(_io_resp_bits_target_T_70, _io_resp_bits_target_T_44) node _io_resp_bits_target_T_72 = or(_io_resp_bits_target_T_71, _io_resp_bits_target_T_45) node _io_resp_bits_target_T_73 = or(_io_resp_bits_target_T_72, _io_resp_bits_target_T_46) node _io_resp_bits_target_T_74 = or(_io_resp_bits_target_T_73, _io_resp_bits_target_T_47) node _io_resp_bits_target_T_75 = or(_io_resp_bits_target_T_74, _io_resp_bits_target_T_48) node _io_resp_bits_target_T_76 = or(_io_resp_bits_target_T_75, _io_resp_bits_target_T_49) node _io_resp_bits_target_T_77 = or(_io_resp_bits_target_T_76, _io_resp_bits_target_T_50) node _io_resp_bits_target_T_78 = or(_io_resp_bits_target_T_77, _io_resp_bits_target_T_51) node _io_resp_bits_target_T_79 = or(_io_resp_bits_target_T_78, _io_resp_bits_target_T_52) node _io_resp_bits_target_T_80 = or(_io_resp_bits_target_T_79, _io_resp_bits_target_T_53) node _io_resp_bits_target_T_81 = or(_io_resp_bits_target_T_80, _io_resp_bits_target_T_54) node _io_resp_bits_target_T_82 = or(_io_resp_bits_target_T_81, _io_resp_bits_target_T_55) wire _io_resp_bits_target_WIRE : UInt<3> connect _io_resp_bits_target_WIRE, _io_resp_bits_target_T_82 node _io_resp_bits_target_T_83 = eq(_io_resp_bits_target_WIRE, UInt<1>(0h1)) node _io_resp_bits_target_T_84 = mux(_io_resp_bits_target_T_83, pagesMasked_1, pagesMasked_0) node _io_resp_bits_target_T_85 = eq(_io_resp_bits_target_WIRE, UInt<2>(0h2)) node _io_resp_bits_target_T_86 = mux(_io_resp_bits_target_T_85, pagesMasked_2, _io_resp_bits_target_T_84) node _io_resp_bits_target_T_87 = eq(_io_resp_bits_target_WIRE, UInt<2>(0h3)) node _io_resp_bits_target_T_88 = mux(_io_resp_bits_target_T_87, pagesMasked_3, _io_resp_bits_target_T_86) node _io_resp_bits_target_T_89 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h4)) node _io_resp_bits_target_T_90 = mux(_io_resp_bits_target_T_89, pagesMasked_4, _io_resp_bits_target_T_88) node _io_resp_bits_target_T_91 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h5)) node _io_resp_bits_target_T_92 = mux(_io_resp_bits_target_T_91, pagesMasked_5, _io_resp_bits_target_T_90) node _io_resp_bits_target_T_93 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h6)) node _io_resp_bits_target_T_94 = mux(_io_resp_bits_target_T_93, pagesMasked_4, _io_resp_bits_target_T_92) node _io_resp_bits_target_T_95 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h7)) node _io_resp_bits_target_T_96 = mux(_io_resp_bits_target_T_95, pagesMasked_5, _io_resp_bits_target_T_94) node _io_resp_bits_target_T_97 = bits(idxHit, 0, 0) node _io_resp_bits_target_T_98 = bits(idxHit, 1, 1) node _io_resp_bits_target_T_99 = bits(idxHit, 2, 2) node _io_resp_bits_target_T_100 = bits(idxHit, 3, 3) node _io_resp_bits_target_T_101 = bits(idxHit, 4, 4) node _io_resp_bits_target_T_102 = bits(idxHit, 5, 5) node _io_resp_bits_target_T_103 = bits(idxHit, 6, 6) node _io_resp_bits_target_T_104 = bits(idxHit, 7, 7) node _io_resp_bits_target_T_105 = bits(idxHit, 8, 8) node _io_resp_bits_target_T_106 = bits(idxHit, 9, 9) node _io_resp_bits_target_T_107 = bits(idxHit, 10, 10) node _io_resp_bits_target_T_108 = bits(idxHit, 11, 11) node _io_resp_bits_target_T_109 = bits(idxHit, 12, 12) node _io_resp_bits_target_T_110 = bits(idxHit, 13, 13) node _io_resp_bits_target_T_111 = bits(idxHit, 14, 14) node _io_resp_bits_target_T_112 = bits(idxHit, 15, 15) node _io_resp_bits_target_T_113 = bits(idxHit, 16, 16) node _io_resp_bits_target_T_114 = bits(idxHit, 17, 17) node _io_resp_bits_target_T_115 = bits(idxHit, 18, 18) node _io_resp_bits_target_T_116 = bits(idxHit, 19, 19) node _io_resp_bits_target_T_117 = bits(idxHit, 20, 20) node _io_resp_bits_target_T_118 = bits(idxHit, 21, 21) node _io_resp_bits_target_T_119 = bits(idxHit, 22, 22) node _io_resp_bits_target_T_120 = bits(idxHit, 23, 23) node _io_resp_bits_target_T_121 = bits(idxHit, 24, 24) node _io_resp_bits_target_T_122 = bits(idxHit, 25, 25) node _io_resp_bits_target_T_123 = bits(idxHit, 26, 26) node _io_resp_bits_target_T_124 = bits(idxHit, 27, 27) node _io_resp_bits_target_T_125 = mux(_io_resp_bits_target_T_97, tgts[0], UInt<1>(0h0)) node _io_resp_bits_target_T_126 = mux(_io_resp_bits_target_T_98, tgts[1], UInt<1>(0h0)) node _io_resp_bits_target_T_127 = mux(_io_resp_bits_target_T_99, tgts[2], UInt<1>(0h0)) node _io_resp_bits_target_T_128 = mux(_io_resp_bits_target_T_100, tgts[3], UInt<1>(0h0)) node _io_resp_bits_target_T_129 = mux(_io_resp_bits_target_T_101, tgts[4], UInt<1>(0h0)) node _io_resp_bits_target_T_130 = mux(_io_resp_bits_target_T_102, tgts[5], UInt<1>(0h0)) node _io_resp_bits_target_T_131 = mux(_io_resp_bits_target_T_103, tgts[6], UInt<1>(0h0)) node _io_resp_bits_target_T_132 = mux(_io_resp_bits_target_T_104, tgts[7], UInt<1>(0h0)) node _io_resp_bits_target_T_133 = mux(_io_resp_bits_target_T_105, tgts[8], UInt<1>(0h0)) node _io_resp_bits_target_T_134 = mux(_io_resp_bits_target_T_106, tgts[9], UInt<1>(0h0)) node _io_resp_bits_target_T_135 = mux(_io_resp_bits_target_T_107, tgts[10], UInt<1>(0h0)) node _io_resp_bits_target_T_136 = mux(_io_resp_bits_target_T_108, tgts[11], UInt<1>(0h0)) node _io_resp_bits_target_T_137 = mux(_io_resp_bits_target_T_109, tgts[12], UInt<1>(0h0)) node _io_resp_bits_target_T_138 = mux(_io_resp_bits_target_T_110, tgts[13], UInt<1>(0h0)) node _io_resp_bits_target_T_139 = mux(_io_resp_bits_target_T_111, tgts[14], UInt<1>(0h0)) node _io_resp_bits_target_T_140 = mux(_io_resp_bits_target_T_112, tgts[15], UInt<1>(0h0)) node _io_resp_bits_target_T_141 = mux(_io_resp_bits_target_T_113, tgts[16], UInt<1>(0h0)) node _io_resp_bits_target_T_142 = mux(_io_resp_bits_target_T_114, tgts[17], UInt<1>(0h0)) node _io_resp_bits_target_T_143 = mux(_io_resp_bits_target_T_115, tgts[18], UInt<1>(0h0)) node _io_resp_bits_target_T_144 = mux(_io_resp_bits_target_T_116, tgts[19], UInt<1>(0h0)) node _io_resp_bits_target_T_145 = mux(_io_resp_bits_target_T_117, tgts[20], UInt<1>(0h0)) node _io_resp_bits_target_T_146 = mux(_io_resp_bits_target_T_118, tgts[21], UInt<1>(0h0)) node _io_resp_bits_target_T_147 = mux(_io_resp_bits_target_T_119, tgts[22], UInt<1>(0h0)) node _io_resp_bits_target_T_148 = mux(_io_resp_bits_target_T_120, tgts[23], UInt<1>(0h0)) node _io_resp_bits_target_T_149 = mux(_io_resp_bits_target_T_121, tgts[24], UInt<1>(0h0)) node _io_resp_bits_target_T_150 = mux(_io_resp_bits_target_T_122, tgts[25], UInt<1>(0h0)) node _io_resp_bits_target_T_151 = mux(_io_resp_bits_target_T_123, tgts[26], UInt<1>(0h0)) node _io_resp_bits_target_T_152 = mux(_io_resp_bits_target_T_124, tgts[27], UInt<1>(0h0)) node _io_resp_bits_target_T_153 = or(_io_resp_bits_target_T_125, _io_resp_bits_target_T_126) node _io_resp_bits_target_T_154 = or(_io_resp_bits_target_T_153, _io_resp_bits_target_T_127) node _io_resp_bits_target_T_155 = or(_io_resp_bits_target_T_154, _io_resp_bits_target_T_128) node _io_resp_bits_target_T_156 = or(_io_resp_bits_target_T_155, _io_resp_bits_target_T_129) node _io_resp_bits_target_T_157 = or(_io_resp_bits_target_T_156, _io_resp_bits_target_T_130) node _io_resp_bits_target_T_158 = or(_io_resp_bits_target_T_157, _io_resp_bits_target_T_131) node _io_resp_bits_target_T_159 = or(_io_resp_bits_target_T_158, _io_resp_bits_target_T_132) node _io_resp_bits_target_T_160 = or(_io_resp_bits_target_T_159, _io_resp_bits_target_T_133) node _io_resp_bits_target_T_161 = or(_io_resp_bits_target_T_160, _io_resp_bits_target_T_134) node _io_resp_bits_target_T_162 = or(_io_resp_bits_target_T_161, _io_resp_bits_target_T_135) node _io_resp_bits_target_T_163 = or(_io_resp_bits_target_T_162, _io_resp_bits_target_T_136) node _io_resp_bits_target_T_164 = or(_io_resp_bits_target_T_163, _io_resp_bits_target_T_137) node _io_resp_bits_target_T_165 = or(_io_resp_bits_target_T_164, _io_resp_bits_target_T_138) node _io_resp_bits_target_T_166 = or(_io_resp_bits_target_T_165, _io_resp_bits_target_T_139) node _io_resp_bits_target_T_167 = or(_io_resp_bits_target_T_166, _io_resp_bits_target_T_140) node _io_resp_bits_target_T_168 = or(_io_resp_bits_target_T_167, _io_resp_bits_target_T_141) node _io_resp_bits_target_T_169 = or(_io_resp_bits_target_T_168, _io_resp_bits_target_T_142) node _io_resp_bits_target_T_170 = or(_io_resp_bits_target_T_169, _io_resp_bits_target_T_143) node _io_resp_bits_target_T_171 = or(_io_resp_bits_target_T_170, _io_resp_bits_target_T_144) node _io_resp_bits_target_T_172 = or(_io_resp_bits_target_T_171, _io_resp_bits_target_T_145) node _io_resp_bits_target_T_173 = or(_io_resp_bits_target_T_172, _io_resp_bits_target_T_146) node _io_resp_bits_target_T_174 = or(_io_resp_bits_target_T_173, _io_resp_bits_target_T_147) node _io_resp_bits_target_T_175 = or(_io_resp_bits_target_T_174, _io_resp_bits_target_T_148) node _io_resp_bits_target_T_176 = or(_io_resp_bits_target_T_175, _io_resp_bits_target_T_149) node _io_resp_bits_target_T_177 = or(_io_resp_bits_target_T_176, _io_resp_bits_target_T_150) node _io_resp_bits_target_T_178 = or(_io_resp_bits_target_T_177, _io_resp_bits_target_T_151) node _io_resp_bits_target_T_179 = or(_io_resp_bits_target_T_178, _io_resp_bits_target_T_152) wire _io_resp_bits_target_WIRE_1 : UInt<13> connect _io_resp_bits_target_WIRE_1, _io_resp_bits_target_T_179 node _io_resp_bits_target_T_180 = shl(_io_resp_bits_target_WIRE_1, 1) node _io_resp_bits_target_T_181 = cat(_io_resp_bits_target_T_96, _io_resp_bits_target_T_180) connect io.resp.bits.target, _io_resp_bits_target_T_181 node io_resp_bits_entry_hi = bits(idxHit, 27, 16) node io_resp_bits_entry_lo = bits(idxHit, 15, 0) node _io_resp_bits_entry_T = orr(io_resp_bits_entry_hi) node _io_resp_bits_entry_T_1 = or(io_resp_bits_entry_hi, io_resp_bits_entry_lo) node io_resp_bits_entry_hi_1 = bits(_io_resp_bits_entry_T_1, 15, 8) node io_resp_bits_entry_lo_1 = bits(_io_resp_bits_entry_T_1, 7, 0) node _io_resp_bits_entry_T_2 = orr(io_resp_bits_entry_hi_1) node _io_resp_bits_entry_T_3 = or(io_resp_bits_entry_hi_1, io_resp_bits_entry_lo_1) node io_resp_bits_entry_hi_2 = bits(_io_resp_bits_entry_T_3, 7, 4) node io_resp_bits_entry_lo_2 = bits(_io_resp_bits_entry_T_3, 3, 0) node _io_resp_bits_entry_T_4 = orr(io_resp_bits_entry_hi_2) node _io_resp_bits_entry_T_5 = or(io_resp_bits_entry_hi_2, io_resp_bits_entry_lo_2) node io_resp_bits_entry_hi_3 = bits(_io_resp_bits_entry_T_5, 3, 2) node io_resp_bits_entry_lo_3 = bits(_io_resp_bits_entry_T_5, 1, 0) node _io_resp_bits_entry_T_6 = orr(io_resp_bits_entry_hi_3) node _io_resp_bits_entry_T_7 = or(io_resp_bits_entry_hi_3, io_resp_bits_entry_lo_3) node _io_resp_bits_entry_T_8 = bits(_io_resp_bits_entry_T_7, 1, 1) node _io_resp_bits_entry_T_9 = cat(_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8) node _io_resp_bits_entry_T_10 = cat(_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9) node _io_resp_bits_entry_T_11 = cat(_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10) node _io_resp_bits_entry_T_12 = cat(_io_resp_bits_entry_T, _io_resp_bits_entry_T_11) connect io.resp.bits.entry, _io_resp_bits_entry_T_12 node _io_resp_bits_bridx_T = bits(idxHit, 0, 0) node _io_resp_bits_bridx_T_1 = bits(idxHit, 1, 1) node _io_resp_bits_bridx_T_2 = bits(idxHit, 2, 2) node _io_resp_bits_bridx_T_3 = bits(idxHit, 3, 3) node _io_resp_bits_bridx_T_4 = bits(idxHit, 4, 4) node _io_resp_bits_bridx_T_5 = bits(idxHit, 5, 5) node _io_resp_bits_bridx_T_6 = bits(idxHit, 6, 6) node _io_resp_bits_bridx_T_7 = bits(idxHit, 7, 7) node _io_resp_bits_bridx_T_8 = bits(idxHit, 8, 8) node _io_resp_bits_bridx_T_9 = bits(idxHit, 9, 9) node _io_resp_bits_bridx_T_10 = bits(idxHit, 10, 10) node _io_resp_bits_bridx_T_11 = bits(idxHit, 11, 11) node _io_resp_bits_bridx_T_12 = bits(idxHit, 12, 12) node _io_resp_bits_bridx_T_13 = bits(idxHit, 13, 13) node _io_resp_bits_bridx_T_14 = bits(idxHit, 14, 14) node _io_resp_bits_bridx_T_15 = bits(idxHit, 15, 15) node _io_resp_bits_bridx_T_16 = bits(idxHit, 16, 16) node _io_resp_bits_bridx_T_17 = bits(idxHit, 17, 17) node _io_resp_bits_bridx_T_18 = bits(idxHit, 18, 18) node _io_resp_bits_bridx_T_19 = bits(idxHit, 19, 19) node _io_resp_bits_bridx_T_20 = bits(idxHit, 20, 20) node _io_resp_bits_bridx_T_21 = bits(idxHit, 21, 21) node _io_resp_bits_bridx_T_22 = bits(idxHit, 22, 22) node _io_resp_bits_bridx_T_23 = bits(idxHit, 23, 23) node _io_resp_bits_bridx_T_24 = bits(idxHit, 24, 24) node _io_resp_bits_bridx_T_25 = bits(idxHit, 25, 25) node _io_resp_bits_bridx_T_26 = bits(idxHit, 26, 26) node _io_resp_bits_bridx_T_27 = bits(idxHit, 27, 27) node _io_resp_bits_bridx_T_28 = mux(_io_resp_bits_bridx_T, brIdx[0], UInt<1>(0h0)) node _io_resp_bits_bridx_T_29 = mux(_io_resp_bits_bridx_T_1, brIdx[1], UInt<1>(0h0)) node _io_resp_bits_bridx_T_30 = mux(_io_resp_bits_bridx_T_2, brIdx[2], UInt<1>(0h0)) node _io_resp_bits_bridx_T_31 = mux(_io_resp_bits_bridx_T_3, brIdx[3], UInt<1>(0h0)) node _io_resp_bits_bridx_T_32 = mux(_io_resp_bits_bridx_T_4, brIdx[4], UInt<1>(0h0)) node _io_resp_bits_bridx_T_33 = mux(_io_resp_bits_bridx_T_5, brIdx[5], UInt<1>(0h0)) node _io_resp_bits_bridx_T_34 = mux(_io_resp_bits_bridx_T_6, brIdx[6], UInt<1>(0h0)) node _io_resp_bits_bridx_T_35 = mux(_io_resp_bits_bridx_T_7, brIdx[7], UInt<1>(0h0)) node _io_resp_bits_bridx_T_36 = mux(_io_resp_bits_bridx_T_8, brIdx[8], UInt<1>(0h0)) node _io_resp_bits_bridx_T_37 = mux(_io_resp_bits_bridx_T_9, brIdx[9], UInt<1>(0h0)) node _io_resp_bits_bridx_T_38 = mux(_io_resp_bits_bridx_T_10, brIdx[10], UInt<1>(0h0)) node _io_resp_bits_bridx_T_39 = mux(_io_resp_bits_bridx_T_11, brIdx[11], UInt<1>(0h0)) node _io_resp_bits_bridx_T_40 = mux(_io_resp_bits_bridx_T_12, brIdx[12], UInt<1>(0h0)) node _io_resp_bits_bridx_T_41 = mux(_io_resp_bits_bridx_T_13, brIdx[13], UInt<1>(0h0)) node _io_resp_bits_bridx_T_42 = mux(_io_resp_bits_bridx_T_14, brIdx[14], UInt<1>(0h0)) node _io_resp_bits_bridx_T_43 = mux(_io_resp_bits_bridx_T_15, brIdx[15], UInt<1>(0h0)) node _io_resp_bits_bridx_T_44 = mux(_io_resp_bits_bridx_T_16, brIdx[16], UInt<1>(0h0)) node _io_resp_bits_bridx_T_45 = mux(_io_resp_bits_bridx_T_17, brIdx[17], UInt<1>(0h0)) node _io_resp_bits_bridx_T_46 = mux(_io_resp_bits_bridx_T_18, brIdx[18], UInt<1>(0h0)) node _io_resp_bits_bridx_T_47 = mux(_io_resp_bits_bridx_T_19, brIdx[19], UInt<1>(0h0)) node _io_resp_bits_bridx_T_48 = mux(_io_resp_bits_bridx_T_20, brIdx[20], UInt<1>(0h0)) node _io_resp_bits_bridx_T_49 = mux(_io_resp_bits_bridx_T_21, brIdx[21], UInt<1>(0h0)) node _io_resp_bits_bridx_T_50 = mux(_io_resp_bits_bridx_T_22, brIdx[22], UInt<1>(0h0)) node _io_resp_bits_bridx_T_51 = mux(_io_resp_bits_bridx_T_23, brIdx[23], UInt<1>(0h0)) node _io_resp_bits_bridx_T_52 = mux(_io_resp_bits_bridx_T_24, brIdx[24], UInt<1>(0h0)) node _io_resp_bits_bridx_T_53 = mux(_io_resp_bits_bridx_T_25, brIdx[25], UInt<1>(0h0)) node _io_resp_bits_bridx_T_54 = mux(_io_resp_bits_bridx_T_26, brIdx[26], UInt<1>(0h0)) node _io_resp_bits_bridx_T_55 = mux(_io_resp_bits_bridx_T_27, brIdx[27], UInt<1>(0h0)) node _io_resp_bits_bridx_T_56 = or(_io_resp_bits_bridx_T_28, _io_resp_bits_bridx_T_29) node _io_resp_bits_bridx_T_57 = or(_io_resp_bits_bridx_T_56, _io_resp_bits_bridx_T_30) node _io_resp_bits_bridx_T_58 = or(_io_resp_bits_bridx_T_57, _io_resp_bits_bridx_T_31) node _io_resp_bits_bridx_T_59 = or(_io_resp_bits_bridx_T_58, _io_resp_bits_bridx_T_32) node _io_resp_bits_bridx_T_60 = or(_io_resp_bits_bridx_T_59, _io_resp_bits_bridx_T_33) node _io_resp_bits_bridx_T_61 = or(_io_resp_bits_bridx_T_60, _io_resp_bits_bridx_T_34) node _io_resp_bits_bridx_T_62 = or(_io_resp_bits_bridx_T_61, _io_resp_bits_bridx_T_35) node _io_resp_bits_bridx_T_63 = or(_io_resp_bits_bridx_T_62, _io_resp_bits_bridx_T_36) node _io_resp_bits_bridx_T_64 = or(_io_resp_bits_bridx_T_63, _io_resp_bits_bridx_T_37) node _io_resp_bits_bridx_T_65 = or(_io_resp_bits_bridx_T_64, _io_resp_bits_bridx_T_38) node _io_resp_bits_bridx_T_66 = or(_io_resp_bits_bridx_T_65, _io_resp_bits_bridx_T_39) node _io_resp_bits_bridx_T_67 = or(_io_resp_bits_bridx_T_66, _io_resp_bits_bridx_T_40) node _io_resp_bits_bridx_T_68 = or(_io_resp_bits_bridx_T_67, _io_resp_bits_bridx_T_41) node _io_resp_bits_bridx_T_69 = or(_io_resp_bits_bridx_T_68, _io_resp_bits_bridx_T_42) node _io_resp_bits_bridx_T_70 = or(_io_resp_bits_bridx_T_69, _io_resp_bits_bridx_T_43) node _io_resp_bits_bridx_T_71 = or(_io_resp_bits_bridx_T_70, _io_resp_bits_bridx_T_44) node _io_resp_bits_bridx_T_72 = or(_io_resp_bits_bridx_T_71, _io_resp_bits_bridx_T_45) node _io_resp_bits_bridx_T_73 = or(_io_resp_bits_bridx_T_72, _io_resp_bits_bridx_T_46) node _io_resp_bits_bridx_T_74 = or(_io_resp_bits_bridx_T_73, _io_resp_bits_bridx_T_47) node _io_resp_bits_bridx_T_75 = or(_io_resp_bits_bridx_T_74, _io_resp_bits_bridx_T_48) node _io_resp_bits_bridx_T_76 = or(_io_resp_bits_bridx_T_75, _io_resp_bits_bridx_T_49) node _io_resp_bits_bridx_T_77 = or(_io_resp_bits_bridx_T_76, _io_resp_bits_bridx_T_50) node _io_resp_bits_bridx_T_78 = or(_io_resp_bits_bridx_T_77, _io_resp_bits_bridx_T_51) node _io_resp_bits_bridx_T_79 = or(_io_resp_bits_bridx_T_78, _io_resp_bits_bridx_T_52) node _io_resp_bits_bridx_T_80 = or(_io_resp_bits_bridx_T_79, _io_resp_bits_bridx_T_53) node _io_resp_bits_bridx_T_81 = or(_io_resp_bits_bridx_T_80, _io_resp_bits_bridx_T_54) node _io_resp_bits_bridx_T_82 = or(_io_resp_bits_bridx_T_81, _io_resp_bits_bridx_T_55) wire _io_resp_bits_bridx_WIRE : UInt<1> connect _io_resp_bits_bridx_WIRE, _io_resp_bits_bridx_T_82 connect io.resp.bits.bridx, _io_resp_bits_bridx_WIRE node _io_resp_bits_mask_T = not(io.resp.bits.bridx) node _io_resp_bits_mask_T_1 = mux(io.resp.bits.taken, _io_resp_bits_mask_T, UInt<1>(0h0)) node _io_resp_bits_mask_T_2 = not(_io_resp_bits_mask_T_1) node _io_resp_bits_mask_T_3 = dshl(UInt<1>(0h1), _io_resp_bits_mask_T_2) node _io_resp_bits_mask_T_4 = sub(_io_resp_bits_mask_T_3, UInt<1>(0h1)) node _io_resp_bits_mask_T_5 = tail(_io_resp_bits_mask_T_4, 1) node _io_resp_bits_mask_T_6 = cat(_io_resp_bits_mask_T_5, UInt<1>(0h1)) connect io.resp.bits.mask, _io_resp_bits_mask_T_6 node _io_resp_bits_cfiType_T = bits(idxHit, 0, 0) node _io_resp_bits_cfiType_T_1 = bits(idxHit, 1, 1) node _io_resp_bits_cfiType_T_2 = bits(idxHit, 2, 2) node _io_resp_bits_cfiType_T_3 = bits(idxHit, 3, 3) node _io_resp_bits_cfiType_T_4 = bits(idxHit, 4, 4) node _io_resp_bits_cfiType_T_5 = bits(idxHit, 5, 5) node _io_resp_bits_cfiType_T_6 = bits(idxHit, 6, 6) node _io_resp_bits_cfiType_T_7 = bits(idxHit, 7, 7) node _io_resp_bits_cfiType_T_8 = bits(idxHit, 8, 8) node _io_resp_bits_cfiType_T_9 = bits(idxHit, 9, 9) node _io_resp_bits_cfiType_T_10 = bits(idxHit, 10, 10) node _io_resp_bits_cfiType_T_11 = bits(idxHit, 11, 11) node _io_resp_bits_cfiType_T_12 = bits(idxHit, 12, 12) node _io_resp_bits_cfiType_T_13 = bits(idxHit, 13, 13) node _io_resp_bits_cfiType_T_14 = bits(idxHit, 14, 14) node _io_resp_bits_cfiType_T_15 = bits(idxHit, 15, 15) node _io_resp_bits_cfiType_T_16 = bits(idxHit, 16, 16) node _io_resp_bits_cfiType_T_17 = bits(idxHit, 17, 17) node _io_resp_bits_cfiType_T_18 = bits(idxHit, 18, 18) node _io_resp_bits_cfiType_T_19 = bits(idxHit, 19, 19) node _io_resp_bits_cfiType_T_20 = bits(idxHit, 20, 20) node _io_resp_bits_cfiType_T_21 = bits(idxHit, 21, 21) node _io_resp_bits_cfiType_T_22 = bits(idxHit, 22, 22) node _io_resp_bits_cfiType_T_23 = bits(idxHit, 23, 23) node _io_resp_bits_cfiType_T_24 = bits(idxHit, 24, 24) node _io_resp_bits_cfiType_T_25 = bits(idxHit, 25, 25) node _io_resp_bits_cfiType_T_26 = bits(idxHit, 26, 26) node _io_resp_bits_cfiType_T_27 = bits(idxHit, 27, 27) node _io_resp_bits_cfiType_T_28 = mux(_io_resp_bits_cfiType_T, cfiType[0], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_29 = mux(_io_resp_bits_cfiType_T_1, cfiType[1], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_30 = mux(_io_resp_bits_cfiType_T_2, cfiType[2], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_31 = mux(_io_resp_bits_cfiType_T_3, cfiType[3], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_32 = mux(_io_resp_bits_cfiType_T_4, cfiType[4], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_33 = mux(_io_resp_bits_cfiType_T_5, cfiType[5], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_34 = mux(_io_resp_bits_cfiType_T_6, cfiType[6], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_35 = mux(_io_resp_bits_cfiType_T_7, cfiType[7], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_36 = mux(_io_resp_bits_cfiType_T_8, cfiType[8], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_37 = mux(_io_resp_bits_cfiType_T_9, cfiType[9], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_38 = mux(_io_resp_bits_cfiType_T_10, cfiType[10], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_39 = mux(_io_resp_bits_cfiType_T_11, cfiType[11], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_40 = mux(_io_resp_bits_cfiType_T_12, cfiType[12], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_41 = mux(_io_resp_bits_cfiType_T_13, cfiType[13], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_42 = mux(_io_resp_bits_cfiType_T_14, cfiType[14], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_43 = mux(_io_resp_bits_cfiType_T_15, cfiType[15], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_44 = mux(_io_resp_bits_cfiType_T_16, cfiType[16], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_45 = mux(_io_resp_bits_cfiType_T_17, cfiType[17], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_46 = mux(_io_resp_bits_cfiType_T_18, cfiType[18], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_47 = mux(_io_resp_bits_cfiType_T_19, cfiType[19], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_48 = mux(_io_resp_bits_cfiType_T_20, cfiType[20], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_49 = mux(_io_resp_bits_cfiType_T_21, cfiType[21], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_50 = mux(_io_resp_bits_cfiType_T_22, cfiType[22], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_51 = mux(_io_resp_bits_cfiType_T_23, cfiType[23], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_52 = mux(_io_resp_bits_cfiType_T_24, cfiType[24], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_53 = mux(_io_resp_bits_cfiType_T_25, cfiType[25], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_54 = mux(_io_resp_bits_cfiType_T_26, cfiType[26], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_55 = mux(_io_resp_bits_cfiType_T_27, cfiType[27], UInt<1>(0h0)) node _io_resp_bits_cfiType_T_56 = or(_io_resp_bits_cfiType_T_28, _io_resp_bits_cfiType_T_29) node _io_resp_bits_cfiType_T_57 = or(_io_resp_bits_cfiType_T_56, _io_resp_bits_cfiType_T_30) node _io_resp_bits_cfiType_T_58 = or(_io_resp_bits_cfiType_T_57, _io_resp_bits_cfiType_T_31) node _io_resp_bits_cfiType_T_59 = or(_io_resp_bits_cfiType_T_58, _io_resp_bits_cfiType_T_32) node _io_resp_bits_cfiType_T_60 = or(_io_resp_bits_cfiType_T_59, _io_resp_bits_cfiType_T_33) node _io_resp_bits_cfiType_T_61 = or(_io_resp_bits_cfiType_T_60, _io_resp_bits_cfiType_T_34) node _io_resp_bits_cfiType_T_62 = or(_io_resp_bits_cfiType_T_61, _io_resp_bits_cfiType_T_35) node _io_resp_bits_cfiType_T_63 = or(_io_resp_bits_cfiType_T_62, _io_resp_bits_cfiType_T_36) node _io_resp_bits_cfiType_T_64 = or(_io_resp_bits_cfiType_T_63, _io_resp_bits_cfiType_T_37) node _io_resp_bits_cfiType_T_65 = or(_io_resp_bits_cfiType_T_64, _io_resp_bits_cfiType_T_38) node _io_resp_bits_cfiType_T_66 = or(_io_resp_bits_cfiType_T_65, _io_resp_bits_cfiType_T_39) node _io_resp_bits_cfiType_T_67 = or(_io_resp_bits_cfiType_T_66, _io_resp_bits_cfiType_T_40) node _io_resp_bits_cfiType_T_68 = or(_io_resp_bits_cfiType_T_67, _io_resp_bits_cfiType_T_41) node _io_resp_bits_cfiType_T_69 = or(_io_resp_bits_cfiType_T_68, _io_resp_bits_cfiType_T_42) node _io_resp_bits_cfiType_T_70 = or(_io_resp_bits_cfiType_T_69, _io_resp_bits_cfiType_T_43) node _io_resp_bits_cfiType_T_71 = or(_io_resp_bits_cfiType_T_70, _io_resp_bits_cfiType_T_44) node _io_resp_bits_cfiType_T_72 = or(_io_resp_bits_cfiType_T_71, _io_resp_bits_cfiType_T_45) node _io_resp_bits_cfiType_T_73 = or(_io_resp_bits_cfiType_T_72, _io_resp_bits_cfiType_T_46) node _io_resp_bits_cfiType_T_74 = or(_io_resp_bits_cfiType_T_73, _io_resp_bits_cfiType_T_47) node _io_resp_bits_cfiType_T_75 = or(_io_resp_bits_cfiType_T_74, _io_resp_bits_cfiType_T_48) node _io_resp_bits_cfiType_T_76 = or(_io_resp_bits_cfiType_T_75, _io_resp_bits_cfiType_T_49) node _io_resp_bits_cfiType_T_77 = or(_io_resp_bits_cfiType_T_76, _io_resp_bits_cfiType_T_50) node _io_resp_bits_cfiType_T_78 = or(_io_resp_bits_cfiType_T_77, _io_resp_bits_cfiType_T_51) node _io_resp_bits_cfiType_T_79 = or(_io_resp_bits_cfiType_T_78, _io_resp_bits_cfiType_T_52) node _io_resp_bits_cfiType_T_80 = or(_io_resp_bits_cfiType_T_79, _io_resp_bits_cfiType_T_53) node _io_resp_bits_cfiType_T_81 = or(_io_resp_bits_cfiType_T_80, _io_resp_bits_cfiType_T_54) node _io_resp_bits_cfiType_T_82 = or(_io_resp_bits_cfiType_T_81, _io_resp_bits_cfiType_T_55) wire _io_resp_bits_cfiType_WIRE : UInt<2> connect _io_resp_bits_cfiType_WIRE, _io_resp_bits_cfiType_T_82 connect io.resp.bits.cfiType, _io_resp_bits_cfiType_WIRE node _T_19 = bits(idxHit, 13, 0) node _T_20 = bits(_T_19, 6, 0) node _T_21 = bits(_T_20, 2, 0) node _T_22 = bits(_T_21, 0, 0) node leftOne = bits(_T_22, 0, 0) node _T_23 = bits(_T_21, 2, 1) node _T_24 = bits(_T_23, 0, 0) node leftOne_1 = bits(_T_24, 0, 0) node _T_25 = bits(_T_23, 1, 1) node rightOne = bits(_T_25, 0, 0) node rightOne_1 = or(leftOne_1, rightOne) node _T_26 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_27 = and(leftOne_1, rightOne) node rightTwo = or(_T_26, _T_27) node leftOne_2 = or(leftOne, rightOne_1) node _T_28 = or(UInt<1>(0h0), rightTwo) node _T_29 = and(leftOne, rightOne_1) node leftTwo = or(_T_28, _T_29) node _T_30 = bits(_T_20, 6, 3) node _T_31 = bits(_T_30, 1, 0) node _T_32 = bits(_T_31, 0, 0) node leftOne_3 = bits(_T_32, 0, 0) node _T_33 = bits(_T_31, 1, 1) node rightOne_2 = bits(_T_33, 0, 0) node leftOne_4 = or(leftOne_3, rightOne_2) node _T_34 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_35 = and(leftOne_3, rightOne_2) node leftTwo_1 = or(_T_34, _T_35) node _T_36 = bits(_T_30, 3, 2) node _T_37 = bits(_T_36, 0, 0) node leftOne_5 = bits(_T_37, 0, 0) node _T_38 = bits(_T_36, 1, 1) node rightOne_3 = bits(_T_38, 0, 0) node rightOne_4 = or(leftOne_5, rightOne_3) node _T_39 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_40 = and(leftOne_5, rightOne_3) node rightTwo_1 = or(_T_39, _T_40) node rightOne_5 = or(leftOne_4, rightOne_4) node _T_41 = or(leftTwo_1, rightTwo_1) node _T_42 = and(leftOne_4, rightOne_4) node rightTwo_2 = or(_T_41, _T_42) node leftOne_6 = or(leftOne_2, rightOne_5) node _T_43 = or(leftTwo, rightTwo_2) node _T_44 = and(leftOne_2, rightOne_5) node leftTwo_2 = or(_T_43, _T_44) node _T_45 = bits(_T_19, 13, 7) node _T_46 = bits(_T_45, 2, 0) node _T_47 = bits(_T_46, 0, 0) node leftOne_7 = bits(_T_47, 0, 0) node _T_48 = bits(_T_46, 2, 1) node _T_49 = bits(_T_48, 0, 0) node leftOne_8 = bits(_T_49, 0, 0) node _T_50 = bits(_T_48, 1, 1) node rightOne_6 = bits(_T_50, 0, 0) node rightOne_7 = or(leftOne_8, rightOne_6) node _T_51 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_52 = and(leftOne_8, rightOne_6) node rightTwo_3 = or(_T_51, _T_52) node leftOne_9 = or(leftOne_7, rightOne_7) node _T_53 = or(UInt<1>(0h0), rightTwo_3) node _T_54 = and(leftOne_7, rightOne_7) node leftTwo_3 = or(_T_53, _T_54) node _T_55 = bits(_T_45, 6, 3) node _T_56 = bits(_T_55, 1, 0) node _T_57 = bits(_T_56, 0, 0) node leftOne_10 = bits(_T_57, 0, 0) node _T_58 = bits(_T_56, 1, 1) node rightOne_8 = bits(_T_58, 0, 0) node leftOne_11 = or(leftOne_10, rightOne_8) node _T_59 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_60 = and(leftOne_10, rightOne_8) node leftTwo_4 = or(_T_59, _T_60) node _T_61 = bits(_T_55, 3, 2) node _T_62 = bits(_T_61, 0, 0) node leftOne_12 = bits(_T_62, 0, 0) node _T_63 = bits(_T_61, 1, 1) node rightOne_9 = bits(_T_63, 0, 0) node rightOne_10 = or(leftOne_12, rightOne_9) node _T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_65 = and(leftOne_12, rightOne_9) node rightTwo_4 = or(_T_64, _T_65) node rightOne_11 = or(leftOne_11, rightOne_10) node _T_66 = or(leftTwo_4, rightTwo_4) node _T_67 = and(leftOne_11, rightOne_10) node rightTwo_5 = or(_T_66, _T_67) node rightOne_12 = or(leftOne_9, rightOne_11) node _T_68 = or(leftTwo_3, rightTwo_5) node _T_69 = and(leftOne_9, rightOne_11) node rightTwo_6 = or(_T_68, _T_69) node leftOne_13 = or(leftOne_6, rightOne_12) node _T_70 = or(leftTwo_2, rightTwo_6) node _T_71 = and(leftOne_6, rightOne_12) node leftTwo_5 = or(_T_70, _T_71) node _T_72 = bits(idxHit, 27, 14) node _T_73 = bits(_T_72, 6, 0) node _T_74 = bits(_T_73, 2, 0) node _T_75 = bits(_T_74, 0, 0) node leftOne_14 = bits(_T_75, 0, 0) node _T_76 = bits(_T_74, 2, 1) node _T_77 = bits(_T_76, 0, 0) node leftOne_15 = bits(_T_77, 0, 0) node _T_78 = bits(_T_76, 1, 1) node rightOne_13 = bits(_T_78, 0, 0) node rightOne_14 = or(leftOne_15, rightOne_13) node _T_79 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_80 = and(leftOne_15, rightOne_13) node rightTwo_7 = or(_T_79, _T_80) node leftOne_16 = or(leftOne_14, rightOne_14) node _T_81 = or(UInt<1>(0h0), rightTwo_7) node _T_82 = and(leftOne_14, rightOne_14) node leftTwo_6 = or(_T_81, _T_82) node _T_83 = bits(_T_73, 6, 3) node _T_84 = bits(_T_83, 1, 0) node _T_85 = bits(_T_84, 0, 0) node leftOne_17 = bits(_T_85, 0, 0) node _T_86 = bits(_T_84, 1, 1) node rightOne_15 = bits(_T_86, 0, 0) node leftOne_18 = or(leftOne_17, rightOne_15) node _T_87 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_88 = and(leftOne_17, rightOne_15) node leftTwo_7 = or(_T_87, _T_88) node _T_89 = bits(_T_83, 3, 2) node _T_90 = bits(_T_89, 0, 0) node leftOne_19 = bits(_T_90, 0, 0) node _T_91 = bits(_T_89, 1, 1) node rightOne_16 = bits(_T_91, 0, 0) node rightOne_17 = or(leftOne_19, rightOne_16) node _T_92 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_93 = and(leftOne_19, rightOne_16) node rightTwo_8 = or(_T_92, _T_93) node rightOne_18 = or(leftOne_18, rightOne_17) node _T_94 = or(leftTwo_7, rightTwo_8) node _T_95 = and(leftOne_18, rightOne_17) node rightTwo_9 = or(_T_94, _T_95) node leftOne_20 = or(leftOne_16, rightOne_18) node _T_96 = or(leftTwo_6, rightTwo_9) node _T_97 = and(leftOne_16, rightOne_18) node leftTwo_8 = or(_T_96, _T_97) node _T_98 = bits(_T_72, 13, 7) node _T_99 = bits(_T_98, 2, 0) node _T_100 = bits(_T_99, 0, 0) node leftOne_21 = bits(_T_100, 0, 0) node _T_101 = bits(_T_99, 2, 1) node _T_102 = bits(_T_101, 0, 0) node leftOne_22 = bits(_T_102, 0, 0) node _T_103 = bits(_T_101, 1, 1) node rightOne_19 = bits(_T_103, 0, 0) node rightOne_20 = or(leftOne_22, rightOne_19) node _T_104 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_105 = and(leftOne_22, rightOne_19) node rightTwo_10 = or(_T_104, _T_105) node leftOne_23 = or(leftOne_21, rightOne_20) node _T_106 = or(UInt<1>(0h0), rightTwo_10) node _T_107 = and(leftOne_21, rightOne_20) node leftTwo_9 = or(_T_106, _T_107) node _T_108 = bits(_T_98, 6, 3) node _T_109 = bits(_T_108, 1, 0) node _T_110 = bits(_T_109, 0, 0) node leftOne_24 = bits(_T_110, 0, 0) node _T_111 = bits(_T_109, 1, 1) node rightOne_21 = bits(_T_111, 0, 0) node leftOne_25 = or(leftOne_24, rightOne_21) node _T_112 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_113 = and(leftOne_24, rightOne_21) node leftTwo_10 = or(_T_112, _T_113) node _T_114 = bits(_T_108, 3, 2) node _T_115 = bits(_T_114, 0, 0) node leftOne_26 = bits(_T_115, 0, 0) node _T_116 = bits(_T_114, 1, 1) node rightOne_22 = bits(_T_116, 0, 0) node rightOne_23 = or(leftOne_26, rightOne_22) node _T_117 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_118 = and(leftOne_26, rightOne_22) node rightTwo_11 = or(_T_117, _T_118) node rightOne_24 = or(leftOne_25, rightOne_23) node _T_119 = or(leftTwo_10, rightTwo_11) node _T_120 = and(leftOne_25, rightOne_23) node rightTwo_12 = or(_T_119, _T_120) node rightOne_25 = or(leftOne_23, rightOne_24) node _T_121 = or(leftTwo_9, rightTwo_12) node _T_122 = and(leftOne_23, rightOne_24) node rightTwo_13 = or(_T_121, _T_122) node rightOne_26 = or(leftOne_20, rightOne_25) node _T_123 = or(leftTwo_8, rightTwo_13) node _T_124 = and(leftOne_20, rightOne_25) node rightTwo_14 = or(_T_123, _T_124) node _T_125 = or(leftOne_13, rightOne_26) node _T_126 = or(leftTwo_5, rightTwo_14) node _T_127 = and(leftOne_13, rightOne_26) node _T_128 = or(_T_126, _T_127) when _T_128 : node _isValid_T_4 = not(idxHit) node _isValid_T_5 = and(isValid, _isValid_T_4) connect isValid, _isValid_T_5 when io.flush : connect isValid, UInt<1>(0h0) cmem table : UInt<1> [512] regreset history : UInt<8>, clock, reset, UInt<8>(0h0) regreset reset_waddr : UInt<10>, clock, reset, UInt<10>(0h0) node _resetting_T = bits(reset_waddr, 9, 9) node resetting = eq(_resetting_T, UInt<1>(0h0)) wire wen : UInt<1> connect wen, resetting wire waddr_1 : UInt connect waddr_1, reset_waddr wire wdata : UInt connect wdata, UInt<1>(0h0) when resetting : node _reset_waddr_T = add(reset_waddr, UInt<1>(0h1)) node _reset_waddr_T_1 = tail(_reset_waddr_T, 1) connect reset_waddr, _reset_waddr_T_1 when wen : node _T_129 = or(waddr_1, UInt<9>(0h0)) node _T_130 = bits(_T_129, 8, 0) infer mport MPORT = table[_T_130], clock connect MPORT, wdata node _isBranch_T = eq(cfiType[0], UInt<1>(0h0)) node _isBranch_T_1 = eq(cfiType[1], UInt<1>(0h0)) node _isBranch_T_2 = eq(cfiType[2], UInt<1>(0h0)) node _isBranch_T_3 = eq(cfiType[3], UInt<1>(0h0)) node _isBranch_T_4 = eq(cfiType[4], UInt<1>(0h0)) node _isBranch_T_5 = eq(cfiType[5], UInt<1>(0h0)) node _isBranch_T_6 = eq(cfiType[6], UInt<1>(0h0)) node _isBranch_T_7 = eq(cfiType[7], UInt<1>(0h0)) node _isBranch_T_8 = eq(cfiType[8], UInt<1>(0h0)) node _isBranch_T_9 = eq(cfiType[9], UInt<1>(0h0)) node _isBranch_T_10 = eq(cfiType[10], UInt<1>(0h0)) node _isBranch_T_11 = eq(cfiType[11], UInt<1>(0h0)) node _isBranch_T_12 = eq(cfiType[12], UInt<1>(0h0)) node _isBranch_T_13 = eq(cfiType[13], UInt<1>(0h0)) node _isBranch_T_14 = eq(cfiType[14], UInt<1>(0h0)) node _isBranch_T_15 = eq(cfiType[15], UInt<1>(0h0)) node _isBranch_T_16 = eq(cfiType[16], UInt<1>(0h0)) node _isBranch_T_17 = eq(cfiType[17], UInt<1>(0h0)) node _isBranch_T_18 = eq(cfiType[18], UInt<1>(0h0)) node _isBranch_T_19 = eq(cfiType[19], UInt<1>(0h0)) node _isBranch_T_20 = eq(cfiType[20], UInt<1>(0h0)) node _isBranch_T_21 = eq(cfiType[21], UInt<1>(0h0)) node _isBranch_T_22 = eq(cfiType[22], UInt<1>(0h0)) node _isBranch_T_23 = eq(cfiType[23], UInt<1>(0h0)) node _isBranch_T_24 = eq(cfiType[24], UInt<1>(0h0)) node _isBranch_T_25 = eq(cfiType[25], UInt<1>(0h0)) node _isBranch_T_26 = eq(cfiType[26], UInt<1>(0h0)) node _isBranch_T_27 = eq(cfiType[27], UInt<1>(0h0)) node isBranch_lo_lo_lo_hi = cat(_isBranch_T_2, _isBranch_T_1) node isBranch_lo_lo_lo = cat(isBranch_lo_lo_lo_hi, _isBranch_T) node isBranch_lo_lo_hi_lo = cat(_isBranch_T_4, _isBranch_T_3) node isBranch_lo_lo_hi_hi = cat(_isBranch_T_6, _isBranch_T_5) node isBranch_lo_lo_hi = cat(isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo) node isBranch_lo_lo = cat(isBranch_lo_lo_hi, isBranch_lo_lo_lo) node isBranch_lo_hi_lo_hi = cat(_isBranch_T_9, _isBranch_T_8) node isBranch_lo_hi_lo = cat(isBranch_lo_hi_lo_hi, _isBranch_T_7) node isBranch_lo_hi_hi_lo = cat(_isBranch_T_11, _isBranch_T_10) node isBranch_lo_hi_hi_hi = cat(_isBranch_T_13, _isBranch_T_12) node isBranch_lo_hi_hi = cat(isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo) node isBranch_lo_hi = cat(isBranch_lo_hi_hi, isBranch_lo_hi_lo) node isBranch_lo = cat(isBranch_lo_hi, isBranch_lo_lo) node isBranch_hi_lo_lo_hi = cat(_isBranch_T_16, _isBranch_T_15) node isBranch_hi_lo_lo = cat(isBranch_hi_lo_lo_hi, _isBranch_T_14) node isBranch_hi_lo_hi_lo = cat(_isBranch_T_18, _isBranch_T_17) node isBranch_hi_lo_hi_hi = cat(_isBranch_T_20, _isBranch_T_19) node isBranch_hi_lo_hi = cat(isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo) node isBranch_hi_lo = cat(isBranch_hi_lo_hi, isBranch_hi_lo_lo) node isBranch_hi_hi_lo_hi = cat(_isBranch_T_23, _isBranch_T_22) node isBranch_hi_hi_lo = cat(isBranch_hi_hi_lo_hi, _isBranch_T_21) node isBranch_hi_hi_hi_lo = cat(_isBranch_T_25, _isBranch_T_24) node isBranch_hi_hi_hi_hi = cat(_isBranch_T_27, _isBranch_T_26) node isBranch_hi_hi_hi = cat(isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo) node isBranch_hi_hi = cat(isBranch_hi_hi_hi, isBranch_hi_hi_lo) node isBranch_hi = cat(isBranch_hi_hi, isBranch_hi_lo) node _isBranch_T_28 = cat(isBranch_hi, isBranch_lo) node _isBranch_T_29 = and(idxHit, _isBranch_T_28) node isBranch = orr(_isBranch_T_29) wire res : { history : UInt<8>, value : UInt<1>} node res_res_value_hi = shr(io.req.bits.addr, 2) node _res_res_value_T = bits(res_res_value_hi, 8, 0) node _res_res_value_T_1 = shr(res_res_value_hi, 9) node _res_res_value_T_2 = bits(_res_res_value_T_1, 1, 0) node _res_res_value_T_3 = xor(_res_res_value_T, _res_res_value_T_2) node _res_res_value_T_4 = mul(UInt<8>(0hdd), history) node _res_res_value_T_5 = bits(_res_res_value_T_4, 7, 5) node _res_res_value_T_6 = shl(_res_res_value_T_5, 6) node _res_res_value_T_7 = xor(_res_res_value_T_3, _res_res_value_T_6) infer mport res_res_value_MPORT = table[_res_res_value_T_7], clock node _res_res_value_T_8 = mux(resetting, UInt<1>(0h0), res_res_value_MPORT) connect res.value, _res_res_value_T_8 connect res.history, history when io.bht_advance.valid : node _T_131 = bits(io.bht_advance.bits.bht.value, 0, 0) node _history_T = shr(history, 1) node _history_T_1 = cat(_T_131, _history_T) connect history, _history_T_1 when io.bht_update.valid : when io.bht_update.bits.branch : connect wen, UInt<1>(0h1) node _T_132 = eq(resetting, UInt<1>(0h0)) when _T_132 : node waddr_hi = shr(io.bht_update.bits.pc, 2) node _waddr_T_40 = bits(waddr_hi, 8, 0) node _waddr_T_41 = shr(waddr_hi, 9) node _waddr_T_42 = bits(_waddr_T_41, 1, 0) node _waddr_T_43 = xor(_waddr_T_40, _waddr_T_42) node _waddr_T_44 = mul(UInt<8>(0hdd), io.bht_update.bits.prediction.history) node _waddr_T_45 = bits(_waddr_T_44, 7, 5) node _waddr_T_46 = shl(_waddr_T_45, 6) node _waddr_T_47 = xor(_waddr_T_43, _waddr_T_46) connect waddr_1, _waddr_T_47 connect wdata, io.bht_update.bits.taken when io.bht_update.bits.mispredict : node _history_T_2 = shr(io.bht_update.bits.prediction.history, 1) node _history_T_3 = cat(io.bht_update.bits.taken, _history_T_2) connect history, _history_T_3 else : when io.bht_update.bits.mispredict : connect history, io.bht_update.bits.prediction.history node _T_133 = bits(res.value, 0, 0) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = and(_T_134, isBranch) when _T_135 : connect io.resp.bits.taken, UInt<1>(0h0) connect io.resp.bits.bht, res regreset count : UInt<3>, clock, reset, UInt<3>(0h0) regreset pos : UInt<3>, clock, reset, UInt<3>(0h0) reg stack : UInt[6], clock node _doPeek_T = eq(cfiType[0], UInt<2>(0h3)) node _doPeek_T_1 = eq(cfiType[1], UInt<2>(0h3)) node _doPeek_T_2 = eq(cfiType[2], UInt<2>(0h3)) node _doPeek_T_3 = eq(cfiType[3], UInt<2>(0h3)) node _doPeek_T_4 = eq(cfiType[4], UInt<2>(0h3)) node _doPeek_T_5 = eq(cfiType[5], UInt<2>(0h3)) node _doPeek_T_6 = eq(cfiType[6], UInt<2>(0h3)) node _doPeek_T_7 = eq(cfiType[7], UInt<2>(0h3)) node _doPeek_T_8 = eq(cfiType[8], UInt<2>(0h3)) node _doPeek_T_9 = eq(cfiType[9], UInt<2>(0h3)) node _doPeek_T_10 = eq(cfiType[10], UInt<2>(0h3)) node _doPeek_T_11 = eq(cfiType[11], UInt<2>(0h3)) node _doPeek_T_12 = eq(cfiType[12], UInt<2>(0h3)) node _doPeek_T_13 = eq(cfiType[13], UInt<2>(0h3)) node _doPeek_T_14 = eq(cfiType[14], UInt<2>(0h3)) node _doPeek_T_15 = eq(cfiType[15], UInt<2>(0h3)) node _doPeek_T_16 = eq(cfiType[16], UInt<2>(0h3)) node _doPeek_T_17 = eq(cfiType[17], UInt<2>(0h3)) node _doPeek_T_18 = eq(cfiType[18], UInt<2>(0h3)) node _doPeek_T_19 = eq(cfiType[19], UInt<2>(0h3)) node _doPeek_T_20 = eq(cfiType[20], UInt<2>(0h3)) node _doPeek_T_21 = eq(cfiType[21], UInt<2>(0h3)) node _doPeek_T_22 = eq(cfiType[22], UInt<2>(0h3)) node _doPeek_T_23 = eq(cfiType[23], UInt<2>(0h3)) node _doPeek_T_24 = eq(cfiType[24], UInt<2>(0h3)) node _doPeek_T_25 = eq(cfiType[25], UInt<2>(0h3)) node _doPeek_T_26 = eq(cfiType[26], UInt<2>(0h3)) node _doPeek_T_27 = eq(cfiType[27], UInt<2>(0h3)) node doPeek_lo_lo_lo_hi = cat(_doPeek_T_2, _doPeek_T_1) node doPeek_lo_lo_lo = cat(doPeek_lo_lo_lo_hi, _doPeek_T) node doPeek_lo_lo_hi_lo = cat(_doPeek_T_4, _doPeek_T_3) node doPeek_lo_lo_hi_hi = cat(_doPeek_T_6, _doPeek_T_5) node doPeek_lo_lo_hi = cat(doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo) node doPeek_lo_lo = cat(doPeek_lo_lo_hi, doPeek_lo_lo_lo) node doPeek_lo_hi_lo_hi = cat(_doPeek_T_9, _doPeek_T_8) node doPeek_lo_hi_lo = cat(doPeek_lo_hi_lo_hi, _doPeek_T_7) node doPeek_lo_hi_hi_lo = cat(_doPeek_T_11, _doPeek_T_10) node doPeek_lo_hi_hi_hi = cat(_doPeek_T_13, _doPeek_T_12) node doPeek_lo_hi_hi = cat(doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo) node doPeek_lo_hi = cat(doPeek_lo_hi_hi, doPeek_lo_hi_lo) node doPeek_lo = cat(doPeek_lo_hi, doPeek_lo_lo) node doPeek_hi_lo_lo_hi = cat(_doPeek_T_16, _doPeek_T_15) node doPeek_hi_lo_lo = cat(doPeek_hi_lo_lo_hi, _doPeek_T_14) node doPeek_hi_lo_hi_lo = cat(_doPeek_T_18, _doPeek_T_17) node doPeek_hi_lo_hi_hi = cat(_doPeek_T_20, _doPeek_T_19) node doPeek_hi_lo_hi = cat(doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo) node doPeek_hi_lo = cat(doPeek_hi_lo_hi, doPeek_hi_lo_lo) node doPeek_hi_hi_lo_hi = cat(_doPeek_T_23, _doPeek_T_22) node doPeek_hi_hi_lo = cat(doPeek_hi_hi_lo_hi, _doPeek_T_21) node doPeek_hi_hi_hi_lo = cat(_doPeek_T_25, _doPeek_T_24) node doPeek_hi_hi_hi_hi = cat(_doPeek_T_27, _doPeek_T_26) node doPeek_hi_hi_hi = cat(doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo) node doPeek_hi_hi = cat(doPeek_hi_hi_hi, doPeek_hi_hi_lo) node doPeek_hi = cat(doPeek_hi_hi, doPeek_hi_lo) node _doPeek_T_28 = cat(doPeek_hi, doPeek_lo) node _doPeek_T_29 = and(idxHit, _doPeek_T_28) node doPeek = orr(_doPeek_T_29) node _io_ras_head_valid_T = eq(count, UInt<1>(0h0)) node _io_ras_head_valid_T_1 = eq(_io_ras_head_valid_T, UInt<1>(0h0)) connect io.ras_head.valid, _io_ras_head_valid_T_1 connect io.ras_head.bits, stack[pos] node _T_136 = eq(count, UInt<1>(0h0)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = and(_T_137, doPeek) when _T_138 : connect io.resp.bits.target, stack[pos] when io.ras_update.valid : node _T_139 = eq(io.ras_update.bits.cfiType, UInt<2>(0h2)) when _T_139 : node _T_140 = lt(count, UInt<3>(0h6)) when _T_140 : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 node _nextPos_T = lt(pos, UInt<3>(0h5)) node _nextPos_T_1 = or(UInt<1>(0h0), _nextPos_T) node _nextPos_T_2 = add(pos, UInt<1>(0h1)) node _nextPos_T_3 = tail(_nextPos_T_2, 1) node nextPos = mux(_nextPos_T_1, _nextPos_T_3, UInt<1>(0h0)) connect stack[nextPos], io.ras_update.bits.returnAddr connect pos, nextPos else : node _T_141 = eq(io.ras_update.bits.cfiType, UInt<2>(0h3)) when _T_141 : node _T_142 = eq(count, UInt<1>(0h0)) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _count_T_2 = sub(count, UInt<1>(0h1)) node _count_T_3 = tail(_count_T_2, 1) connect count, _count_T_3 node _pos_T = gt(pos, UInt<1>(0h0)) node _pos_T_1 = or(UInt<1>(0h0), _pos_T) node _pos_T_2 = sub(pos, UInt<1>(0h1)) node _pos_T_3 = tail(_pos_T_2, 1) node _pos_T_4 = mux(_pos_T_1, _pos_T_3, UInt<3>(0h5)) connect pos, _pos_T_4
module BTB( // @[BTB.scala:187:7] input clock, // @[BTB.scala:187:7] input reset, // @[BTB.scala:187:7] input io_req_valid, // @[BTB.scala:188:14] input [47:0] io_req_bits_addr, // @[BTB.scala:188:14] output io_resp_valid, // @[BTB.scala:188:14] output [1:0] io_resp_bits_cfiType, // @[BTB.scala:188:14] output io_resp_bits_taken, // @[BTB.scala:188:14] output [1:0] io_resp_bits_mask, // @[BTB.scala:188:14] output io_resp_bits_bridx, // @[BTB.scala:188:14] output [47:0] io_resp_bits_target, // @[BTB.scala:188:14] output [4:0] io_resp_bits_entry, // @[BTB.scala:188:14] output [7:0] io_resp_bits_bht_history, // @[BTB.scala:188:14] output io_resp_bits_bht_value, // @[BTB.scala:188:14] input io_btb_update_valid, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_cfiType, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_taken, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_mask, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bridx, // @[BTB.scala:188:14] input [47:0] io_btb_update_bits_prediction_target, // @[BTB.scala:188:14] input [4:0] io_btb_update_bits_prediction_entry, // @[BTB.scala:188:14] input [7:0] io_btb_update_bits_prediction_bht_history, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bht_value, // @[BTB.scala:188:14] input [47:0] io_btb_update_bits_pc, // @[BTB.scala:188:14] input [47:0] io_btb_update_bits_target, // @[BTB.scala:188:14] input io_btb_update_bits_isValid, // @[BTB.scala:188:14] input [47:0] io_btb_update_bits_br_pc, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_cfiType, // @[BTB.scala:188:14] input io_bht_update_valid, // @[BTB.scala:188:14] input [7:0] io_bht_update_bits_prediction_history, // @[BTB.scala:188:14] input io_bht_update_bits_prediction_value, // @[BTB.scala:188:14] input [47:0] io_bht_update_bits_pc, // @[BTB.scala:188:14] input io_bht_update_bits_branch, // @[BTB.scala:188:14] input io_bht_update_bits_taken, // @[BTB.scala:188:14] input io_bht_update_bits_mispredict, // @[BTB.scala:188:14] input io_bht_advance_valid, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_cfiType, // @[BTB.scala:188:14] input io_bht_advance_bits_taken, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_mask, // @[BTB.scala:188:14] input io_bht_advance_bits_bridx, // @[BTB.scala:188:14] input [47:0] io_bht_advance_bits_target, // @[BTB.scala:188:14] input [4:0] io_bht_advance_bits_entry, // @[BTB.scala:188:14] input [7:0] io_bht_advance_bits_bht_history, // @[BTB.scala:188:14] input io_bht_advance_bits_bht_value, // @[BTB.scala:188:14] input io_ras_update_valid, // @[BTB.scala:188:14] input [1:0] io_ras_update_bits_cfiType, // @[BTB.scala:188:14] input [47:0] io_ras_update_bits_returnAddr, // @[BTB.scala:188:14] output io_ras_head_valid, // @[BTB.scala:188:14] output [47:0] io_ras_head_bits, // @[BTB.scala:188:14] input io_flush // @[BTB.scala:188:14] ); wire _table_ext_R0_data; // @[BTB.scala:116:26] wire io_req_valid_0 = io_req_valid; // @[BTB.scala:187:7] wire [47:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BTB.scala:187:7] wire io_btb_update_valid_0 = io_btb_update_valid; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_cfiType_0 = io_btb_update_bits_prediction_cfiType; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_taken_0 = io_btb_update_bits_prediction_taken; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_mask_0 = io_btb_update_bits_prediction_mask; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bridx_0 = io_btb_update_bits_prediction_bridx; // @[BTB.scala:187:7] wire [47:0] io_btb_update_bits_prediction_target_0 = io_btb_update_bits_prediction_target; // @[BTB.scala:187:7] wire [4:0] io_btb_update_bits_prediction_entry_0 = io_btb_update_bits_prediction_entry; // @[BTB.scala:187:7] wire [7:0] io_btb_update_bits_prediction_bht_history_0 = io_btb_update_bits_prediction_bht_history; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bht_value_0 = io_btb_update_bits_prediction_bht_value; // @[BTB.scala:187:7] wire [47:0] io_btb_update_bits_pc_0 = io_btb_update_bits_pc; // @[BTB.scala:187:7] wire [47:0] io_btb_update_bits_target_0 = io_btb_update_bits_target; // @[BTB.scala:187:7] wire io_btb_update_bits_isValid_0 = io_btb_update_bits_isValid; // @[BTB.scala:187:7] wire [47:0] io_btb_update_bits_br_pc_0 = io_btb_update_bits_br_pc; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_cfiType_0 = io_btb_update_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_update_valid_0 = io_bht_update_valid; // @[BTB.scala:187:7] wire [7:0] io_bht_update_bits_prediction_history_0 = io_bht_update_bits_prediction_history; // @[BTB.scala:187:7] wire io_bht_update_bits_prediction_value_0 = io_bht_update_bits_prediction_value; // @[BTB.scala:187:7] wire [47:0] io_bht_update_bits_pc_0 = io_bht_update_bits_pc; // @[BTB.scala:187:7] wire io_bht_update_bits_branch_0 = io_bht_update_bits_branch; // @[BTB.scala:187:7] wire io_bht_update_bits_taken_0 = io_bht_update_bits_taken; // @[BTB.scala:187:7] wire io_bht_update_bits_mispredict_0 = io_bht_update_bits_mispredict; // @[BTB.scala:187:7] wire io_bht_advance_valid_0 = io_bht_advance_valid; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_cfiType_0 = io_bht_advance_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_advance_bits_taken_0 = io_bht_advance_bits_taken; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_mask_0 = io_bht_advance_bits_mask; // @[BTB.scala:187:7] wire io_bht_advance_bits_bridx_0 = io_bht_advance_bits_bridx; // @[BTB.scala:187:7] wire [47:0] io_bht_advance_bits_target_0 = io_bht_advance_bits_target; // @[BTB.scala:187:7] wire [4:0] io_bht_advance_bits_entry_0 = io_bht_advance_bits_entry; // @[BTB.scala:187:7] wire [7:0] io_bht_advance_bits_bht_history_0 = io_bht_advance_bits_bht_history; // @[BTB.scala:187:7] wire io_bht_advance_bits_bht_value_0 = io_bht_advance_bits_bht_value; // @[BTB.scala:187:7] wire io_ras_update_valid_0 = io_ras_update_valid; // @[BTB.scala:187:7] wire [1:0] io_ras_update_bits_cfiType_0 = io_ras_update_bits_cfiType; // @[BTB.scala:187:7] wire [47:0] io_ras_update_bits_returnAddr_0 = io_ras_update_bits_returnAddr; // @[BTB.scala:187:7] wire io_flush_0 = io_flush; // @[BTB.scala:187:7] wire io_btb_update_bits_taken = 1'h0; // @[BTB.scala:187:7] wire r_btb_update_bits_taken = 1'h0; // @[Valid.scala:135:21] wire _io_resp_valid_T_85; // @[BTB.scala:287:34] wire [1:0] _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire [4:0] _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire [7:0] res_history; // @[BTB.scala:91:19] wire res_value; // @[BTB.scala:91:19] wire _io_ras_head_valid_T_1; // @[BTB.scala:327:26] wire [7:0] io_resp_bits_bht_history_0; // @[BTB.scala:187:7] wire io_resp_bits_bht_value_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_cfiType_0; // @[BTB.scala:187:7] wire io_resp_bits_taken_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_mask_0; // @[BTB.scala:187:7] wire io_resp_bits_bridx_0; // @[BTB.scala:187:7] wire [47:0] io_resp_bits_target_0; // @[BTB.scala:187:7] wire [4:0] io_resp_bits_entry_0; // @[BTB.scala:187:7] wire io_resp_valid_0; // @[BTB.scala:187:7] wire io_ras_head_valid_0; // @[BTB.scala:187:7] wire [47:0] io_ras_head_bits_0; // @[BTB.scala:187:7] reg [12:0] idxs_0; // @[BTB.scala:199:17] reg [12:0] idxs_1; // @[BTB.scala:199:17] reg [12:0] idxs_2; // @[BTB.scala:199:17] reg [12:0] idxs_3; // @[BTB.scala:199:17] reg [12:0] idxs_4; // @[BTB.scala:199:17] reg [12:0] idxs_5; // @[BTB.scala:199:17] reg [12:0] idxs_6; // @[BTB.scala:199:17] reg [12:0] idxs_7; // @[BTB.scala:199:17] reg [12:0] idxs_8; // @[BTB.scala:199:17] reg [12:0] idxs_9; // @[BTB.scala:199:17] reg [12:0] idxs_10; // @[BTB.scala:199:17] reg [12:0] idxs_11; // @[BTB.scala:199:17] reg [12:0] idxs_12; // @[BTB.scala:199:17] reg [12:0] idxs_13; // @[BTB.scala:199:17] reg [12:0] idxs_14; // @[BTB.scala:199:17] reg [12:0] idxs_15; // @[BTB.scala:199:17] reg [12:0] idxs_16; // @[BTB.scala:199:17] reg [12:0] idxs_17; // @[BTB.scala:199:17] reg [12:0] idxs_18; // @[BTB.scala:199:17] reg [12:0] idxs_19; // @[BTB.scala:199:17] reg [12:0] idxs_20; // @[BTB.scala:199:17] reg [12:0] idxs_21; // @[BTB.scala:199:17] reg [12:0] idxs_22; // @[BTB.scala:199:17] reg [12:0] idxs_23; // @[BTB.scala:199:17] reg [12:0] idxs_24; // @[BTB.scala:199:17] reg [12:0] idxs_25; // @[BTB.scala:199:17] reg [12:0] idxs_26; // @[BTB.scala:199:17] reg [12:0] idxs_27; // @[BTB.scala:199:17] reg [2:0] idxPages_0; // @[BTB.scala:200:21] reg [2:0] idxPages_1; // @[BTB.scala:200:21] reg [2:0] idxPages_2; // @[BTB.scala:200:21] reg [2:0] idxPages_3; // @[BTB.scala:200:21] reg [2:0] idxPages_4; // @[BTB.scala:200:21] reg [2:0] idxPages_5; // @[BTB.scala:200:21] reg [2:0] idxPages_6; // @[BTB.scala:200:21] reg [2:0] idxPages_7; // @[BTB.scala:200:21] reg [2:0] idxPages_8; // @[BTB.scala:200:21] reg [2:0] idxPages_9; // @[BTB.scala:200:21] reg [2:0] idxPages_10; // @[BTB.scala:200:21] reg [2:0] idxPages_11; // @[BTB.scala:200:21] reg [2:0] idxPages_12; // @[BTB.scala:200:21] reg [2:0] idxPages_13; // @[BTB.scala:200:21] reg [2:0] idxPages_14; // @[BTB.scala:200:21] reg [2:0] idxPages_15; // @[BTB.scala:200:21] reg [2:0] idxPages_16; // @[BTB.scala:200:21] reg [2:0] idxPages_17; // @[BTB.scala:200:21] reg [2:0] idxPages_18; // @[BTB.scala:200:21] reg [2:0] idxPages_19; // @[BTB.scala:200:21] reg [2:0] idxPages_20; // @[BTB.scala:200:21] reg [2:0] idxPages_21; // @[BTB.scala:200:21] reg [2:0] idxPages_22; // @[BTB.scala:200:21] reg [2:0] idxPages_23; // @[BTB.scala:200:21] reg [2:0] idxPages_24; // @[BTB.scala:200:21] reg [2:0] idxPages_25; // @[BTB.scala:200:21] reg [2:0] idxPages_26; // @[BTB.scala:200:21] reg [2:0] idxPages_27; // @[BTB.scala:200:21] reg [12:0] tgts_0; // @[BTB.scala:201:17] reg [12:0] tgts_1; // @[BTB.scala:201:17] reg [12:0] tgts_2; // @[BTB.scala:201:17] reg [12:0] tgts_3; // @[BTB.scala:201:17] reg [12:0] tgts_4; // @[BTB.scala:201:17] reg [12:0] tgts_5; // @[BTB.scala:201:17] reg [12:0] tgts_6; // @[BTB.scala:201:17] reg [12:0] tgts_7; // @[BTB.scala:201:17] reg [12:0] tgts_8; // @[BTB.scala:201:17] reg [12:0] tgts_9; // @[BTB.scala:201:17] reg [12:0] tgts_10; // @[BTB.scala:201:17] reg [12:0] tgts_11; // @[BTB.scala:201:17] reg [12:0] tgts_12; // @[BTB.scala:201:17] reg [12:0] tgts_13; // @[BTB.scala:201:17] reg [12:0] tgts_14; // @[BTB.scala:201:17] reg [12:0] tgts_15; // @[BTB.scala:201:17] reg [12:0] tgts_16; // @[BTB.scala:201:17] reg [12:0] tgts_17; // @[BTB.scala:201:17] reg [12:0] tgts_18; // @[BTB.scala:201:17] reg [12:0] tgts_19; // @[BTB.scala:201:17] reg [12:0] tgts_20; // @[BTB.scala:201:17] reg [12:0] tgts_21; // @[BTB.scala:201:17] reg [12:0] tgts_22; // @[BTB.scala:201:17] reg [12:0] tgts_23; // @[BTB.scala:201:17] reg [12:0] tgts_24; // @[BTB.scala:201:17] reg [12:0] tgts_25; // @[BTB.scala:201:17] reg [12:0] tgts_26; // @[BTB.scala:201:17] reg [12:0] tgts_27; // @[BTB.scala:201:17] reg [2:0] tgtPages_0; // @[BTB.scala:202:21] reg [2:0] tgtPages_1; // @[BTB.scala:202:21] reg [2:0] tgtPages_2; // @[BTB.scala:202:21] reg [2:0] tgtPages_3; // @[BTB.scala:202:21] reg [2:0] tgtPages_4; // @[BTB.scala:202:21] reg [2:0] tgtPages_5; // @[BTB.scala:202:21] reg [2:0] tgtPages_6; // @[BTB.scala:202:21] reg [2:0] tgtPages_7; // @[BTB.scala:202:21] reg [2:0] tgtPages_8; // @[BTB.scala:202:21] reg [2:0] tgtPages_9; // @[BTB.scala:202:21] reg [2:0] tgtPages_10; // @[BTB.scala:202:21] reg [2:0] tgtPages_11; // @[BTB.scala:202:21] reg [2:0] tgtPages_12; // @[BTB.scala:202:21] reg [2:0] tgtPages_13; // @[BTB.scala:202:21] reg [2:0] tgtPages_14; // @[BTB.scala:202:21] reg [2:0] tgtPages_15; // @[BTB.scala:202:21] reg [2:0] tgtPages_16; // @[BTB.scala:202:21] reg [2:0] tgtPages_17; // @[BTB.scala:202:21] reg [2:0] tgtPages_18; // @[BTB.scala:202:21] reg [2:0] tgtPages_19; // @[BTB.scala:202:21] reg [2:0] tgtPages_20; // @[BTB.scala:202:21] reg [2:0] tgtPages_21; // @[BTB.scala:202:21] reg [2:0] tgtPages_22; // @[BTB.scala:202:21] reg [2:0] tgtPages_23; // @[BTB.scala:202:21] reg [2:0] tgtPages_24; // @[BTB.scala:202:21] reg [2:0] tgtPages_25; // @[BTB.scala:202:21] reg [2:0] tgtPages_26; // @[BTB.scala:202:21] reg [2:0] tgtPages_27; // @[BTB.scala:202:21] reg [33:0] pages_0; // @[BTB.scala:203:18] reg [33:0] pages_1; // @[BTB.scala:203:18] reg [33:0] pages_2; // @[BTB.scala:203:18] reg [33:0] pages_3; // @[BTB.scala:203:18] reg [33:0] pages_4; // @[BTB.scala:203:18] reg [33:0] pages_5; // @[BTB.scala:203:18] reg [5:0] pageValid; // @[BTB.scala:204:26] wire _pagesMasked_T = pageValid[0]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_1 = pageValid[1]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_2 = pageValid[2]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_3 = pageValid[3]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_4 = pageValid[4]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_5 = pageValid[5]; // @[BTB.scala:204:26, :205:32] wire [33:0] pagesMasked_0 = _pagesMasked_T ? pages_0 : 34'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [33:0] pagesMasked_1 = _pagesMasked_T_1 ? pages_1 : 34'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [33:0] pagesMasked_2 = _pagesMasked_T_2 ? pages_2 : 34'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [33:0] pagesMasked_3 = _pagesMasked_T_3 ? pages_3 : 34'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [33:0] pagesMasked_4 = _pagesMasked_T_4 ? pages_4 : 34'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [33:0] pagesMasked_5 = _pagesMasked_T_5 ? pages_5 : 34'h0; // @[BTB.scala:203:18, :205:{32,75}] reg [27:0] isValid; // @[BTB.scala:207:24] reg [1:0] cfiType_0; // @[BTB.scala:208:20] reg [1:0] cfiType_1; // @[BTB.scala:208:20] reg [1:0] cfiType_2; // @[BTB.scala:208:20] reg [1:0] cfiType_3; // @[BTB.scala:208:20] reg [1:0] cfiType_4; // @[BTB.scala:208:20] reg [1:0] cfiType_5; // @[BTB.scala:208:20] reg [1:0] cfiType_6; // @[BTB.scala:208:20] reg [1:0] cfiType_7; // @[BTB.scala:208:20] reg [1:0] cfiType_8; // @[BTB.scala:208:20] reg [1:0] cfiType_9; // @[BTB.scala:208:20] reg [1:0] cfiType_10; // @[BTB.scala:208:20] reg [1:0] cfiType_11; // @[BTB.scala:208:20] reg [1:0] cfiType_12; // @[BTB.scala:208:20] reg [1:0] cfiType_13; // @[BTB.scala:208:20] reg [1:0] cfiType_14; // @[BTB.scala:208:20] reg [1:0] cfiType_15; // @[BTB.scala:208:20] reg [1:0] cfiType_16; // @[BTB.scala:208:20] reg [1:0] cfiType_17; // @[BTB.scala:208:20] reg [1:0] cfiType_18; // @[BTB.scala:208:20] reg [1:0] cfiType_19; // @[BTB.scala:208:20] reg [1:0] cfiType_20; // @[BTB.scala:208:20] reg [1:0] cfiType_21; // @[BTB.scala:208:20] reg [1:0] cfiType_22; // @[BTB.scala:208:20] reg [1:0] cfiType_23; // @[BTB.scala:208:20] reg [1:0] cfiType_24; // @[BTB.scala:208:20] reg [1:0] cfiType_25; // @[BTB.scala:208:20] reg [1:0] cfiType_26; // @[BTB.scala:208:20] reg [1:0] cfiType_27; // @[BTB.scala:208:20] reg brIdx_0; // @[BTB.scala:209:18] reg brIdx_1; // @[BTB.scala:209:18] reg brIdx_2; // @[BTB.scala:209:18] reg brIdx_3; // @[BTB.scala:209:18] reg brIdx_4; // @[BTB.scala:209:18] reg brIdx_5; // @[BTB.scala:209:18] reg brIdx_6; // @[BTB.scala:209:18] reg brIdx_7; // @[BTB.scala:209:18] reg brIdx_8; // @[BTB.scala:209:18] reg brIdx_9; // @[BTB.scala:209:18] reg brIdx_10; // @[BTB.scala:209:18] reg brIdx_11; // @[BTB.scala:209:18] reg brIdx_12; // @[BTB.scala:209:18] reg brIdx_13; // @[BTB.scala:209:18] reg brIdx_14; // @[BTB.scala:209:18] reg brIdx_15; // @[BTB.scala:209:18] reg brIdx_16; // @[BTB.scala:209:18] reg brIdx_17; // @[BTB.scala:209:18] reg brIdx_18; // @[BTB.scala:209:18] reg brIdx_19; // @[BTB.scala:209:18] reg brIdx_20; // @[BTB.scala:209:18] reg brIdx_21; // @[BTB.scala:209:18] reg brIdx_22; // @[BTB.scala:209:18] reg brIdx_23; // @[BTB.scala:209:18] reg brIdx_24; // @[BTB.scala:209:18] reg brIdx_25; // @[BTB.scala:209:18] reg brIdx_26; // @[BTB.scala:209:18] reg brIdx_27; // @[BTB.scala:209:18] reg r_btb_update_pipe_v; // @[Valid.scala:141:24] wire r_btb_update_valid = r_btb_update_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_cfiType = r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_taken = r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_mask = r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bridx = r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:135:21, :142:26] reg [47:0] r_btb_update_pipe_b_prediction_target; // @[Valid.scala:142:26] wire [47:0] r_btb_update_bits_prediction_target = r_btb_update_pipe_b_prediction_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:142:26] wire [4:0] r_btb_update_bits_prediction_entry = r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:142:26] wire [7:0] r_btb_update_bits_prediction_bht_history = r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bht_value = r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:135:21, :142:26] reg [47:0] r_btb_update_pipe_b_pc; // @[Valid.scala:142:26] wire [47:0] r_btb_update_bits_pc = r_btb_update_pipe_b_pc; // @[Valid.scala:135:21, :142:26] reg [47:0] r_btb_update_pipe_b_target; // @[Valid.scala:142:26] wire [47:0] r_btb_update_bits_target = r_btb_update_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_isValid; // @[Valid.scala:142:26] wire r_btb_update_bits_isValid = r_btb_update_pipe_b_isValid; // @[Valid.scala:135:21, :142:26] reg [47:0] r_btb_update_pipe_b_br_pc; // @[Valid.scala:142:26] wire [47:0] r_btb_update_bits_br_pc = r_btb_update_pipe_b_br_pc; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_cfiType = r_btb_update_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] wire [33:0] pageHit_p = io_req_bits_addr_0[47:14]; // @[BTB.scala:187:7, :211:39] wire [33:0] _samePage_T_1 = io_req_bits_addr_0[47:14]; // @[BTB.scala:187:7, :211:39] wire _pageHit_T = pages_0 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_1 = pages_1 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_2 = pages_2 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_3 = pages_3 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_4 = pages_4 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_5 = pages_5 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] pageHit_lo_hi = {_pageHit_T_2, _pageHit_T_1}; // @[package.scala:45:27] wire [2:0] pageHit_lo = {pageHit_lo_hi, _pageHit_T}; // @[package.scala:45:27] wire [1:0] pageHit_hi_hi = {_pageHit_T_5, _pageHit_T_4}; // @[package.scala:45:27] wire [2:0] pageHit_hi = {pageHit_hi_hi, _pageHit_T_3}; // @[package.scala:45:27] wire [5:0] _pageHit_T_6 = {pageHit_hi, pageHit_lo}; // @[package.scala:45:27] wire [5:0] pageHit = pageValid & _pageHit_T_6; // @[package.scala:45:27] wire [12:0] idxHit_idx = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19] wire [12:0] _tgts_T = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19, :265:33] wire _idxHit_T = idxs_0 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_1 = idxs_1 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_2 = idxs_2 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_3 = idxs_3 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_4 = idxs_4 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_5 = idxs_5 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_6 = idxs_6 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_7 = idxs_7 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_8 = idxs_8 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_9 = idxs_9 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_10 = idxs_10 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_11 = idxs_11 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_12 = idxs_12 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_13 = idxs_13 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_14 = idxs_14 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_15 = idxs_15 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_16 = idxs_16 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_17 = idxs_17 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_18 = idxs_18 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_19 = idxs_19 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_20 = idxs_20 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_21 = idxs_21 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_22 = idxs_22 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_23 = idxs_23 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_24 = idxs_24 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_25 = idxs_25 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_26 = idxs_26 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_27 = idxs_27 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire [1:0] idxHit_lo_lo_lo_hi = {_idxHit_T_2, _idxHit_T_1}; // @[package.scala:45:27] wire [2:0] idxHit_lo_lo_lo = {idxHit_lo_lo_lo_hi, _idxHit_T}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_lo = {_idxHit_T_4, _idxHit_T_3}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_hi = {_idxHit_T_6, _idxHit_T_5}; // @[package.scala:45:27] wire [3:0] idxHit_lo_lo_hi = {idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_lo = {idxHit_lo_lo_hi, idxHit_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_lo_hi = {_idxHit_T_9, _idxHit_T_8}; // @[package.scala:45:27] wire [2:0] idxHit_lo_hi_lo = {idxHit_lo_hi_lo_hi, _idxHit_T_7}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_lo = {_idxHit_T_11, _idxHit_T_10}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_hi = {_idxHit_T_13, _idxHit_T_12}; // @[package.scala:45:27] wire [3:0] idxHit_lo_hi_hi = {idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_hi = {idxHit_lo_hi_hi, idxHit_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_lo = {idxHit_lo_hi, idxHit_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_lo_hi = {_idxHit_T_16, _idxHit_T_15}; // @[package.scala:45:27] wire [2:0] idxHit_hi_lo_lo = {idxHit_hi_lo_lo_hi, _idxHit_T_14}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_lo = {_idxHit_T_18, _idxHit_T_17}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_hi = {_idxHit_T_20, _idxHit_T_19}; // @[package.scala:45:27] wire [3:0] idxHit_hi_lo_hi = {idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_lo = {idxHit_hi_lo_hi, idxHit_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_lo_hi = {_idxHit_T_23, _idxHit_T_22}; // @[package.scala:45:27] wire [2:0] idxHit_hi_hi_lo = {idxHit_hi_hi_lo_hi, _idxHit_T_21}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_lo = {_idxHit_T_25, _idxHit_T_24}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_hi = {_idxHit_T_27, _idxHit_T_26}; // @[package.scala:45:27] wire [3:0] idxHit_hi_hi_hi = {idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_hi = {idxHit_hi_hi_hi, idxHit_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_hi = {idxHit_hi_hi, idxHit_hi_lo}; // @[package.scala:45:27] wire [27:0] _idxHit_T_28 = {idxHit_hi, idxHit_lo}; // @[package.scala:45:27] wire [27:0] idxHit = _idxHit_T_28 & isValid; // @[package.scala:45:27] wire [33:0] updatePageHit_p = r_btb_update_bits_pc[47:14]; // @[Valid.scala:135:21] wire [33:0] _samePage_T = r_btb_update_bits_pc[47:14]; // @[Valid.scala:135:21] wire _updatePageHit_T = pages_0 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_1 = pages_1 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_2 = pages_2 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_3 = pages_3 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_4 = pages_4 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_5 = pages_5 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] updatePageHit_lo_hi = {_updatePageHit_T_2, _updatePageHit_T_1}; // @[package.scala:45:27] wire [2:0] updatePageHit_lo = {updatePageHit_lo_hi, _updatePageHit_T}; // @[package.scala:45:27] wire [1:0] updatePageHit_hi_hi = {_updatePageHit_T_5, _updatePageHit_T_4}; // @[package.scala:45:27] wire [2:0] updatePageHit_hi = {updatePageHit_hi_hi, _updatePageHit_T_3}; // @[package.scala:45:27] wire [5:0] _updatePageHit_T_6 = {updatePageHit_hi, updatePageHit_lo}; // @[package.scala:45:27] wire [5:0] updatePageHit = pageValid & _updatePageHit_T_6; // @[package.scala:45:27] wire updateHit = r_btb_update_bits_prediction_entry[4:2] != 3'h7; // @[Valid.scala:135:21] wire useUpdatePageHit = |updatePageHit; // @[BTB.scala:214:15, :234:40] wire usePageHit = |pageHit; // @[BTB.scala:214:15, :235:28] wire doIdxPageRepl = ~useUpdatePageHit; // @[BTB.scala:234:40, :236:23] reg [2:0] nextPageRepl; // @[BTB.scala:237:29] wire [4:0] _idxPageRepl_T = pageHit[4:0]; // @[BTB.scala:214:15, :238:32] wire _idxPageRepl_T_1 = pageHit[5]; // @[BTB.scala:214:15, :238:53] wire [5:0] _idxPageRepl_T_2 = {_idxPageRepl_T, _idxPageRepl_T_1}; // @[BTB.scala:238:{24,32,53}] wire [7:0] _idxPageRepl_T_3 = 8'h1 << nextPageRepl; // @[OneHot.scala:58:35] wire [7:0] _idxPageRepl_T_4 = usePageHit ? 8'h0 : _idxPageRepl_T_3; // @[OneHot.scala:58:35] wire [7:0] idxPageRepl = {2'h0, _idxPageRepl_T_2} | _idxPageRepl_T_4; // @[BTB.scala:238:{24,65,70}] wire [7:0] idxPageUpdateOH = useUpdatePageHit ? {2'h0, updatePageHit} : idxPageRepl; // @[BTB.scala:214:15, :234:40, :238:65, :239:28] wire [3:0] idxPageUpdate_hi = idxPageUpdateOH[7:4]; // @[OneHot.scala:30:18] wire [3:0] idxPageUpdate_lo = idxPageUpdateOH[3:0]; // @[OneHot.scala:31:18] wire _idxPageUpdate_T = |idxPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _idxPageUpdate_T_1 = idxPageUpdate_hi | idxPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] idxPageUpdate_hi_1 = _idxPageUpdate_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] idxPageUpdate_lo_1 = _idxPageUpdate_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _idxPageUpdate_T_2 = |idxPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _idxPageUpdate_T_3 = idxPageUpdate_hi_1 | idxPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _idxPageUpdate_T_4 = _idxPageUpdate_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _idxPageUpdate_T_5 = {_idxPageUpdate_T_2, _idxPageUpdate_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] idxPageUpdate = {_idxPageUpdate_T, _idxPageUpdate_T_5}; // @[OneHot.scala:32:{10,14}] wire [7:0] idxPageReplEn = doIdxPageRepl ? idxPageRepl : 8'h0; // @[BTB.scala:236:23, :238:65, :241:26] wire samePage = _samePage_T == _samePage_T_1; // @[BTB.scala:211:39, :243:45] wire _doTgtPageRepl_T = ~samePage; // @[BTB.scala:243:45, :244:23] wire _doTgtPageRepl_T_1 = ~usePageHit; // @[BTB.scala:235:28, :244:36] wire doTgtPageRepl = _doTgtPageRepl_T & _doTgtPageRepl_T_1; // @[BTB.scala:244:{23,33,36}] wire [4:0] _tgtPageRepl_T = idxPageUpdateOH[4:0]; // @[BTB.scala:239:28, :245:71] wire _tgtPageRepl_T_1 = idxPageUpdateOH[5]; // @[BTB.scala:239:28, :245:100] wire [5:0] _tgtPageRepl_T_2 = {_tgtPageRepl_T, _tgtPageRepl_T_1}; // @[BTB.scala:245:{55,71,100}] wire [7:0] tgtPageRepl = samePage ? idxPageUpdateOH : {2'h0, _tgtPageRepl_T_2}; // @[BTB.scala:239:28, :243:45, :245:{24,55}] wire [7:0] _tgtPageUpdate_T = usePageHit ? 8'h0 : tgtPageRepl; // @[BTB.scala:235:28, :245:24, :246:45] wire [7:0] _tgtPageUpdate_T_1 = {2'h0, pageHit} | _tgtPageUpdate_T; // @[BTB.scala:214:15, :246:{40,45}] wire [3:0] tgtPageUpdate_hi = _tgtPageUpdate_T_1[7:4]; // @[OneHot.scala:30:18] wire [3:0] tgtPageUpdate_lo = _tgtPageUpdate_T_1[3:0]; // @[OneHot.scala:31:18] wire _tgtPageUpdate_T_2 = |tgtPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _tgtPageUpdate_T_3 = tgtPageUpdate_hi | tgtPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] tgtPageUpdate_hi_1 = _tgtPageUpdate_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] tgtPageUpdate_lo_1 = _tgtPageUpdate_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _tgtPageUpdate_T_4 = |tgtPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _tgtPageUpdate_T_5 = tgtPageUpdate_hi_1 | tgtPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _tgtPageUpdate_T_6 = _tgtPageUpdate_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _tgtPageUpdate_T_7 = {_tgtPageUpdate_T_4, _tgtPageUpdate_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] tgtPageUpdate = {_tgtPageUpdate_T_2, _tgtPageUpdate_T_7}; // @[OneHot.scala:32:{10,14}] wire [7:0] tgtPageReplEn = doTgtPageRepl ? tgtPageRepl : 8'h0; // @[BTB.scala:244:33, :245:24, :247:26] wire both = doIdxPageRepl & doTgtPageRepl; // @[BTB.scala:236:23, :244:33, :250:30] wire [1:0] _next_T = both ? 2'h2 : 2'h1; // @[BTB.scala:250:30, :251:40, :292:33] wire [3:0] _next_T_1 = {1'h0, nextPageRepl} + {2'h0, _next_T}; // @[BTB.scala:237:29, :251:{29,40}] wire [2:0] next = _next_T_1[2:0]; // @[BTB.scala:251:29] wire _nextPageRepl_T = next > 3'h5; // @[BTB.scala:251:29, :252:30] wire _nextPageRepl_T_1 = next[0]; // @[BTB.scala:251:29, :252:47] wire [2:0] _nextPageRepl_T_2 = _nextPageRepl_T ? {2'h0, _nextPageRepl_T_1} : next; // @[BTB.scala:251:29, :252:{24,30,47}] reg [26:0] state_reg; // @[Replacement.scala:168:70] wire waddr_left_subtree_older = state_reg[26]; // @[Replacement.scala:168:70, :243:38] wire [10:0] waddr_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [10:0] state_reg_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [14:0] waddr_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :245:38] wire [14:0] state_reg_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire waddr_left_subtree_older_1 = waddr_left_subtree_state[10]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_1 = waddr_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_1 = waddr_left_subtree_state[6:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_2 = waddr_left_subtree_state_1[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_2 = waddr_left_subtree_state_1[1]; // @[package.scala:163:13] wire _waddr_T = waddr_left_subtree_state_2; // @[package.scala:163:13] wire waddr_right_subtree_state_2 = waddr_left_subtree_state_1[0]; // @[package.scala:163:13] wire _waddr_T_1 = waddr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_2 = waddr_left_subtree_older_2 ? _waddr_T : _waddr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_3 = {waddr_left_subtree_older_2, _waddr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_3 = waddr_right_subtree_state_1[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_3 = waddr_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_3 = waddr_right_subtree_state_1[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_4 = waddr_left_subtree_state_3[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_4 = waddr_left_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_4 = waddr_left_subtree_state_4; // @[package.scala:163:13] wire waddr_right_subtree_state_4 = waddr_left_subtree_state_3[0]; // @[package.scala:163:13] wire _waddr_T_5 = waddr_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_6 = waddr_left_subtree_older_4 ? _waddr_T_4 : _waddr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_7 = {waddr_left_subtree_older_4, _waddr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_5 = waddr_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_5 = waddr_right_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_8 = waddr_left_subtree_state_5; // @[package.scala:163:13] wire waddr_right_subtree_state_5 = waddr_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _waddr_T_9 = waddr_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_10 = waddr_left_subtree_older_5 ? _waddr_T_8 : _waddr_T_9; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_11 = {waddr_left_subtree_older_5, _waddr_T_10}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_12 = waddr_left_subtree_older_3 ? _waddr_T_7 : _waddr_T_11; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_13 = {waddr_left_subtree_older_3, _waddr_T_12}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_14 = waddr_left_subtree_older_1 ? {1'h0, _waddr_T_3} : _waddr_T_13; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_15 = {waddr_left_subtree_older_1, _waddr_T_14}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_6 = waddr_right_subtree_state[14]; // @[Replacement.scala:243:38, :245:38] wire [6:0] waddr_left_subtree_state_6 = waddr_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_6 = waddr_right_subtree_state[6:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_7 = waddr_left_subtree_state_6[6]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_7 = waddr_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_7 = waddr_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_8 = waddr_left_subtree_state_7[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_8 = waddr_left_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_16 = waddr_left_subtree_state_8; // @[package.scala:163:13] wire waddr_right_subtree_state_8 = waddr_left_subtree_state_7[0]; // @[package.scala:163:13] wire _waddr_T_17 = waddr_right_subtree_state_8; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_18 = waddr_left_subtree_older_8 ? _waddr_T_16 : _waddr_T_17; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_19 = {waddr_left_subtree_older_8, _waddr_T_18}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_9 = waddr_right_subtree_state_7[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_9 = waddr_right_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_20 = waddr_left_subtree_state_9; // @[package.scala:163:13] wire waddr_right_subtree_state_9 = waddr_right_subtree_state_7[0]; // @[Replacement.scala:245:38] wire _waddr_T_21 = waddr_right_subtree_state_9; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_22 = waddr_left_subtree_older_9 ? _waddr_T_20 : _waddr_T_21; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_23 = {waddr_left_subtree_older_9, _waddr_T_22}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_24 = waddr_left_subtree_older_7 ? _waddr_T_19 : _waddr_T_23; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_25 = {waddr_left_subtree_older_7, _waddr_T_24}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_10 = waddr_right_subtree_state_6[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_10 = waddr_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_10 = waddr_right_subtree_state_6[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_11 = waddr_left_subtree_state_10[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_11 = waddr_left_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_26 = waddr_left_subtree_state_11; // @[package.scala:163:13] wire waddr_right_subtree_state_11 = waddr_left_subtree_state_10[0]; // @[package.scala:163:13] wire _waddr_T_27 = waddr_right_subtree_state_11; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_28 = waddr_left_subtree_older_11 ? _waddr_T_26 : _waddr_T_27; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_29 = {waddr_left_subtree_older_11, _waddr_T_28}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_12 = waddr_right_subtree_state_10[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_12 = waddr_right_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_30 = waddr_left_subtree_state_12; // @[package.scala:163:13] wire waddr_right_subtree_state_12 = waddr_right_subtree_state_10[0]; // @[Replacement.scala:245:38] wire _waddr_T_31 = waddr_right_subtree_state_12; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_32 = waddr_left_subtree_older_12 ? _waddr_T_30 : _waddr_T_31; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_33 = {waddr_left_subtree_older_12, _waddr_T_32}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_34 = waddr_left_subtree_older_10 ? _waddr_T_29 : _waddr_T_33; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_35 = {waddr_left_subtree_older_10, _waddr_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_36 = waddr_left_subtree_older_6 ? _waddr_T_25 : _waddr_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_37 = {waddr_left_subtree_older_6, _waddr_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_38 = waddr_left_subtree_older ? _waddr_T_15 : _waddr_T_37; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] _waddr_T_39 = {waddr_left_subtree_older, _waddr_T_38}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] waddr = updateHit ? r_btb_update_bits_prediction_entry : _waddr_T_39; // @[Valid.scala:135:21] reg r_resp_pipe_v; // @[Valid.scala:141:24] wire r_resp_valid = r_resp_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_resp_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_cfiType = r_resp_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_taken; // @[Valid.scala:142:26] wire r_resp_bits_taken = r_resp_pipe_b_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_resp_pipe_b_mask; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_mask = r_resp_pipe_b_mask; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bridx; // @[Valid.scala:142:26] wire r_resp_bits_bridx = r_resp_pipe_b_bridx; // @[Valid.scala:135:21, :142:26] reg [47:0] r_resp_pipe_b_target; // @[Valid.scala:142:26] wire [47:0] r_resp_bits_target = r_resp_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_resp_pipe_b_entry; // @[Valid.scala:142:26] wire [4:0] r_resp_bits_entry = r_resp_pipe_b_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_resp_pipe_b_bht_history; // @[Valid.scala:142:26] wire [7:0] r_resp_bits_bht_history = r_resp_pipe_b_bht_history; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bht_value; // @[Valid.scala:142:26] wire r_resp_bits_bht_value = r_resp_pipe_b_bht_value; // @[Valid.scala:135:21, :142:26] wire [4:0] state_reg_touch_way_sized = r_btb_update_valid ? waddr : r_resp_bits_entry; // @[Valid.scala:135:21] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[4]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0] _state_reg_T = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire [3:0] _state_reg_T_39 = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[3]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_1 = state_reg_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_1 = state_reg_left_subtree_state[6:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_1 = _state_reg_T[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_left_subtree_state_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_left_subtree_state_1[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_3 = _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_4 = ~_state_reg_T_3; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_5 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_4; // @[package.scala:163:13] wire _state_reg_T_7 = _state_reg_T_6; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_8 = ~_state_reg_T_7; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_9 = state_reg_set_left_older_2 ? _state_reg_T_8 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_2, _state_reg_T_5}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_10 = {state_reg_hi, _state_reg_T_9}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_11 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_10; // @[package.scala:163:13] wire [2:0] _state_reg_T_12 = _state_reg_T[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_3 = _state_reg_T_12[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_3 = state_reg_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_3 = state_reg_right_subtree_state_1[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_13 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_24 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_13[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_14 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_18 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_15 = _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_16 = ~_state_reg_T_15; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_17 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_16; // @[package.scala:163:13] wire _state_reg_T_19 = _state_reg_T_18; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_20 = ~_state_reg_T_19; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_21 = state_reg_set_left_older_4 ? _state_reg_T_20 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_4, _state_reg_T_17}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_22 = {state_reg_hi_1, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_23 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_22; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_24[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_25 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_26 = _state_reg_T_25; // @[package.scala:163:13] wire _state_reg_T_27 = ~_state_reg_T_26; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_28 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_27; // @[package.scala:163:13] wire _state_reg_T_30 = _state_reg_T_29; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_31 = ~_state_reg_T_30; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_32 = state_reg_set_left_older_5 ? _state_reg_T_31 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_2 = {state_reg_set_left_older_5, _state_reg_T_28}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_33 = {state_reg_hi_2, _state_reg_T_32}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_34 = state_reg_set_left_older_3 ? _state_reg_T_33 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_23}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_35 = {state_reg_hi_3, _state_reg_T_34}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_36 = state_reg_set_left_older_1 ? _state_reg_T_35 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_4 = {state_reg_set_left_older_1, _state_reg_T_11}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [10:0] _state_reg_T_37 = {state_reg_hi_4, _state_reg_T_36}; // @[Replacement.scala:202:12, :206:16] wire [10:0] _state_reg_T_38 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_set_left_older_T_6 = _state_reg_T_39[3]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [6:0] state_reg_left_subtree_state_6 = state_reg_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_6 = state_reg_right_subtree_state[6:0]; // @[Replacement.scala:198:38] wire [2:0] _state_reg_T_40 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire [2:0] _state_reg_T_65 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_40[2]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_41 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_52 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_41[1]; // @[package.scala:163:13] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_left_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_left_subtree_state_7[0]; // @[package.scala:163:13] wire _state_reg_T_42 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_46 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_43 = _state_reg_T_42; // @[package.scala:163:13] wire _state_reg_T_44 = ~_state_reg_T_43; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_45 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_44; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_48 = ~_state_reg_T_47; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_49 = state_reg_set_left_older_8 ? _state_reg_T_48 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_5 = {state_reg_set_left_older_8, _state_reg_T_45}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_50 = {state_reg_hi_5, _state_reg_T_49}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_51 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_50; // @[package.scala:163:13] wire _state_reg_set_left_older_T_9 = _state_reg_T_52[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_9 = ~_state_reg_set_left_older_T_9; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_9 = state_reg_right_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_9 = state_reg_right_subtree_state_7[0]; // @[Replacement.scala:198:38] wire _state_reg_T_53 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_57 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_54 = _state_reg_T_53; // @[package.scala:163:13] wire _state_reg_T_55 = ~_state_reg_T_54; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_56 = state_reg_set_left_older_9 ? state_reg_left_subtree_state_9 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_T_58 = _state_reg_T_57; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_59 = ~_state_reg_T_58; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_60 = state_reg_set_left_older_9 ? _state_reg_T_59 : state_reg_right_subtree_state_9; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_9, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_61 = {state_reg_hi_6, _state_reg_T_60}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_62 = state_reg_set_left_older_7 ? _state_reg_T_61 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_7 = {state_reg_set_left_older_7, _state_reg_T_51}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_63 = {state_reg_hi_7, _state_reg_T_62}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_64 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_63; // @[package.scala:163:13] wire _state_reg_set_left_older_T_10 = _state_reg_T_65[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_10 = ~_state_reg_set_left_older_T_10; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_10 = state_reg_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_10 = state_reg_right_subtree_state_6[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_66 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_77 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_11 = _state_reg_T_66[1]; // @[package.scala:163:13] wire state_reg_set_left_older_11 = ~_state_reg_set_left_older_T_11; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_11 = state_reg_left_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_left_subtree_state_10[0]; // @[package.scala:163:13] wire _state_reg_T_67 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_71 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_68 = _state_reg_T_67; // @[package.scala:163:13] wire _state_reg_T_69 = ~_state_reg_T_68; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_70 = state_reg_set_left_older_11 ? state_reg_left_subtree_state_11 : _state_reg_T_69; // @[package.scala:163:13] wire _state_reg_T_72 = _state_reg_T_71; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_73 = ~_state_reg_T_72; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_74 = state_reg_set_left_older_11 ? _state_reg_T_73 : state_reg_right_subtree_state_11; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_8 = {state_reg_set_left_older_11, _state_reg_T_70}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_75 = {state_reg_hi_8, _state_reg_T_74}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_76 = state_reg_set_left_older_10 ? state_reg_left_subtree_state_10 : _state_reg_T_75; // @[package.scala:163:13] wire _state_reg_set_left_older_T_12 = _state_reg_T_77[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_12 = ~_state_reg_set_left_older_T_12; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_12 = state_reg_right_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_12 = state_reg_right_subtree_state_10[0]; // @[Replacement.scala:198:38] wire _state_reg_T_78 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_82 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_79 = _state_reg_T_78; // @[package.scala:163:13] wire _state_reg_T_80 = ~_state_reg_T_79; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_81 = state_reg_set_left_older_12 ? state_reg_left_subtree_state_12 : _state_reg_T_80; // @[package.scala:163:13] wire _state_reg_T_83 = _state_reg_T_82; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_84 = ~_state_reg_T_83; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_85 = state_reg_set_left_older_12 ? _state_reg_T_84 : state_reg_right_subtree_state_12; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_9 = {state_reg_set_left_older_12, _state_reg_T_81}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_86 = {state_reg_hi_9, _state_reg_T_85}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_87 = state_reg_set_left_older_10 ? _state_reg_T_86 : state_reg_right_subtree_state_10; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_10 = {state_reg_set_left_older_10, _state_reg_T_76}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_88 = {state_reg_hi_10, _state_reg_T_87}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_89 = state_reg_set_left_older_6 ? _state_reg_T_88 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [7:0] state_reg_hi_11 = {state_reg_set_left_older_6, _state_reg_T_64}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [14:0] _state_reg_T_90 = {state_reg_hi_11, _state_reg_T_89}; // @[Replacement.scala:202:12, :206:16] wire [14:0] _state_reg_T_91 = state_reg_set_left_older ? _state_reg_T_90 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [11:0] state_reg_hi_12 = {state_reg_set_left_older, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [26:0] _state_reg_T_92 = {state_reg_hi_12, _state_reg_T_91}; // @[Replacement.scala:202:12, :206:16] wire [31:0] mask = 32'h1 << waddr; // @[OneHot.scala:58:35] wire [12:0] _idxs_T = r_btb_update_bits_pc[13:1]; // @[Valid.scala:135:21] wire [3:0] _idxPages_T = {1'h0, idxPageUpdate} + 4'h1; // @[OneHot.scala:32:10] wire [31:0] _isValid_T = {4'h0, isValid} | mask; // @[OneHot.scala:32:14, :58:35] wire [31:0] _isValid_T_1 = ~mask; // @[OneHot.scala:58:35] wire [31:0] _isValid_T_2 = {4'h0, _isValid_T_1[27:0] & isValid}; // @[OneHot.scala:32:14] wire [31:0] _isValid_T_3 = r_btb_update_bits_isValid ? _isValid_T : _isValid_T_2; // @[Valid.scala:135:21] wire [46:0] _brIdx_T = r_btb_update_bits_br_pc[47:1]; // @[Valid.scala:135:21] wire _idxWritesEven_T = idxPageUpdate[0]; // @[OneHot.scala:32:10] wire idxWritesEven = ~_idxWritesEven_T; // @[BTB.scala:274:{25,39}] wire [7:0] _pageValid_T = {2'h0, pageValid} | tgtPageReplEn; // @[BTB.scala:204:26, :247:26, :284:28] wire [7:0] _pageValid_T_1 = _pageValid_T | idxPageReplEn; // @[BTB.scala:241:26, :284:{28,44}] wire [6:0] _io_resp_valid_T = {pageHit, 1'h0}; // @[BTB.scala:214:15, :287:29] wire _io_resp_valid_T_1 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_97 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_valid_T_2 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_98 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_valid_T_3 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_99 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_valid_T_4 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_100 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_valid_T_5 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_101 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_valid_T_6 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_102 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_valid_T_7 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_103 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_valid_T_8 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_104 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_valid_T_9 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_105 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_valid_T_10 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_106 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_valid_T_11 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_107 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_valid_T_12 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_108 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_valid_T_13 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_109 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_valid_T_14 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_110 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_valid_T_15 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_111 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_valid_T_16 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_112 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_valid_T_17 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_113 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_valid_T_18 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_114 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_valid_T_19 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_115 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_valid_T_20 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_116 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_valid_T_21 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_117 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_valid_T_22 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_118 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_valid_T_23 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_119 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_valid_T_24 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_120 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_valid_T_25 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_121 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_valid_T_26 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_122 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_valid_T_27 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_123 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_valid_T_28 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_124 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire [2:0] _io_resp_valid_T_29 = _io_resp_valid_T_1 ? idxPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_30 = _io_resp_valid_T_2 ? idxPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_31 = _io_resp_valid_T_3 ? idxPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_32 = _io_resp_valid_T_4 ? idxPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_33 = _io_resp_valid_T_5 ? idxPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_34 = _io_resp_valid_T_6 ? idxPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_35 = _io_resp_valid_T_7 ? idxPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_36 = _io_resp_valid_T_8 ? idxPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_37 = _io_resp_valid_T_9 ? idxPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_38 = _io_resp_valid_T_10 ? idxPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_39 = _io_resp_valid_T_11 ? idxPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_40 = _io_resp_valid_T_12 ? idxPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_41 = _io_resp_valid_T_13 ? idxPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_42 = _io_resp_valid_T_14 ? idxPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_43 = _io_resp_valid_T_15 ? idxPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_44 = _io_resp_valid_T_16 ? idxPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_45 = _io_resp_valid_T_17 ? idxPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_46 = _io_resp_valid_T_18 ? idxPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_47 = _io_resp_valid_T_19 ? idxPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_48 = _io_resp_valid_T_20 ? idxPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_49 = _io_resp_valid_T_21 ? idxPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_50 = _io_resp_valid_T_22 ? idxPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_51 = _io_resp_valid_T_23 ? idxPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_52 = _io_resp_valid_T_24 ? idxPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_53 = _io_resp_valid_T_25 ? idxPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_54 = _io_resp_valid_T_26 ? idxPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_55 = _io_resp_valid_T_27 ? idxPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_56 = _io_resp_valid_T_28 ? idxPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_57 = _io_resp_valid_T_29 | _io_resp_valid_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_58 = _io_resp_valid_T_57 | _io_resp_valid_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_59 = _io_resp_valid_T_58 | _io_resp_valid_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_60 = _io_resp_valid_T_59 | _io_resp_valid_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_61 = _io_resp_valid_T_60 | _io_resp_valid_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_62 = _io_resp_valid_T_61 | _io_resp_valid_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_63 = _io_resp_valid_T_62 | _io_resp_valid_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_64 = _io_resp_valid_T_63 | _io_resp_valid_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_65 = _io_resp_valid_T_64 | _io_resp_valid_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_66 = _io_resp_valid_T_65 | _io_resp_valid_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_67 = _io_resp_valid_T_66 | _io_resp_valid_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_68 = _io_resp_valid_T_67 | _io_resp_valid_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_69 = _io_resp_valid_T_68 | _io_resp_valid_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_70 = _io_resp_valid_T_69 | _io_resp_valid_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_71 = _io_resp_valid_T_70 | _io_resp_valid_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_72 = _io_resp_valid_T_71 | _io_resp_valid_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_73 = _io_resp_valid_T_72 | _io_resp_valid_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_74 = _io_resp_valid_T_73 | _io_resp_valid_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_75 = _io_resp_valid_T_74 | _io_resp_valid_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_76 = _io_resp_valid_T_75 | _io_resp_valid_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_77 = _io_resp_valid_T_76 | _io_resp_valid_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_78 = _io_resp_valid_T_77 | _io_resp_valid_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_79 = _io_resp_valid_T_78 | _io_resp_valid_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_80 = _io_resp_valid_T_79 | _io_resp_valid_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_81 = _io_resp_valid_T_80 | _io_resp_valid_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_82 = _io_resp_valid_T_81 | _io_resp_valid_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_83 = _io_resp_valid_T_82 | _io_resp_valid_T_56; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_WIRE = _io_resp_valid_T_83; // @[Mux.scala:30:73] wire [6:0] _io_resp_valid_T_84 = _io_resp_valid_T >> _io_resp_valid_WIRE; // @[Mux.scala:30:73] assign _io_resp_valid_T_85 = _io_resp_valid_T_84[0]; // @[BTB.scala:287:34] assign io_resp_valid_0 = _io_resp_valid_T_85; // @[BTB.scala:187:7, :287:34] wire [2:0] _io_resp_bits_target_T_28 = _io_resp_bits_target_T ? tgtPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_29 = _io_resp_bits_target_T_1 ? tgtPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_30 = _io_resp_bits_target_T_2 ? tgtPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_31 = _io_resp_bits_target_T_3 ? tgtPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_32 = _io_resp_bits_target_T_4 ? tgtPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_33 = _io_resp_bits_target_T_5 ? tgtPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_34 = _io_resp_bits_target_T_6 ? tgtPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_35 = _io_resp_bits_target_T_7 ? tgtPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_36 = _io_resp_bits_target_T_8 ? tgtPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_37 = _io_resp_bits_target_T_9 ? tgtPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_38 = _io_resp_bits_target_T_10 ? tgtPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_39 = _io_resp_bits_target_T_11 ? tgtPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_40 = _io_resp_bits_target_T_12 ? tgtPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_41 = _io_resp_bits_target_T_13 ? tgtPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_42 = _io_resp_bits_target_T_14 ? tgtPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_43 = _io_resp_bits_target_T_15 ? tgtPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_44 = _io_resp_bits_target_T_16 ? tgtPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_45 = _io_resp_bits_target_T_17 ? tgtPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_46 = _io_resp_bits_target_T_18 ? tgtPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_47 = _io_resp_bits_target_T_19 ? tgtPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_48 = _io_resp_bits_target_T_20 ? tgtPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_49 = _io_resp_bits_target_T_21 ? tgtPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_50 = _io_resp_bits_target_T_22 ? tgtPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_51 = _io_resp_bits_target_T_23 ? tgtPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_52 = _io_resp_bits_target_T_24 ? tgtPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_53 = _io_resp_bits_target_T_25 ? tgtPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_54 = _io_resp_bits_target_T_26 ? tgtPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_55 = _io_resp_bits_target_T_27 ? tgtPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_56 = _io_resp_bits_target_T_28 | _io_resp_bits_target_T_29; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_57 = _io_resp_bits_target_T_56 | _io_resp_bits_target_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_58 = _io_resp_bits_target_T_57 | _io_resp_bits_target_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_59 = _io_resp_bits_target_T_58 | _io_resp_bits_target_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_60 = _io_resp_bits_target_T_59 | _io_resp_bits_target_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_61 = _io_resp_bits_target_T_60 | _io_resp_bits_target_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_62 = _io_resp_bits_target_T_61 | _io_resp_bits_target_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_63 = _io_resp_bits_target_T_62 | _io_resp_bits_target_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_64 = _io_resp_bits_target_T_63 | _io_resp_bits_target_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_65 = _io_resp_bits_target_T_64 | _io_resp_bits_target_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_66 = _io_resp_bits_target_T_65 | _io_resp_bits_target_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_67 = _io_resp_bits_target_T_66 | _io_resp_bits_target_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_68 = _io_resp_bits_target_T_67 | _io_resp_bits_target_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_69 = _io_resp_bits_target_T_68 | _io_resp_bits_target_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_70 = _io_resp_bits_target_T_69 | _io_resp_bits_target_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_71 = _io_resp_bits_target_T_70 | _io_resp_bits_target_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_72 = _io_resp_bits_target_T_71 | _io_resp_bits_target_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_73 = _io_resp_bits_target_T_72 | _io_resp_bits_target_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_74 = _io_resp_bits_target_T_73 | _io_resp_bits_target_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_75 = _io_resp_bits_target_T_74 | _io_resp_bits_target_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_76 = _io_resp_bits_target_T_75 | _io_resp_bits_target_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_77 = _io_resp_bits_target_T_76 | _io_resp_bits_target_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_78 = _io_resp_bits_target_T_77 | _io_resp_bits_target_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_79 = _io_resp_bits_target_T_78 | _io_resp_bits_target_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_80 = _io_resp_bits_target_T_79 | _io_resp_bits_target_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_81 = _io_resp_bits_target_T_80 | _io_resp_bits_target_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_82 = _io_resp_bits_target_T_81 | _io_resp_bits_target_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_WIRE = _io_resp_bits_target_T_82; // @[Mux.scala:30:73] wire _io_resp_bits_target_T_83 = _io_resp_bits_target_WIRE == 3'h1; // @[Mux.scala:30:73] wire [33:0] _io_resp_bits_target_T_84 = _io_resp_bits_target_T_83 ? pagesMasked_1 : pagesMasked_0; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_85 = _io_resp_bits_target_WIRE == 3'h2; // @[Mux.scala:30:73] wire [33:0] _io_resp_bits_target_T_86 = _io_resp_bits_target_T_85 ? pagesMasked_2 : _io_resp_bits_target_T_84; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_87 = _io_resp_bits_target_WIRE == 3'h3; // @[Mux.scala:30:73] wire [33:0] _io_resp_bits_target_T_88 = _io_resp_bits_target_T_87 ? pagesMasked_3 : _io_resp_bits_target_T_86; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_89 = _io_resp_bits_target_WIRE == 3'h4; // @[Mux.scala:30:73] wire [33:0] _io_resp_bits_target_T_90 = _io_resp_bits_target_T_89 ? pagesMasked_4 : _io_resp_bits_target_T_88; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_91 = _io_resp_bits_target_WIRE == 3'h5; // @[Mux.scala:30:73] wire [33:0] _io_resp_bits_target_T_92 = _io_resp_bits_target_T_91 ? pagesMasked_5 : _io_resp_bits_target_T_90; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_93 = _io_resp_bits_target_WIRE == 3'h6; // @[Mux.scala:30:73] wire [33:0] _io_resp_bits_target_T_94 = _io_resp_bits_target_T_93 ? pagesMasked_4 : _io_resp_bits_target_T_92; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_95 = &_io_resp_bits_target_WIRE; // @[Mux.scala:30:73] wire [33:0] _io_resp_bits_target_T_96 = _io_resp_bits_target_T_95 ? pagesMasked_5 : _io_resp_bits_target_T_94; // @[package.scala:39:{76,86}] wire [12:0] _io_resp_bits_target_T_125 = _io_resp_bits_target_T_97 ? tgts_0 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_126 = _io_resp_bits_target_T_98 ? tgts_1 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_127 = _io_resp_bits_target_T_99 ? tgts_2 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_128 = _io_resp_bits_target_T_100 ? tgts_3 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_129 = _io_resp_bits_target_T_101 ? tgts_4 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_130 = _io_resp_bits_target_T_102 ? tgts_5 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_131 = _io_resp_bits_target_T_103 ? tgts_6 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_132 = _io_resp_bits_target_T_104 ? tgts_7 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_133 = _io_resp_bits_target_T_105 ? tgts_8 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_134 = _io_resp_bits_target_T_106 ? tgts_9 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_135 = _io_resp_bits_target_T_107 ? tgts_10 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_136 = _io_resp_bits_target_T_108 ? tgts_11 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_137 = _io_resp_bits_target_T_109 ? tgts_12 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_138 = _io_resp_bits_target_T_110 ? tgts_13 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_139 = _io_resp_bits_target_T_111 ? tgts_14 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_140 = _io_resp_bits_target_T_112 ? tgts_15 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_141 = _io_resp_bits_target_T_113 ? tgts_16 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_142 = _io_resp_bits_target_T_114 ? tgts_17 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_143 = _io_resp_bits_target_T_115 ? tgts_18 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_144 = _io_resp_bits_target_T_116 ? tgts_19 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_145 = _io_resp_bits_target_T_117 ? tgts_20 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_146 = _io_resp_bits_target_T_118 ? tgts_21 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_147 = _io_resp_bits_target_T_119 ? tgts_22 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_148 = _io_resp_bits_target_T_120 ? tgts_23 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_149 = _io_resp_bits_target_T_121 ? tgts_24 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_150 = _io_resp_bits_target_T_122 ? tgts_25 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_151 = _io_resp_bits_target_T_123 ? tgts_26 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_152 = _io_resp_bits_target_T_124 ? tgts_27 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_153 = _io_resp_bits_target_T_125 | _io_resp_bits_target_T_126; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_154 = _io_resp_bits_target_T_153 | _io_resp_bits_target_T_127; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_155 = _io_resp_bits_target_T_154 | _io_resp_bits_target_T_128; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_156 = _io_resp_bits_target_T_155 | _io_resp_bits_target_T_129; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_157 = _io_resp_bits_target_T_156 | _io_resp_bits_target_T_130; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_158 = _io_resp_bits_target_T_157 | _io_resp_bits_target_T_131; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_159 = _io_resp_bits_target_T_158 | _io_resp_bits_target_T_132; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_160 = _io_resp_bits_target_T_159 | _io_resp_bits_target_T_133; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_161 = _io_resp_bits_target_T_160 | _io_resp_bits_target_T_134; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_162 = _io_resp_bits_target_T_161 | _io_resp_bits_target_T_135; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_163 = _io_resp_bits_target_T_162 | _io_resp_bits_target_T_136; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_164 = _io_resp_bits_target_T_163 | _io_resp_bits_target_T_137; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_165 = _io_resp_bits_target_T_164 | _io_resp_bits_target_T_138; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_166 = _io_resp_bits_target_T_165 | _io_resp_bits_target_T_139; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_167 = _io_resp_bits_target_T_166 | _io_resp_bits_target_T_140; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_168 = _io_resp_bits_target_T_167 | _io_resp_bits_target_T_141; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_169 = _io_resp_bits_target_T_168 | _io_resp_bits_target_T_142; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_170 = _io_resp_bits_target_T_169 | _io_resp_bits_target_T_143; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_171 = _io_resp_bits_target_T_170 | _io_resp_bits_target_T_144; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_172 = _io_resp_bits_target_T_171 | _io_resp_bits_target_T_145; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_173 = _io_resp_bits_target_T_172 | _io_resp_bits_target_T_146; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_174 = _io_resp_bits_target_T_173 | _io_resp_bits_target_T_147; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_175 = _io_resp_bits_target_T_174 | _io_resp_bits_target_T_148; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_176 = _io_resp_bits_target_T_175 | _io_resp_bits_target_T_149; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_177 = _io_resp_bits_target_T_176 | _io_resp_bits_target_T_150; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_178 = _io_resp_bits_target_T_177 | _io_resp_bits_target_T_151; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_179 = _io_resp_bits_target_T_178 | _io_resp_bits_target_T_152; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_WIRE_1 = _io_resp_bits_target_T_179; // @[Mux.scala:30:73] wire [13:0] _io_resp_bits_target_T_180 = {_io_resp_bits_target_WIRE_1, 1'h0}; // @[Mux.scala:30:73] wire [47:0] _io_resp_bits_target_T_181 = {_io_resp_bits_target_T_96, _io_resp_bits_target_T_180}; // @[package.scala:39:76] wire [11:0] io_resp_bits_entry_hi = idxHit[27:16]; // @[OneHot.scala:30:18] wire [15:0] io_resp_bits_entry_lo = idxHit[15:0]; // @[OneHot.scala:31:18] wire _io_resp_bits_entry_T = |io_resp_bits_entry_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _io_resp_bits_entry_T_1 = {4'h0, io_resp_bits_entry_hi} | io_resp_bits_entry_lo; // @[OneHot.scala:30:18, :31:18, :32:{14,28}] wire [7:0] io_resp_bits_entry_hi_1 = _io_resp_bits_entry_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] io_resp_bits_entry_lo_1 = _io_resp_bits_entry_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_2 = |io_resp_bits_entry_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _io_resp_bits_entry_T_3 = io_resp_bits_entry_hi_1 | io_resp_bits_entry_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] io_resp_bits_entry_hi_2 = _io_resp_bits_entry_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] io_resp_bits_entry_lo_2 = _io_resp_bits_entry_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_4 = |io_resp_bits_entry_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _io_resp_bits_entry_T_5 = io_resp_bits_entry_hi_2 | io_resp_bits_entry_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] io_resp_bits_entry_hi_3 = _io_resp_bits_entry_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] io_resp_bits_entry_lo_3 = _io_resp_bits_entry_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_6 = |io_resp_bits_entry_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _io_resp_bits_entry_T_7 = io_resp_bits_entry_hi_3 | io_resp_bits_entry_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _io_resp_bits_entry_T_8 = _io_resp_bits_entry_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _io_resp_bits_entry_T_9 = {_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _io_resp_bits_entry_T_10 = {_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _io_resp_bits_entry_T_11 = {_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10}; // @[OneHot.scala:32:{10,14}] assign _io_resp_bits_entry_T_12 = {_io_resp_bits_entry_T, _io_resp_bits_entry_T_11}; // @[OneHot.scala:32:{10,14}] assign io_resp_bits_entry_0 = _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire _io_resp_bits_bridx_T_28 = _io_resp_bits_bridx_T & brIdx_0; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_29 = _io_resp_bits_bridx_T_1 & brIdx_1; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_30 = _io_resp_bits_bridx_T_2 & brIdx_2; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_31 = _io_resp_bits_bridx_T_3 & brIdx_3; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_32 = _io_resp_bits_bridx_T_4 & brIdx_4; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_33 = _io_resp_bits_bridx_T_5 & brIdx_5; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_34 = _io_resp_bits_bridx_T_6 & brIdx_6; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_35 = _io_resp_bits_bridx_T_7 & brIdx_7; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_36 = _io_resp_bits_bridx_T_8 & brIdx_8; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_37 = _io_resp_bits_bridx_T_9 & brIdx_9; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_38 = _io_resp_bits_bridx_T_10 & brIdx_10; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_39 = _io_resp_bits_bridx_T_11 & brIdx_11; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_40 = _io_resp_bits_bridx_T_12 & brIdx_12; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_41 = _io_resp_bits_bridx_T_13 & brIdx_13; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_42 = _io_resp_bits_bridx_T_14 & brIdx_14; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_43 = _io_resp_bits_bridx_T_15 & brIdx_15; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_44 = _io_resp_bits_bridx_T_16 & brIdx_16; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_45 = _io_resp_bits_bridx_T_17 & brIdx_17; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_46 = _io_resp_bits_bridx_T_18 & brIdx_18; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_47 = _io_resp_bits_bridx_T_19 & brIdx_19; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_48 = _io_resp_bits_bridx_T_20 & brIdx_20; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_49 = _io_resp_bits_bridx_T_21 & brIdx_21; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_50 = _io_resp_bits_bridx_T_22 & brIdx_22; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_51 = _io_resp_bits_bridx_T_23 & brIdx_23; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_52 = _io_resp_bits_bridx_T_24 & brIdx_24; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_53 = _io_resp_bits_bridx_T_25 & brIdx_25; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_54 = _io_resp_bits_bridx_T_26 & brIdx_26; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_55 = _io_resp_bits_bridx_T_27 & brIdx_27; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_56 = _io_resp_bits_bridx_T_28 | _io_resp_bits_bridx_T_29; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_57 = _io_resp_bits_bridx_T_56 | _io_resp_bits_bridx_T_30; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_58 = _io_resp_bits_bridx_T_57 | _io_resp_bits_bridx_T_31; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_59 = _io_resp_bits_bridx_T_58 | _io_resp_bits_bridx_T_32; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_60 = _io_resp_bits_bridx_T_59 | _io_resp_bits_bridx_T_33; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_61 = _io_resp_bits_bridx_T_60 | _io_resp_bits_bridx_T_34; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_62 = _io_resp_bits_bridx_T_61 | _io_resp_bits_bridx_T_35; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_63 = _io_resp_bits_bridx_T_62 | _io_resp_bits_bridx_T_36; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_64 = _io_resp_bits_bridx_T_63 | _io_resp_bits_bridx_T_37; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_65 = _io_resp_bits_bridx_T_64 | _io_resp_bits_bridx_T_38; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_66 = _io_resp_bits_bridx_T_65 | _io_resp_bits_bridx_T_39; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_67 = _io_resp_bits_bridx_T_66 | _io_resp_bits_bridx_T_40; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_68 = _io_resp_bits_bridx_T_67 | _io_resp_bits_bridx_T_41; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_69 = _io_resp_bits_bridx_T_68 | _io_resp_bits_bridx_T_42; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_70 = _io_resp_bits_bridx_T_69 | _io_resp_bits_bridx_T_43; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_71 = _io_resp_bits_bridx_T_70 | _io_resp_bits_bridx_T_44; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_72 = _io_resp_bits_bridx_T_71 | _io_resp_bits_bridx_T_45; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_73 = _io_resp_bits_bridx_T_72 | _io_resp_bits_bridx_T_46; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_74 = _io_resp_bits_bridx_T_73 | _io_resp_bits_bridx_T_47; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_75 = _io_resp_bits_bridx_T_74 | _io_resp_bits_bridx_T_48; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_76 = _io_resp_bits_bridx_T_75 | _io_resp_bits_bridx_T_49; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_77 = _io_resp_bits_bridx_T_76 | _io_resp_bits_bridx_T_50; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_78 = _io_resp_bits_bridx_T_77 | _io_resp_bits_bridx_T_51; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_79 = _io_resp_bits_bridx_T_78 | _io_resp_bits_bridx_T_52; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_80 = _io_resp_bits_bridx_T_79 | _io_resp_bits_bridx_T_53; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_81 = _io_resp_bits_bridx_T_80 | _io_resp_bits_bridx_T_54; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_82 = _io_resp_bits_bridx_T_81 | _io_resp_bits_bridx_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_bridx_WIRE = _io_resp_bits_bridx_T_82; // @[Mux.scala:30:73] assign io_resp_bits_bridx_0 = _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_mask_T = ~io_resp_bits_bridx_0; // @[BTB.scala:187:7, :292:61] wire _io_resp_bits_mask_T_1 = io_resp_bits_taken_0 & _io_resp_bits_mask_T; // @[BTB.scala:187:7, :292:{40,61}] wire _io_resp_bits_mask_T_2 = ~_io_resp_bits_mask_T_1; // @[BTB.scala:292:{36,40}] wire [1:0] _io_resp_bits_mask_T_3 = 2'h1 << _io_resp_bits_mask_T_2; // @[BTB.scala:292:{33,36}] wire [2:0] _io_resp_bits_mask_T_4 = {1'h0, _io_resp_bits_mask_T_3} - 3'h1; // @[BTB.scala:292:{33,87}] wire [1:0] _io_resp_bits_mask_T_5 = _io_resp_bits_mask_T_4[1:0]; // @[BTB.scala:292:87] wire [2:0] _io_resp_bits_mask_T_6 = {_io_resp_bits_mask_T_5, 1'h1}; // @[BTB.scala:187:7, :292:{27,87}] assign io_resp_bits_mask_0 = _io_resp_bits_mask_T_6[1:0]; // @[BTB.scala:187:7, :292:{21,27}] wire [1:0] _io_resp_bits_cfiType_T_28 = _io_resp_bits_cfiType_T ? cfiType_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_29 = _io_resp_bits_cfiType_T_1 ? cfiType_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_30 = _io_resp_bits_cfiType_T_2 ? cfiType_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_31 = _io_resp_bits_cfiType_T_3 ? cfiType_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_32 = _io_resp_bits_cfiType_T_4 ? cfiType_4 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_33 = _io_resp_bits_cfiType_T_5 ? cfiType_5 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_34 = _io_resp_bits_cfiType_T_6 ? cfiType_6 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_35 = _io_resp_bits_cfiType_T_7 ? cfiType_7 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_36 = _io_resp_bits_cfiType_T_8 ? cfiType_8 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_37 = _io_resp_bits_cfiType_T_9 ? cfiType_9 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_38 = _io_resp_bits_cfiType_T_10 ? cfiType_10 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_39 = _io_resp_bits_cfiType_T_11 ? cfiType_11 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_40 = _io_resp_bits_cfiType_T_12 ? cfiType_12 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_41 = _io_resp_bits_cfiType_T_13 ? cfiType_13 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_42 = _io_resp_bits_cfiType_T_14 ? cfiType_14 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_43 = _io_resp_bits_cfiType_T_15 ? cfiType_15 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_44 = _io_resp_bits_cfiType_T_16 ? cfiType_16 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_45 = _io_resp_bits_cfiType_T_17 ? cfiType_17 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_46 = _io_resp_bits_cfiType_T_18 ? cfiType_18 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_47 = _io_resp_bits_cfiType_T_19 ? cfiType_19 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_48 = _io_resp_bits_cfiType_T_20 ? cfiType_20 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_49 = _io_resp_bits_cfiType_T_21 ? cfiType_21 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_50 = _io_resp_bits_cfiType_T_22 ? cfiType_22 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_51 = _io_resp_bits_cfiType_T_23 ? cfiType_23 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_52 = _io_resp_bits_cfiType_T_24 ? cfiType_24 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_53 = _io_resp_bits_cfiType_T_25 ? cfiType_25 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_54 = _io_resp_bits_cfiType_T_26 ? cfiType_26 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_55 = _io_resp_bits_cfiType_T_27 ? cfiType_27 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_56 = _io_resp_bits_cfiType_T_28 | _io_resp_bits_cfiType_T_29; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_57 = _io_resp_bits_cfiType_T_56 | _io_resp_bits_cfiType_T_30; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_58 = _io_resp_bits_cfiType_T_57 | _io_resp_bits_cfiType_T_31; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_59 = _io_resp_bits_cfiType_T_58 | _io_resp_bits_cfiType_T_32; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_60 = _io_resp_bits_cfiType_T_59 | _io_resp_bits_cfiType_T_33; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_61 = _io_resp_bits_cfiType_T_60 | _io_resp_bits_cfiType_T_34; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_62 = _io_resp_bits_cfiType_T_61 | _io_resp_bits_cfiType_T_35; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_63 = _io_resp_bits_cfiType_T_62 | _io_resp_bits_cfiType_T_36; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_64 = _io_resp_bits_cfiType_T_63 | _io_resp_bits_cfiType_T_37; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_65 = _io_resp_bits_cfiType_T_64 | _io_resp_bits_cfiType_T_38; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_66 = _io_resp_bits_cfiType_T_65 | _io_resp_bits_cfiType_T_39; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_67 = _io_resp_bits_cfiType_T_66 | _io_resp_bits_cfiType_T_40; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_68 = _io_resp_bits_cfiType_T_67 | _io_resp_bits_cfiType_T_41; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_69 = _io_resp_bits_cfiType_T_68 | _io_resp_bits_cfiType_T_42; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_70 = _io_resp_bits_cfiType_T_69 | _io_resp_bits_cfiType_T_43; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_71 = _io_resp_bits_cfiType_T_70 | _io_resp_bits_cfiType_T_44; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_72 = _io_resp_bits_cfiType_T_71 | _io_resp_bits_cfiType_T_45; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_73 = _io_resp_bits_cfiType_T_72 | _io_resp_bits_cfiType_T_46; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_74 = _io_resp_bits_cfiType_T_73 | _io_resp_bits_cfiType_T_47; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_75 = _io_resp_bits_cfiType_T_74 | _io_resp_bits_cfiType_T_48; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_76 = _io_resp_bits_cfiType_T_75 | _io_resp_bits_cfiType_T_49; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_77 = _io_resp_bits_cfiType_T_76 | _io_resp_bits_cfiType_T_50; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_78 = _io_resp_bits_cfiType_T_77 | _io_resp_bits_cfiType_T_51; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_79 = _io_resp_bits_cfiType_T_78 | _io_resp_bits_cfiType_T_52; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_80 = _io_resp_bits_cfiType_T_79 | _io_resp_bits_cfiType_T_53; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_81 = _io_resp_bits_cfiType_T_80 | _io_resp_bits_cfiType_T_54; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_82 = _io_resp_bits_cfiType_T_81 | _io_resp_bits_cfiType_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_cfiType_WIRE = _io_resp_bits_cfiType_T_82; // @[Mux.scala:30:73] assign io_resp_bits_cfiType_0 = _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire leftOne = idxHit[0]; // @[Misc.scala:178:18, :181:37] wire leftOne_1 = idxHit[1]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne = idxHit[2]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_1 = leftOne_1 | rightOne; // @[Misc.scala:178:18, :183:16] wire rightTwo = leftOne_1 & rightOne; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_2 = leftOne | rightOne_1; // @[Misc.scala:178:18, :183:16] wire leftTwo = rightTwo | leftOne & rightOne_1; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_3 = idxHit[3]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_2 = idxHit[4]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_4 = leftOne_3 | rightOne_2; // @[Misc.scala:178:18, :183:16] wire leftTwo_1 = leftOne_3 & rightOne_2; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_5 = idxHit[5]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_3 = idxHit[6]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_4 = leftOne_5 | rightOne_3; // @[Misc.scala:178:18, :183:16] wire rightTwo_1 = leftOne_5 & rightOne_3; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_5 = leftOne_4 | rightOne_4; // @[Misc.scala:183:16] wire rightTwo_2 = leftTwo_1 | rightTwo_1 | leftOne_4 & rightOne_4; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_6 = leftOne_2 | rightOne_5; // @[Misc.scala:183:16] wire leftTwo_2 = leftTwo | rightTwo_2 | leftOne_2 & rightOne_5; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_7 = idxHit[7]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_8 = idxHit[8]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_6 = idxHit[9]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_7 = leftOne_8 | rightOne_6; // @[Misc.scala:178:18, :183:16] wire rightTwo_3 = leftOne_8 & rightOne_6; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_9 = leftOne_7 | rightOne_7; // @[Misc.scala:178:18, :183:16] wire leftTwo_3 = rightTwo_3 | leftOne_7 & rightOne_7; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_10 = idxHit[10]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_8 = idxHit[11]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_11 = leftOne_10 | rightOne_8; // @[Misc.scala:178:18, :183:16] wire leftTwo_4 = leftOne_10 & rightOne_8; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_12 = idxHit[12]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_9 = idxHit[13]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_10 = leftOne_12 | rightOne_9; // @[Misc.scala:178:18, :183:16] wire rightTwo_4 = leftOne_12 & rightOne_9; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_11 = leftOne_11 | rightOne_10; // @[Misc.scala:183:16] wire rightTwo_5 = leftTwo_4 | rightTwo_4 | leftOne_11 & rightOne_10; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_12 = leftOne_9 | rightOne_11; // @[Misc.scala:183:16] wire rightTwo_6 = leftTwo_3 | rightTwo_5 | leftOne_9 & rightOne_11; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_13 = leftOne_6 | rightOne_12; // @[Misc.scala:183:16] wire leftTwo_5 = leftTwo_2 | rightTwo_6 | leftOne_6 & rightOne_12; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_14 = idxHit[14]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_15 = idxHit[15]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_13 = idxHit[16]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_14 = leftOne_15 | rightOne_13; // @[Misc.scala:178:18, :183:16] wire rightTwo_7 = leftOne_15 & rightOne_13; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_16 = leftOne_14 | rightOne_14; // @[Misc.scala:178:18, :183:16] wire leftTwo_6 = rightTwo_7 | leftOne_14 & rightOne_14; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_17 = idxHit[17]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_15 = idxHit[18]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_18 = leftOne_17 | rightOne_15; // @[Misc.scala:178:18, :183:16] wire leftTwo_7 = leftOne_17 & rightOne_15; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_19 = idxHit[19]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_16 = idxHit[20]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_17 = leftOne_19 | rightOne_16; // @[Misc.scala:178:18, :183:16] wire rightTwo_8 = leftOne_19 & rightOne_16; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_18 = leftOne_18 | rightOne_17; // @[Misc.scala:183:16] wire rightTwo_9 = leftTwo_7 | rightTwo_8 | leftOne_18 & rightOne_17; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_20 = leftOne_16 | rightOne_18; // @[Misc.scala:183:16] wire leftTwo_8 = leftTwo_6 | rightTwo_9 | leftOne_16 & rightOne_18; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_21 = idxHit[21]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_22 = idxHit[22]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_19 = idxHit[23]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_20 = leftOne_22 | rightOne_19; // @[Misc.scala:178:18, :183:16] wire rightTwo_10 = leftOne_22 & rightOne_19; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_23 = leftOne_21 | rightOne_20; // @[Misc.scala:178:18, :183:16] wire leftTwo_9 = rightTwo_10 | leftOne_21 & rightOne_20; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_24 = idxHit[24]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_21 = idxHit[25]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_25 = leftOne_24 | rightOne_21; // @[Misc.scala:178:18, :183:16] wire leftTwo_10 = leftOne_24 & rightOne_21; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_26 = idxHit[26]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_22 = idxHit[27]; // @[Misc.scala:178:18, :182:39] wire rightOne_23 = leftOne_26 | rightOne_22; // @[Misc.scala:178:18, :183:16] wire rightTwo_11 = leftOne_26 & rightOne_22; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_24 = leftOne_25 | rightOne_23; // @[Misc.scala:183:16] wire rightTwo_12 = leftTwo_10 | rightTwo_11 | leftOne_25 & rightOne_23; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_25 = leftOne_23 | rightOne_24; // @[Misc.scala:183:16] wire rightTwo_13 = leftTwo_9 | rightTwo_12 | leftOne_23 & rightOne_24; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_26 = leftOne_20 | rightOne_25; // @[Misc.scala:183:16] wire rightTwo_14 = leftTwo_8 | rightTwo_13 | leftOne_20 & rightOne_25; // @[Misc.scala:183:{16,37,49,61}] wire [27:0] _isValid_T_4 = ~idxHit; // @[BTB.scala:218:32, :297:26] wire [27:0] _isValid_T_5 = isValid & _isValid_T_4; // @[BTB.scala:207:24, :297:{24,26}] reg [7:0] history; // @[BTB.scala:117:24] assign res_history = history; // @[BTB.scala:91:19, :117:24] reg [9:0] reset_waddr; // @[BTB.scala:119:36] wire _resetting_T = reset_waddr[9]; // @[BTB.scala:119:36, :120:39] wire resetting = ~_resetting_T; // @[BTB.scala:120:{27,39}] wire wen; // @[BTB.scala:121:29] wire [9:0] waddr_1; // @[BTB.scala:122:31] wire wdata; // @[BTB.scala:123:31] wire [10:0] _reset_waddr_T = {1'h0, reset_waddr} + 11'h1; // @[BTB.scala:119:36, :124:49] wire [9:0] _reset_waddr_T_1 = _reset_waddr_T[9:0]; // @[BTB.scala:124:49] wire _isBranch_T = cfiType_0 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_1 = cfiType_1 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_2 = cfiType_2 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_3 = cfiType_3 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_4 = cfiType_4 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_5 = cfiType_5 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_6 = cfiType_6 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_7 = cfiType_7 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_8 = cfiType_8 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_9 = cfiType_9 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_10 = cfiType_10 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_11 = cfiType_11 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_12 = cfiType_12 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_13 = cfiType_13 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_14 = cfiType_14 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_15 = cfiType_15 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_16 = cfiType_16 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_17 = cfiType_17 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_18 = cfiType_18 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_19 = cfiType_19 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_20 = cfiType_20 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_21 = cfiType_21 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_22 = cfiType_22 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_23 = cfiType_23 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_24 = cfiType_24 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_25 = cfiType_25 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_26 = cfiType_26 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_27 = cfiType_27 == 2'h0; // @[BTB.scala:208:20, :305:44] wire [1:0] isBranch_lo_lo_lo_hi = {_isBranch_T_2, _isBranch_T_1}; // @[package.scala:45:27] wire [2:0] isBranch_lo_lo_lo = {isBranch_lo_lo_lo_hi, _isBranch_T}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_lo = {_isBranch_T_4, _isBranch_T_3}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_hi = {_isBranch_T_6, _isBranch_T_5}; // @[package.scala:45:27] wire [3:0] isBranch_lo_lo_hi = {isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_lo = {isBranch_lo_lo_hi, isBranch_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_lo_hi = {_isBranch_T_9, _isBranch_T_8}; // @[package.scala:45:27] wire [2:0] isBranch_lo_hi_lo = {isBranch_lo_hi_lo_hi, _isBranch_T_7}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_lo = {_isBranch_T_11, _isBranch_T_10}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_hi = {_isBranch_T_13, _isBranch_T_12}; // @[package.scala:45:27] wire [3:0] isBranch_lo_hi_hi = {isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_hi = {isBranch_lo_hi_hi, isBranch_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_lo = {isBranch_lo_hi, isBranch_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_lo_hi = {_isBranch_T_16, _isBranch_T_15}; // @[package.scala:45:27] wire [2:0] isBranch_hi_lo_lo = {isBranch_hi_lo_lo_hi, _isBranch_T_14}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_lo = {_isBranch_T_18, _isBranch_T_17}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_hi = {_isBranch_T_20, _isBranch_T_19}; // @[package.scala:45:27] wire [3:0] isBranch_hi_lo_hi = {isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_lo = {isBranch_hi_lo_hi, isBranch_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_lo_hi = {_isBranch_T_23, _isBranch_T_22}; // @[package.scala:45:27] wire [2:0] isBranch_hi_hi_lo = {isBranch_hi_hi_lo_hi, _isBranch_T_21}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_lo = {_isBranch_T_25, _isBranch_T_24}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_hi = {_isBranch_T_27, _isBranch_T_26}; // @[package.scala:45:27] wire [3:0] isBranch_hi_hi_hi = {isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_hi = {isBranch_hi_hi_hi, isBranch_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_hi = {isBranch_hi_hi, isBranch_hi_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_28 = {isBranch_hi, isBranch_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_29 = idxHit & _isBranch_T_28; // @[package.scala:45:27] wire isBranch = |_isBranch_T_29; // @[BTB.scala:305:{28,72}] assign io_resp_bits_bht_history_0 = res_history; // @[BTB.scala:91:19, :187:7] wire _res_res_value_T_8; // @[BTB.scala:92:21] assign io_resp_bits_bht_value_0 = res_value; // @[BTB.scala:91:19, :187:7] wire [45:0] res_res_value_hi = io_req_bits_addr_0[47:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _res_res_value_T = res_res_value_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [36:0] _res_res_value_T_1 = res_res_value_hi[45:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _res_res_value_T_2 = _res_res_value_T_1[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _res_res_value_T_3 = {_res_res_value_T[8:2], _res_res_value_T[1:0] ^ _res_res_value_T_2}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _res_res_value_T_4 = {8'h0, history} * 16'hDD; // @[BTB.scala:82:12, :117:24] wire [2:0] _res_res_value_T_5 = _res_res_value_T_4[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _res_res_value_T_6 = {_res_res_value_T_5, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _res_res_value_T_7 = _res_res_value_T_3 ^ _res_res_value_T_6; // @[BTB.scala:86:42, :88:{20,44}] assign _res_res_value_T_8 = ~resetting & _table_ext_R0_data; // @[BTB.scala:92:21, :116:26, :120:27] assign res_value = _res_res_value_T_8; // @[BTB.scala:91:19, :92:21] wire [6:0] _history_T = history[7:1]; // @[BTB.scala:113:35, :117:24] wire [7:0] _history_T_1 = {io_bht_advance_bits_bht_value_0, _history_T}; // @[BTB.scala:113:{19,35}, :187:7] wire _GEN = io_bht_update_valid_0 & io_bht_update_bits_branch_0; // @[BTB.scala:97:9, :121:29, :187:7, :310:32, :311:40] assign wen = _GEN | resetting; // @[BTB.scala:97:9, :120:27, :121:29, :310:32, :311:40] wire [45:0] waddr_hi = io_bht_update_bits_pc_0[47:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _waddr_T_40 = waddr_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [36:0] _waddr_T_41 = waddr_hi[45:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _waddr_T_42 = _waddr_T_41[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _waddr_T_43 = {_waddr_T_40[8:2], _waddr_T_40[1:0] ^ _waddr_T_42}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _waddr_T_44 = {8'h0, io_bht_update_bits_prediction_history_0} * 16'hDD; // @[BTB.scala:82:12, :187:7] wire [2:0] _waddr_T_45 = _waddr_T_44[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _waddr_T_46 = {_waddr_T_45, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _waddr_T_47 = _waddr_T_43 ^ _waddr_T_46; // @[BTB.scala:86:42, :88:{20,44}] assign waddr_1 = io_bht_update_valid_0 & io_bht_update_bits_branch_0 & ~resetting ? {1'h0, _waddr_T_47} : reset_waddr; // @[BTB.scala:88:20, :98:{11,23}, :99:13, :119:36, :120:27, :122:31, :187:7, :310:32, :311:40] assign wdata = _GEN & ~resetting & io_bht_update_bits_taken_0; // @[BTB.scala:97:9, :98:{11,23}, :100:13, :120:27, :121:29, :123:31, :187:7, :310:32, :311:40] wire [6:0] _history_T_2 = io_bht_update_bits_prediction_history_0[7:1]; // @[BTB.scala:110:37, :187:7] wire [7:0] _history_T_3 = {io_bht_update_bits_taken_0, _history_T_2}; // @[BTB.scala:110:{19,37}, :187:7] assign io_resp_bits_taken_0 = ~(~res_value & isBranch); // @[BTB.scala:91:19, :187:7, :288:22, :305:72, :320:{11,22,35,56}] reg [2:0] count; // @[BTB.scala:56:30] reg [2:0] pos; // @[BTB.scala:57:28] reg [47:0] stack_0; // @[BTB.scala:58:26] reg [47:0] stack_1; // @[BTB.scala:58:26] reg [47:0] stack_2; // @[BTB.scala:58:26] reg [47:0] stack_3; // @[BTB.scala:58:26] reg [47:0] stack_4; // @[BTB.scala:58:26] reg [47:0] stack_5; // @[BTB.scala:58:26] wire _doPeek_T = &cfiType_0; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_1 = &cfiType_1; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_2 = &cfiType_2; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_3 = &cfiType_3; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_4 = &cfiType_4; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_5 = &cfiType_5; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_6 = &cfiType_6; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_7 = &cfiType_7; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_8 = &cfiType_8; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_9 = &cfiType_9; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_10 = &cfiType_10; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_11 = &cfiType_11; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_12 = &cfiType_12; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_13 = &cfiType_13; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_14 = &cfiType_14; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_15 = &cfiType_15; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_16 = &cfiType_16; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_17 = &cfiType_17; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_18 = &cfiType_18; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_19 = &cfiType_19; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_20 = &cfiType_20; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_21 = &cfiType_21; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_22 = &cfiType_22; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_23 = &cfiType_23; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_24 = &cfiType_24; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_25 = &cfiType_25; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_26 = &cfiType_26; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_27 = &cfiType_27; // @[BTB.scala:208:20, :326:42] wire [1:0] doPeek_lo_lo_lo_hi = {_doPeek_T_2, _doPeek_T_1}; // @[package.scala:45:27] wire [2:0] doPeek_lo_lo_lo = {doPeek_lo_lo_lo_hi, _doPeek_T}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_lo = {_doPeek_T_4, _doPeek_T_3}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_hi = {_doPeek_T_6, _doPeek_T_5}; // @[package.scala:45:27] wire [3:0] doPeek_lo_lo_hi = {doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_lo = {doPeek_lo_lo_hi, doPeek_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_lo_hi = {_doPeek_T_9, _doPeek_T_8}; // @[package.scala:45:27] wire [2:0] doPeek_lo_hi_lo = {doPeek_lo_hi_lo_hi, _doPeek_T_7}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_lo = {_doPeek_T_11, _doPeek_T_10}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_hi = {_doPeek_T_13, _doPeek_T_12}; // @[package.scala:45:27] wire [3:0] doPeek_lo_hi_hi = {doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_hi = {doPeek_lo_hi_hi, doPeek_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_lo = {doPeek_lo_hi, doPeek_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_lo_hi = {_doPeek_T_16, _doPeek_T_15}; // @[package.scala:45:27] wire [2:0] doPeek_hi_lo_lo = {doPeek_hi_lo_lo_hi, _doPeek_T_14}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_lo = {_doPeek_T_18, _doPeek_T_17}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_hi = {_doPeek_T_20, _doPeek_T_19}; // @[package.scala:45:27] wire [3:0] doPeek_hi_lo_hi = {doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_lo = {doPeek_hi_lo_hi, doPeek_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_lo_hi = {_doPeek_T_23, _doPeek_T_22}; // @[package.scala:45:27] wire [2:0] doPeek_hi_hi_lo = {doPeek_hi_hi_lo_hi, _doPeek_T_21}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_lo = {_doPeek_T_25, _doPeek_T_24}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_hi = {_doPeek_T_27, _doPeek_T_26}; // @[package.scala:45:27] wire [3:0] doPeek_hi_hi_hi = {doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_hi = {doPeek_hi_hi_hi, doPeek_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_hi = {doPeek_hi_hi, doPeek_hi_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_28 = {doPeek_hi, doPeek_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_29 = idxHit & _doPeek_T_28; // @[package.scala:45:27] wire doPeek = |_doPeek_T_29; // @[BTB.scala:326:{26,67}] wire _io_ras_head_valid_T = ~(|count); // @[BTB.scala:54:29, :56:30] assign _io_ras_head_valid_T_1 = ~_io_ras_head_valid_T; // @[BTB.scala:54:29, :327:26] assign io_ras_head_valid_0 = _io_ras_head_valid_T_1; // @[BTB.scala:187:7, :327:26] wire [7:0][47:0] _GEN_0 = {{stack_0}, {stack_0}, {stack_5}, {stack_4}, {stack_3}, {stack_2}, {stack_1}, {stack_0}}; // @[BTB.scala:58:26, :328:22] assign io_ras_head_bits_0 = _GEN_0[pos]; // @[BTB.scala:57:28, :187:7, :328:22] assign io_resp_bits_target_0 = (|count) & doPeek ? io_ras_head_bits_0 : _io_resp_bits_target_T_181; // @[BTB.scala:54:29, :56:30, :187:7, :289:{23,29}, :326:67, :329:{24,35}, :330:27] wire [3:0] _GEN_1 = {1'h0, count}; // @[BTB.scala:43:44, :56:30] wire [3:0] _count_T = _GEN_1 + 4'h1; // @[BTB.scala:43:44] wire [2:0] _count_T_1 = _count_T[2:0]; // @[BTB.scala:43:44] wire _nextPos_T = pos < 3'h5; // @[BTB.scala:44:47, :57:28] wire _nextPos_T_1 = _nextPos_T; // @[BTB.scala:44:{40,47}] wire [3:0] _GEN_2 = {1'h0, pos}; // @[BTB.scala:44:64, :57:28] wire [3:0] _nextPos_T_2 = _GEN_2 + 4'h1; // @[BTB.scala:44:64] wire [2:0] _nextPos_T_3 = _nextPos_T_2[2:0]; // @[BTB.scala:44:64] wire [2:0] nextPos = _nextPos_T_1 ? _nextPos_T_3 : 3'h0; // @[BTB.scala:44:{22,40,64}, :51:40] wire [3:0] _count_T_2 = _GEN_1 - 4'h1; // @[BTB.scala:43:44, :50:20] wire [2:0] _count_T_3 = _count_T_2[2:0]; // @[BTB.scala:50:20] wire _pos_T = |pos; // @[BTB.scala:51:40, :57:28] wire _pos_T_1 = _pos_T; // @[BTB.scala:51:{33,40}] wire [3:0] _pos_T_2 = _GEN_2 - 4'h1; // @[BTB.scala:44:64, :51:50] wire [2:0] _pos_T_3 = _pos_T_2[2:0]; // @[BTB.scala:51:50] wire [2:0] _pos_T_4 = _pos_T_1 ? _pos_T_3 : 3'h5; // @[BTB.scala:51:{15,33,50}] wire [4:0] _T_5 = idxWritesEven ? idxPageReplEn[4:0] : tgtPageReplEn[4:0]; // @[BTB.scala:241:26, :247:26, :274:25, :280:24] wire [33:0] _T_8 = idxWritesEven ? r_btb_update_bits_pc[47:14] : io_req_bits_addr_0[47:14]; // @[Valid.scala:135:21] wire [4:0] _T_12 = idxWritesEven ? tgtPageReplEn[5:1] : idxPageReplEn[5:1]; // @[BTB.scala:241:26, :247:26, :274:25, :282:24] wire [33:0] _T_15 = idxWritesEven ? io_req_bits_addr_0[47:14] : r_btb_update_bits_pc[47:14]; // @[Valid.scala:135:21] wire _T_139 = io_ras_update_bits_cfiType_0 == 2'h2; // @[BTB.scala:187:7, :333:40] always @(posedge clock) begin // @[BTB.scala:187:7] if (r_btb_update_valid & waddr == 5'h0) begin // @[Valid.scala:135:21] idxs_0 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_0 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_0 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_0 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_0 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_0 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1) begin // @[Valid.scala:135:21] idxs_1 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_1 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_1 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_1 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_1 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_1 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h2) begin // @[Valid.scala:135:21] idxs_2 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_2 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_2 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_2 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_2 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_2 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h3) begin // @[Valid.scala:135:21] idxs_3 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_3 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_3 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_3 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_3 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_3 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h4) begin // @[Valid.scala:135:21] idxs_4 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_4 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_4 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_4 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_4 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_4 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h5) begin // @[Valid.scala:135:21] idxs_5 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_5 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_5 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_5 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_5 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_5 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h6) begin // @[Valid.scala:135:21] idxs_6 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_6 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_6 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_6 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_6 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_6 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h7) begin // @[Valid.scala:135:21] idxs_7 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_7 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_7 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_7 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_7 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_7 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h8) begin // @[Valid.scala:135:21] idxs_8 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_8 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_8 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_8 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_8 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_8 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h9) begin // @[Valid.scala:135:21] idxs_9 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_9 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_9 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_9 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_9 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_9 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hA) begin // @[Valid.scala:135:21] idxs_10 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_10 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_10 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_10 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_10 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_10 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hB) begin // @[Valid.scala:135:21] idxs_11 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_11 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_11 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_11 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_11 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_11 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hC) begin // @[Valid.scala:135:21] idxs_12 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_12 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_12 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_12 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_12 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_12 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hD) begin // @[Valid.scala:135:21] idxs_13 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_13 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_13 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_13 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_13 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_13 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hE) begin // @[Valid.scala:135:21] idxs_14 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_14 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_14 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_14 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_14 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_14 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hF) begin // @[Valid.scala:135:21] idxs_15 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_15 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_15 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_15 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_15 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_15 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h10) begin // @[Valid.scala:135:21] idxs_16 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_16 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_16 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_16 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_16 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_16 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h11) begin // @[Valid.scala:135:21] idxs_17 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_17 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_17 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_17 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_17 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_17 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h12) begin // @[Valid.scala:135:21] idxs_18 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_18 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_18 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_18 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_18 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_18 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h13) begin // @[Valid.scala:135:21] idxs_19 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_19 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_19 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_19 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_19 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_19 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h14) begin // @[Valid.scala:135:21] idxs_20 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_20 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_20 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_20 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_20 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_20 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h15) begin // @[Valid.scala:135:21] idxs_21 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_21 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_21 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_21 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_21 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_21 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h16) begin // @[Valid.scala:135:21] idxs_22 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_22 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_22 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_22 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_22 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_22 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h17) begin // @[Valid.scala:135:21] idxs_23 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_23 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_23 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_23 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_23 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_23 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h18) begin // @[Valid.scala:135:21] idxs_24 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_24 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_24 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_24 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_24 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_24 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h19) begin // @[Valid.scala:135:21] idxs_25 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_25 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_25 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_25 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_25 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_25 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1A) begin // @[Valid.scala:135:21] idxs_26 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_26 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_26 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_26 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_26 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_26 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1B) begin // @[Valid.scala:135:21] idxs_27 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_27 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_27 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_27 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_27 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_27 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & _T_5[0]) // @[Valid.scala:135:21] pages_0 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[0]) // @[Valid.scala:135:21] pages_1 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[2]) // @[Valid.scala:135:21] pages_2 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[2]) // @[Valid.scala:135:21] pages_3 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[4]) // @[Valid.scala:135:21] pages_4 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[4]) // @[Valid.scala:135:21] pages_5 <= _T_15; // @[BTB.scala:203:18, :283:10] if (io_btb_update_valid_0) begin // @[BTB.scala:187:7] r_btb_update_pipe_b_prediction_cfiType <= io_btb_update_bits_prediction_cfiType_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_taken <= io_btb_update_bits_prediction_taken_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_mask <= io_btb_update_bits_prediction_mask_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bridx <= io_btb_update_bits_prediction_bridx_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_target <= io_btb_update_bits_prediction_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_entry <= io_btb_update_bits_prediction_entry_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_history <= io_btb_update_bits_prediction_bht_history_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_value <= io_btb_update_bits_prediction_bht_value_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_pc <= io_btb_update_bits_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_target <= io_btb_update_bits_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_isValid <= io_btb_update_bits_isValid_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_br_pc <= io_btb_update_bits_br_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_cfiType <= io_btb_update_bits_cfiType_0; // @[Valid.scala:142:26] end if (io_resp_valid_0) begin // @[BTB.scala:187:7] r_resp_pipe_b_cfiType <= io_resp_bits_cfiType_0; // @[Valid.scala:142:26] r_resp_pipe_b_taken <= io_resp_bits_taken_0; // @[Valid.scala:142:26] r_resp_pipe_b_mask <= io_resp_bits_mask_0; // @[Valid.scala:142:26] r_resp_pipe_b_bridx <= io_resp_bits_bridx_0; // @[Valid.scala:142:26] r_resp_pipe_b_target <= io_resp_bits_target_0; // @[Valid.scala:142:26] r_resp_pipe_b_entry <= io_resp_bits_entry_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_history <= io_resp_bits_bht_history_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_value <= io_resp_bits_bht_value_0; // @[Valid.scala:142:26] end if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h0) // @[BTB.scala:44:22, :45:20, :51:40, :58:26, :187:7, :332:32, :333:{40,58}] stack_0 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h1) // @[package.scala:39:86] stack_1 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h2) // @[package.scala:39:86] stack_2 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h3) // @[package.scala:39:86] stack_3 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h4) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_4 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h5) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_5 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (reset) begin // @[BTB.scala:187:7] pageValid <= 6'h0; // @[BTB.scala:204:26] isValid <= 28'h0; // @[BTB.scala:207:24] r_btb_update_pipe_v <= 1'h0; // @[Valid.scala:141:24] nextPageRepl <= 3'h0; // @[BTB.scala:51:40, :237:29] state_reg <= 27'h0; // @[Replacement.scala:168:70] r_resp_pipe_v <= 1'h0; // @[Valid.scala:141:24] history <= 8'h0; // @[BTB.scala:117:24] reset_waddr <= 10'h0; // @[BTB.scala:119:36] count <= 3'h0; // @[BTB.scala:51:40, :56:30] pos <= 3'h0; // @[BTB.scala:51:40, :57:28] end else begin // @[BTB.scala:187:7] if (r_btb_update_valid) // @[Valid.scala:135:21] pageValid <= _pageValid_T_1[5:0]; // @[BTB.scala:204:26, :284:{15,44}] if (io_flush_0) // @[BTB.scala:187:7] isValid <= 28'h0; // @[BTB.scala:207:24] else if (leftTwo_5 | rightTwo_14 | leftOne_13 & rightOne_26) // @[Misc.scala:183:{16,37,49,61}] isValid <= _isValid_T_5; // @[BTB.scala:207:24, :297:24] else if (r_btb_update_valid) // @[Valid.scala:135:21] isValid <= _isValid_T_3[27:0]; // @[BTB.scala:207:24, :269:{13,19}] r_btb_update_pipe_v <= io_btb_update_valid_0; // @[Valid.scala:141:24] if (r_btb_update_valid & (doIdxPageRepl | doTgtPageRepl)) // @[Valid.scala:135:21] nextPageRepl <= _nextPageRepl_T_2; // @[BTB.scala:237:29, :252:24] if (r_resp_valid & r_resp_bits_taken | r_btb_update_valid) // @[Valid.scala:135:21] state_reg <= _state_reg_T_92; // @[Replacement.scala:168:70, :202:12] r_resp_pipe_v <= io_resp_valid_0; // @[Valid.scala:141:24] if (io_bht_update_valid_0 & io_bht_update_bits_mispredict_0) // @[BTB.scala:187:7, :307:33, :310:32, :311:40] history <= io_bht_update_bits_branch_0 ? _history_T_3 : io_bht_update_bits_prediction_history_0; // @[BTB.scala:107:13, :110:{13,19}, :117:24, :187:7, :307:33, :313:46, :316:50] else if (io_bht_advance_valid_0) // @[BTB.scala:187:7] history <= _history_T_1; // @[BTB.scala:113:19, :117:24] if (resetting) // @[BTB.scala:120:27] reset_waddr <= _reset_waddr_T_1; // @[BTB.scala:119:36, :124:49] if (io_ras_update_valid_0) begin // @[BTB.scala:187:7] if (_T_139) begin // @[BTB.scala:333:40] if (count[2:1] != 2'h3) // @[BTB.scala:43:17, :56:30] count <= _count_T_1; // @[BTB.scala:43:44, :56:30] pos <= nextPos; // @[BTB.scala:44:22, :57:28] end else if ((&io_ras_update_bits_cfiType_0) & (|count)) begin // @[BTB.scala:49:37, :50:11, :54:29, :56:30, :187:7, :335:{46,63}] count <= _count_T_3; // @[BTB.scala:50:20, :56:30] pos <= _pos_T_4; // @[BTB.scala:51:15, :57:28] end end end always @(posedge) table_512x1 table_ext ( // @[BTB.scala:116:26] .R0_addr (_res_res_value_T_7), // @[BTB.scala:88:20] .R0_en (1'h1), // @[BTB.scala:187:7] .R0_clk (clock), .R0_data (_table_ext_R0_data), .W0_addr (waddr_1[8:0]), // @[BTB.scala:122:31, :125:21] .W0_en (wen), // @[BTB.scala:121:29] .W0_clk (clock), .W0_data (wdata) // @[BTB.scala:123:31] ); // @[BTB.scala:116:26] assign io_resp_valid = io_resp_valid_0; // @[BTB.scala:187:7] assign io_resp_bits_cfiType = io_resp_bits_cfiType_0; // @[BTB.scala:187:7] assign io_resp_bits_taken = io_resp_bits_taken_0; // @[BTB.scala:187:7] assign io_resp_bits_mask = io_resp_bits_mask_0; // @[BTB.scala:187:7] assign io_resp_bits_bridx = io_resp_bits_bridx_0; // @[BTB.scala:187:7] assign io_resp_bits_target = io_resp_bits_target_0; // @[BTB.scala:187:7] assign io_resp_bits_entry = io_resp_bits_entry_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_history = io_resp_bits_bht_history_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_value = io_resp_bits_bht_value_0; // @[BTB.scala:187:7] assign io_ras_head_valid = io_ras_head_valid_0; // @[BTB.scala:187:7] assign io_ras_head_bits = io_ras_head_bits_0; // @[BTB.scala:187:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLROM : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_55 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in wire rom : UInt<64>[512] connect rom[0], UInt<64>(0h405051300000517) connect rom[1], UInt<64>(0h301022f330551073) connect rom[2], UInt<64>(0h12f2934122d293) connect rom[3], UInt<64>(0h3030107300028863) connect rom[4], UInt<64>(0h3445307322200513) connect rom[5], UInt<64>(0h3045107300800513) connect rom[6], UInt<64>(0h1050007330052073) connect rom[7], UInt<64>(0hffdff06f) connect rom[8], UInt<64>(0hf1402573020005b7) connect rom[9], UInt<64>(0h380006f00050463) connect rom[10], UInt<64>(0h10069300458613) connect rom[11], UInt<64>(0h46061300d62023) connect rom[12], UInt<64>(0hfe069ae3ffc62683) connect rom[13], UInt<64>(0h2c0006f) connect rom[14], UInt<64>(0h0) connect rom[15], UInt<64>(0h0) connect rom[16], UInt<64>(0h5a283f81ff06f) connect rom[17], UInt<64>(0h251513fe029ee3) connect rom[18], UInt<64>(0h5a02300b505b3) connect rom[19], UInt<64>(0h5350300001537) connect rom[20], UInt<64>(0hf140257334151073) connect rom[21], UInt<64>(0h185859300000597) connect rom[22], UInt<64>(0h3006307308000613) connect rom[23], UInt<64>(0h1330200073) connect rom[24], UInt<64>(0he0000edfe0dd0) connect rom[25], UInt<64>(0ha00b000038000000) connect rom[26], UInt<64>(0h1100000028000000) connect rom[27], UInt<64>(0h10000000) connect rom[28], UInt<64>(0h680b000060020000) connect rom[29], UInt<64>(0h0) connect rom[30], UInt<64>(0h0) connect rom[31], UInt<64>(0h1000000) connect rom[32], UInt<64>(0h400000003000000) connect rom[33], UInt<64>(0h100000000000000) connect rom[34], UInt<64>(0h400000003000000) connect rom[35], UInt<64>(0h10000000f000000) connect rom[36], UInt<64>(0h1500000003000000) connect rom[37], UInt<64>(0h2d6263751b000000) connect rom[38], UInt<64>(0h706968632c726162) connect rom[39], UInt<64>(0h7665642d64726179) connect rom[40], UInt<64>(0h300000000000000) connect rom[41], UInt<64>(0h2600000011000000) connect rom[42], UInt<64>(0h2c7261622d626375) connect rom[43], UInt<64>(0h6472617970696863) connect rom[44], UInt<64>(0h100000000000000) connect rom[45], UInt<64>(0h73657361696c61) connect rom[46], UInt<64>(0h1500000003000000) connect rom[47], UInt<64>(0h636f732f2c000000) connect rom[48], UInt<64>(0h406c61697265732f) connect rom[49], UInt<64>(0h3030303032303031) connect rom[50], UInt<64>(0h200000000000000) connect rom[51], UInt<64>(0h736f686301000000) connect rom[52], UInt<64>(0h300000000006e65) connect rom[53], UInt<64>(0h3400000015000000) connect rom[54], UInt<64>(0h7265732f636f732f) connect rom[55], UInt<64>(0h32303031406c6169) connect rom[56], UInt<64>(0h30303030) connect rom[57], UInt<64>(0h100000002000000) connect rom[58], UInt<64>(0h73757063) connect rom[59], UInt<64>(0h400000003000000) connect rom[60], UInt<64>(0h100000000000000) connect rom[61], UInt<64>(0h400000003000000) connect rom[62], UInt<64>(0hf000000) connect rom[63], UInt<64>(0h400000003000000) connect rom[64], UInt<64>(0h20a1070040000000) connect rom[65], UInt<64>(0h4075706301000000) connect rom[66], UInt<64>(0h300000000000030) connect rom[67], UInt<64>(0h5300000004000000) connect rom[68], UInt<64>(0h300000000000000) connect rom[69], UInt<64>(0h1b00000014000000) connect rom[70], UInt<64>(0h2c7261622d626375) connect rom[71], UInt<64>(0h697200306d6f6f62) connect rom[72], UInt<64>(0h300000000766373) connect rom[73], UInt<64>(0h6300000004000000) connect rom[74], UInt<64>(0h300000040000000) connect rom[75], UInt<64>(0h7600000004000000) connect rom[76], UInt<64>(0h300000040000000) connect rom[77], UInt<64>(0h8300000004000000) connect rom[78], UInt<64>(0h300000000800000) connect rom[79], UInt<64>(0h9000000004000000) connect rom[80], UInt<64>(0h300000001000000) connect rom[81], UInt<64>(0h9b00000004000000) connect rom[82], UInt<64>(0h300000010000000) connect rom[83], UInt<64>(0ha600000004000000) connect rom[84], UInt<64>(0h300000000757063) connect rom[85], UInt<64>(0hb200000004000000) connect rom[86], UInt<64>(0h300000000000000) connect rom[87], UInt<64>(0hd100000004000000) connect rom[88], UInt<64>(0h300000040000000) connect rom[89], UInt<64>(0he400000004000000) connect rom[90], UInt<64>(0h300000040000000) connect rom[91], UInt<64>(0hf100000004000000) connect rom[92], UInt<64>(0h300000000800000) connect rom[93], UInt<64>(0hfe00000004000000) connect rom[94], UInt<64>(0h300000001000000) connect rom[95], UInt<64>(0h901000004000000) connect rom[96], UInt<64>(0h300000020000000) connect rom[97], UInt<64>(0h140100000b000000) connect rom[98], UInt<64>(0h76732c7663736972) connect rom[99], UInt<64>(0h300000000003933) connect rom[100], UInt<64>(0h1d01000004000000) connect rom[101], UInt<64>(0h300000001000000) connect rom[102], UInt<64>(0h2e01000004000000) connect rom[103], UInt<64>(0h300000000000000) connect rom[104], UInt<64>(0h320100002c000000) connect rom[105], UInt<64>(0h66616d6934367672) connect rom[106], UInt<64>(0h727363697a626364) connect rom[107], UInt<64>(0h65636e6566697a5f) connect rom[108], UInt<64>(0h5f6d7068697a5f69) connect rom[109], UInt<64>(0h5f62627a5f61627a) connect rom[110], UInt<64>(0h30000000073627a) connect rom[111], UInt<64>(0h3c01000004000000) connect rom[112], UInt<64>(0h300000004000000) connect rom[113], UInt<64>(0h5101000004000000) connect rom[114], UInt<64>(0h300000008000000) connect rom[115], UInt<64>(0h6201000005000000) connect rom[116], UInt<64>(0h79616b6f) connect rom[117], UInt<64>(0h400000003000000) connect rom[118], UInt<64>(0h20a1070040000000) connect rom[119], UInt<64>(0h3000000) connect rom[120], UInt<64>(0h100000069010000) connect rom[121], UInt<64>(0h7075727265746e69) connect rom[122], UInt<64>(0h6f72746e6f632d74) connect rom[123], UInt<64>(0h72656c6c) connect rom[124], UInt<64>(0h400000003000000) connect rom[125], UInt<64>(0h100000073010000) connect rom[126], UInt<64>(0hf00000003000000) connect rom[127], UInt<64>(0h637369721b000000) connect rom[128], UInt<64>(0h6e692d7570632c76) connect rom[129], UInt<64>(0h300000000006374) connect rom[130], UInt<64>(0h8401000000000000) connect rom[131], UInt<64>(0h400000003000000) connect rom[132], UInt<64>(0h400000099010000) connect rom[133], UInt<64>(0h200000002000000) connect rom[134], UInt<64>(0h100000002000000) connect rom[135], UInt<64>(0h66697468) connect rom[136], UInt<64>(0ha00000003000000) connect rom[137], UInt<64>(0h2c6263751b000000) connect rom[138], UInt<64>(0h3066697468) connect rom[139], UInt<64>(0h100000002000000) connect rom[140], UInt<64>(0h384079726f6d656d) connect rom[141], UInt<64>(0h303030303030) connect rom[142], UInt<64>(0h700000003000000) connect rom[143], UInt<64>(0h6f6d656da6000000) connect rom[144], UInt<64>(0h300000000007972) connect rom[145], UInt<64>(0h2e01000008000000) connect rom[146], UInt<64>(0h10000000008) connect rom[147], UInt<64>(0h900000003000000) connect rom[148], UInt<64>(0h6173696462010000) connect rom[149], UInt<64>(0h64656c62) connect rom[150], UInt<64>(0h400000003000000) connect rom[151], UInt<64>(0h300000099010000) connect rom[152], UInt<64>(0h100000002000000) connect rom[153], UInt<64>(0h384079726f6d656d) connect rom[154], UInt<64>(0h30303030303030) connect rom[155], UInt<64>(0h700000003000000) connect rom[156], UInt<64>(0h6f6d656da6000000) connect rom[157], UInt<64>(0h300000000007972) connect rom[158], UInt<64>(0h2e01000008000000) connect rom[159], UInt<64>(0h1000000080) connect rom[160], UInt<64>(0h400000003000000) connect rom[161], UInt<64>(0h200000099010000) connect rom[162], UInt<64>(0h100000002000000) connect rom[163], UInt<64>(0h300000000636f73) connect rom[164], UInt<64>(0h4000000) connect rom[165], UInt<64>(0h300000001000000) connect rom[166], UInt<64>(0hf00000004000000) connect rom[167], UInt<64>(0h300000001000000) connect rom[168], UInt<64>(0h1b00000020000000) connect rom[169], UInt<64>(0h2c7261622d626375) connect rom[170], UInt<64>(0h6472617970696863) connect rom[171], UInt<64>(0h6d697300636f732d) connect rom[172], UInt<64>(0h7375622d656c70) connect rom[173], UInt<64>(0h3000000) connect rom[174], UInt<64>(0h1000000a1010000) connect rom[175], UInt<64>(0h6464612d746f6f62) connect rom[176], UInt<64>(0h6765722d73736572) connect rom[177], UInt<64>(0h3030303140) connect rom[178], UInt<64>(0h800000003000000) connect rom[179], UInt<64>(0h1000002e010000) connect rom[180], UInt<64>(0h300000000100000) connect rom[181], UInt<64>(0ha801000008000000) connect rom[182], UInt<64>(0h6c6f72746e6f63) connect rom[183], UInt<64>(0h100000002000000) connect rom[184], UInt<64>(0h6f632d6568636163) connect rom[185], UInt<64>(0h72656c6c6f72746e) connect rom[186], UInt<64>(0h3030303031303240) connect rom[187], UInt<64>(0h300000000000000) connect rom[188], UInt<64>(0h6500000004000000) connect rom[189], UInt<64>(0h300000040000000) connect rom[190], UInt<64>(0hb201000004000000) connect rom[191], UInt<64>(0h300000002000000) connect rom[192], UInt<64>(0h7800000004000000) connect rom[193], UInt<64>(0h300000000040000) connect rom[194], UInt<64>(0h8500000004000000) connect rom[195], UInt<64>(0h300000000000800) connect rom[196], UInt<64>(0hbe01000000000000) connect rom[197], UInt<64>(0h1d00000003000000) connect rom[198], UInt<64>(0h696669731b000000) connect rom[199], UInt<64>(0h756c636e692c6576) connect rom[200], UInt<64>(0h6863616365766973) connect rom[201], UInt<64>(0h6568636163003065) connect rom[202], UInt<64>(0h300000000000000) connect rom[203], UInt<64>(0h1d01000008000000) connect rom[204], UInt<64>(0h300000002000000) connect rom[205], UInt<64>(0h800000003000000) connect rom[206], UInt<64>(0h1022e010000) connect rom[207], UInt<64>(0h300000000100000) connect rom[208], UInt<64>(0ha801000008000000) connect rom[209], UInt<64>(0h6c6f72746e6f63) connect rom[210], UInt<64>(0h400000003000000) connect rom[211], UInt<64>(0hc000000cc010000) connect rom[212], UInt<64>(0h400000003000000) connect rom[213], UInt<64>(0h100000099010000) connect rom[214], UInt<64>(0h100000002000000) connect rom[215], UInt<64>(0h6f6c635f73756263) connect rom[216], UInt<64>(0h300000000006b63) connect rom[217], UInt<64>(0hde01000004000000) connect rom[218], UInt<64>(0h300000000000000) connect rom[219], UInt<64>(0h5300000004000000) connect rom[220], UInt<64>(0h30000000065cd1d) connect rom[221], UInt<64>(0heb0100000b000000) connect rom[222], UInt<64>(0h6f6c635f73756263) connect rom[223], UInt<64>(0h300000000006b63) connect rom[224], UInt<64>(0h1b0000000c000000) connect rom[225], UInt<64>(0h6c632d6465786966) connect rom[226], UInt<64>(0h2000000006b636f) connect rom[227], UInt<64>(0h6e696c6301000000) connect rom[228], UInt<64>(0h3030303030324074) connect rom[229], UInt<64>(0h300000000000030) connect rom[230], UInt<64>(0h1b0000000d000000) connect rom[231], UInt<64>(0h6c632c7663736972) connect rom[232], UInt<64>(0h30746e69) connect rom[233], UInt<64>(0h1000000003000000) connect rom[234], UInt<64>(0h4000000fe010000) connect rom[235], UInt<64>(0h400000003000000) connect rom[236], UInt<64>(0h300000007000000) connect rom[237], UInt<64>(0h2e01000008000000) connect rom[238], UInt<64>(0h10000000002) connect rom[239], UInt<64>(0h800000003000000) connect rom[240], UInt<64>(0h746e6f63a8010000) connect rom[241], UInt<64>(0h2000000006c6f72) connect rom[242], UInt<64>(0h636f6c6301000000) connect rom[243], UInt<64>(0h4072657461672d6b) connect rom[244], UInt<64>(0h303030303031) connect rom[245], UInt<64>(0h800000003000000) connect rom[246], UInt<64>(0h10002e010000) connect rom[247], UInt<64>(0h300000000100000) connect rom[248], UInt<64>(0ha801000008000000) connect rom[249], UInt<64>(0h6c6f72746e6f63) connect rom[250], UInt<64>(0h100000002000000) connect rom[251], UInt<64>(0h6f632d6775626564) connect rom[252], UInt<64>(0h72656c6c6f72746e) connect rom[253], UInt<64>(0h300000000003040) connect rom[254], UInt<64>(0h1b00000021000000) connect rom[255], UInt<64>(0h642c657669666973) connect rom[256], UInt<64>(0h3331302d67756265) connect rom[257], UInt<64>(0h642c766373697200) connect rom[258], UInt<64>(0h3331302d67756265) connect rom[259], UInt<64>(0h300000000000000) connect rom[260], UInt<64>(0h1202000005000000) connect rom[261], UInt<64>(0h6761746a) connect rom[262], UInt<64>(0h800000003000000) connect rom[263], UInt<64>(0h4000000fe010000) connect rom[264], UInt<64>(0h3000000ffff0000) connect rom[265], UInt<64>(0h2e01000008000000) connect rom[266], UInt<64>(0h10000000000000) connect rom[267], UInt<64>(0h800000003000000) connect rom[268], UInt<64>(0h746e6f63a8010000) connect rom[269], UInt<64>(0h2000000006c6f72) connect rom[270], UInt<64>(0h6f72726501000000) connect rom[271], UInt<64>(0h6563697665642d72) connect rom[272], UInt<64>(0h3030303340) connect rom[273], UInt<64>(0he00000003000000) connect rom[274], UInt<64>(0h696669731b000000) connect rom[275], UInt<64>(0h726f7272652c6576) connect rom[276], UInt<64>(0h300000000000030) connect rom[277], UInt<64>(0h2e01000008000000) connect rom[278], UInt<64>(0h10000000300000) connect rom[279], UInt<64>(0h100000002000000) connect rom[280], UInt<64>(0h6f6c635f73756266) connect rom[281], UInt<64>(0h300000000006b63) connect rom[282], UInt<64>(0hde01000004000000) connect rom[283], UInt<64>(0h300000000000000) connect rom[284], UInt<64>(0h5300000004000000) connect rom[285], UInt<64>(0h30000000065cd1d) connect rom[286], UInt<64>(0heb0100000b000000) connect rom[287], UInt<64>(0h6f6c635f73756266) connect rom[288], UInt<64>(0h300000000006b63) connect rom[289], UInt<64>(0h1b0000000c000000) connect rom[290], UInt<64>(0h6c632d6465786966) connect rom[291], UInt<64>(0h2000000006b636f) connect rom[292], UInt<64>(0h65746e6901000000) connect rom[293], UInt<64>(0h6f632d7470757272) connect rom[294], UInt<64>(0h72656c6c6f72746e) connect rom[295], UInt<64>(0h3030303030306340) connect rom[296], UInt<64>(0h300000000000000) connect rom[297], UInt<64>(0h7301000004000000) connect rom[298], UInt<64>(0h300000001000000) connect rom[299], UInt<64>(0h1b0000000c000000) connect rom[300], UInt<64>(0h6c702c7663736972) connect rom[301], UInt<64>(0h300000000306369) connect rom[302], UInt<64>(0h8401000000000000) connect rom[303], UInt<64>(0h1000000003000000) connect rom[304], UInt<64>(0h4000000fe010000) connect rom[305], UInt<64>(0h40000000b000000) connect rom[306], UInt<64>(0h300000009000000) connect rom[307], UInt<64>(0h2e01000008000000) connect rom[308], UInt<64>(0h40000000c) connect rom[309], UInt<64>(0h800000003000000) connect rom[310], UInt<64>(0h746e6f63a8010000) connect rom[311], UInt<64>(0h3000000006c6f72) connect rom[312], UInt<64>(0h1f02000004000000) connect rom[313], UInt<64>(0h300000001000000) connect rom[314], UInt<64>(0h3202000004000000) connect rom[315], UInt<64>(0h300000001000000) connect rom[316], UInt<64>(0h9901000004000000) connect rom[317], UInt<64>(0h200000006000000) connect rom[318], UInt<64>(0h7375626d01000000) connect rom[319], UInt<64>(0h6b636f6c635f) connect rom[320], UInt<64>(0h400000003000000) connect rom[321], UInt<64>(0hde010000) connect rom[322], UInt<64>(0h400000003000000) connect rom[323], UInt<64>(0h65cd1d53000000) connect rom[324], UInt<64>(0hb00000003000000) connect rom[325], UInt<64>(0h7375626deb010000) connect rom[326], UInt<64>(0h6b636f6c635f) connect rom[327], UInt<64>(0hc00000003000000) connect rom[328], UInt<64>(0h657869661b000000) connect rom[329], UInt<64>(0h6b636f6c632d64) connect rom[330], UInt<64>(0h100000002000000) connect rom[331], UInt<64>(0h6f6c635f73756270) connect rom[332], UInt<64>(0h300000000006b63) connect rom[333], UInt<64>(0hde01000004000000) connect rom[334], UInt<64>(0h300000000000000) connect rom[335], UInt<64>(0h5300000004000000) connect rom[336], UInt<64>(0h30000000065cd1d) connect rom[337], UInt<64>(0heb0100000b000000) connect rom[338], UInt<64>(0h6f6c635f73756270) connect rom[339], UInt<64>(0h300000000006b63) connect rom[340], UInt<64>(0h1b0000000c000000) connect rom[341], UInt<64>(0h6c632d6465786966) connect rom[342], UInt<64>(0h3000000006b636f) connect rom[343], UInt<64>(0h9901000004000000) connect rom[344], UInt<64>(0h200000005000000) connect rom[345], UInt<64>(0h406d6f7201000000) connect rom[346], UInt<64>(0h3030303031) connect rom[347], UInt<64>(0hc00000003000000) connect rom[348], UInt<64>(0h696669731b000000) connect rom[349], UInt<64>(0h306d6f722c6576) connect rom[350], UInt<64>(0h800000003000000) connect rom[351], UInt<64>(0h1002e010000) connect rom[352], UInt<64>(0h300000000000100) connect rom[353], UInt<64>(0ha801000004000000) connect rom[354], UInt<64>(0h2000000006d656d) connect rom[355], UInt<64>(0h7375627301000000) connect rom[356], UInt<64>(0h6b636f6c635f) connect rom[357], UInt<64>(0h400000003000000) connect rom[358], UInt<64>(0hde010000) connect rom[359], UInt<64>(0h400000003000000) connect rom[360], UInt<64>(0h65cd1d53000000) connect rom[361], UInt<64>(0hb00000003000000) connect rom[362], UInt<64>(0h73756273eb010000) connect rom[363], UInt<64>(0h6b636f6c635f) connect rom[364], UInt<64>(0hc00000003000000) connect rom[365], UInt<64>(0h657869661b000000) connect rom[366], UInt<64>(0h6b636f6c632d64) connect rom[367], UInt<64>(0h100000002000000) connect rom[368], UInt<64>(0h31406c6169726573) connect rom[369], UInt<64>(0h30303030323030) connect rom[370], UInt<64>(0h400000003000000) connect rom[371], UInt<64>(0h50000003d020000) connect rom[372], UInt<64>(0hd00000003000000) connect rom[373], UInt<64>(0h696669731b000000) connect rom[374], UInt<64>(0h30747261752c6576) connect rom[375], UInt<64>(0h300000000000000) connect rom[376], UInt<64>(0h4402000004000000) connect rom[377], UInt<64>(0h300000006000000) connect rom[378], UInt<64>(0h5502000004000000) connect rom[379], UInt<64>(0h300000001000000) connect rom[380], UInt<64>(0h2e01000008000000) connect rom[381], UInt<64>(0h10000000000210) connect rom[382], UInt<64>(0h800000003000000) connect rom[383], UInt<64>(0h746e6f63a8010000) connect rom[384], UInt<64>(0h2000000006c6f72) connect rom[385], UInt<64>(0h656c697401000000) connect rom[386], UInt<64>(0h732d74657365722d) connect rom[387], UInt<64>(0h3131407265747465) connect rom[388], UInt<64>(0h30303030) connect rom[389], UInt<64>(0h800000003000000) connect rom[390], UInt<64>(0h11002e010000) connect rom[391], UInt<64>(0h300000000100000) connect rom[392], UInt<64>(0ha801000008000000) connect rom[393], UInt<64>(0h6c6f72746e6f63) connect rom[394], UInt<64>(0h200000002000000) connect rom[395], UInt<64>(0h900000002000000) connect rom[396], UInt<64>(0h7373657264646123) connect rom[397], UInt<64>(0h2300736c6c65632d) connect rom[398], UInt<64>(0h6c65632d657a6973) connect rom[399], UInt<64>(0h61706d6f6300736c) connect rom[400], UInt<64>(0h6f6d00656c626974) connect rom[401], UInt<64>(0h69726573006c6564) connect rom[402], UInt<64>(0h6f64747300306c61) connect rom[403], UInt<64>(0h687461702d7475) connect rom[404], UInt<64>(0h65736162656d6974) connect rom[405], UInt<64>(0h6e6575716572662d) connect rom[406], UInt<64>(0h6b636f6c63007963) connect rom[407], UInt<64>(0h6e6575716572662d) connect rom[408], UInt<64>(0h6361632d64007963) connect rom[409], UInt<64>(0h6b636f6c622d6568) connect rom[410], UInt<64>(0h2d6400657a69732d) connect rom[411], UInt<64>(0h65732d6568636163) connect rom[412], UInt<64>(0h6361632d64007374) connect rom[413], UInt<64>(0h657a69732d6568) connect rom[414], UInt<64>(0h65732d626c742d64) connect rom[415], UInt<64>(0h626c742d64007374) connect rom[416], UInt<64>(0h656400657a69732d) connect rom[417], UInt<64>(0h7079745f65636976) connect rom[418], UInt<64>(0h6177647261680065) connect rom[419], UInt<64>(0h2d636578652d6572) connect rom[420], UInt<64>(0h696f706b61657262) connect rom[421], UInt<64>(0h746e756f632d746e) connect rom[422], UInt<64>(0h65686361632d6900) connect rom[423], UInt<64>(0h732d6b636f6c622d) connect rom[424], UInt<64>(0h61632d6900657a69) connect rom[425], UInt<64>(0h737465732d656863) connect rom[426], UInt<64>(0h65686361632d6900) connect rom[427], UInt<64>(0h2d6900657a69732d) connect rom[428], UInt<64>(0h737465732d626c74) connect rom[429], UInt<64>(0h732d626c742d6900) connect rom[430], UInt<64>(0h2d756d6d00657a69) connect rom[431], UInt<64>(0h78656e0065707974) connect rom[432], UInt<64>(0h2d6c6576656c2d74) connect rom[433], UInt<64>(0h6572006568636163) connect rom[434], UInt<64>(0h2c76637369720067) connect rom[435], UInt<64>(0h6373697200617369) connect rom[436], UInt<64>(0h617267706d702c76) connect rom[437], UInt<64>(0h79746972616c756e) connect rom[438], UInt<64>(0h702c766373697200) connect rom[439], UInt<64>(0h6e6f69676572706d) connect rom[440], UInt<64>(0h7375746174730073) connect rom[441], UInt<64>(0h6c70732d626c7400) connect rom[442], UInt<64>(0h65746e6923007469) connect rom[443], UInt<64>(0h65632d7470757272) connect rom[444], UInt<64>(0h65746e6900736c6c) connect rom[445], UInt<64>(0h6f632d7470757272) connect rom[446], UInt<64>(0h72656c6c6f72746e) connect rom[447], UInt<64>(0h656c646e61687000) connect rom[448], UInt<64>(0h7365676e617200) connect rom[449], UInt<64>(0h656d616e2d676572) connect rom[450], UInt<64>(0h2d65686361630073) connect rom[451], UInt<64>(0h6163006c6576656c) connect rom[452], UInt<64>(0h66696e752d656863) connect rom[453], UInt<64>(0h6966697300646569) connect rom[454], UInt<64>(0h2d7268736d2c6576) connect rom[455], UInt<64>(0h632300746e756f63) connect rom[456], UInt<64>(0h6c65632d6b636f6c) connect rom[457], UInt<64>(0h6b636f6c6300736c) connect rom[458], UInt<64>(0h2d74757074756f2d) connect rom[459], UInt<64>(0h6e690073656d616e) connect rom[460], UInt<64>(0h7374707572726574) connect rom[461], UInt<64>(0h65646e657478652d) connect rom[462], UInt<64>(0h2d67756265640064) connect rom[463], UInt<64>(0h7200686361747461) connect rom[464], UInt<64>(0h78616d2c76637369) connect rom[465], UInt<64>(0h7469726f6972702d) connect rom[466], UInt<64>(0h2c76637369720079) connect rom[467], UInt<64>(0h6f6c63007665646e) connect rom[468], UInt<64>(0h65746e6900736b63) connect rom[469], UInt<64>(0h61702d7470757272) connect rom[470], UInt<64>(0h746e6900746e6572) connect rom[471], UInt<64>(0h73747075727265) connect rom[472], UInt<64>(0h0) connect rom[473], UInt<64>(0h0) connect rom[474], UInt<64>(0h0) connect rom[475], UInt<64>(0h0) connect rom[476], UInt<64>(0h0) connect rom[477], UInt<64>(0h0) connect rom[478], UInt<64>(0h0) connect rom[479], UInt<64>(0h0) connect rom[480], UInt<64>(0h0) connect rom[481], UInt<64>(0h0) connect rom[482], UInt<64>(0h0) connect rom[483], UInt<64>(0h0) connect rom[484], UInt<64>(0h0) connect rom[485], UInt<64>(0h0) connect rom[486], UInt<64>(0h0) connect rom[487], UInt<64>(0h0) connect rom[488], UInt<64>(0h0) connect rom[489], UInt<64>(0h0) connect rom[490], UInt<64>(0h0) connect rom[491], UInt<64>(0h0) connect rom[492], UInt<64>(0h0) connect rom[493], UInt<64>(0h0) connect rom[494], UInt<64>(0h0) connect rom[495], UInt<64>(0h0) connect rom[496], UInt<64>(0h0) connect rom[497], UInt<64>(0h0) connect rom[498], UInt<64>(0h0) connect rom[499], UInt<64>(0h0) connect rom[500], UInt<64>(0h0) connect rom[501], UInt<64>(0h0) connect rom[502], UInt<64>(0h0) connect rom[503], UInt<64>(0h0) connect rom[504], UInt<64>(0h0) connect rom[505], UInt<64>(0h0) connect rom[506], UInt<64>(0h0) connect rom[507], UInt<64>(0h0) connect rom[508], UInt<64>(0h0) connect rom[509], UInt<64>(0h0) connect rom[510], UInt<64>(0h0) connect rom[511], UInt<64>(0h0) connect nodeIn.d.valid, nodeIn.a.valid connect nodeIn.a.ready, nodeIn.d.ready node index = bits(nodeIn.a.bits.address, 11, 3) node high = bits(nodeIn.a.bits.address, 15, 12) node _nodeIn_d_bits_T = orr(high) node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, nodeIn.a.bits.size connect nodeIn_d_bits_d.source, nodeIn.a.bits.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)
module TLROM( // @[BootROM.scala:41:9] input clock, // @[BootROM.scala:41:9] input reset, // @[BootROM.scala:41:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9] wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9] wire [511:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h73747075727265, 64'h746E6900746E6572, 64'h61702D7470757272, 64'h65746E6900736B63, 64'h6F6C63007665646E, 64'h2C76637369720079, 64'h7469726F6972702D, 64'h78616D2C76637369, 64'h7200686361747461, 64'h2D67756265640064, 64'h65646E657478652D, 64'h7374707572726574, 64'h6E690073656D616E, 64'h2D74757074756F2D, 64'h6B636F6C6300736C, 64'h6C65632D6B636F6C, 64'h632300746E756F63, 64'h2D7268736D2C6576, 64'h6966697300646569, 64'h66696E752D656863, 64'h6163006C6576656C, 64'h2D65686361630073, 64'h656D616E2D676572, 64'h7365676E617200, 64'h656C646E61687000, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6900736C6C, 64'h65632D7470757272, 64'h65746E6923007469, 64'h6C70732D626C7400, 64'h7375746174730073, 64'h6E6F69676572706D, 64'h702C766373697200, 64'h79746972616C756E, 64'h617267706D702C76, 64'h6373697200617369, 64'h2C76637369720067, 64'h6572006568636163, 64'h2D6C6576656C2D74, 64'h78656E0065707974, 64'h2D756D6D00657A69, 64'h732D626C742D6900, 64'h737465732D626C74, 64'h2D6900657A69732D, 64'h65686361632D6900, 64'h737465732D656863, 64'h61632D6900657A69, 64'h732D6B636F6C622D, 64'h65686361632D6900, 64'h746E756F632D746E, 64'h696F706B61657262, 64'h2D636578652D6572, 64'h6177647261680065, 64'h7079745F65636976, 64'h656400657A69732D, 64'h626C742D64007374, 64'h65732D626C742D64, 64'h657A69732D6568, 64'h6361632D64007374, 64'h65732D6568636163, 64'h2D6400657A69732D, 64'h6B636F6C622D6568, 64'h6361632D64007963, 64'h6E6575716572662D, 64'h6B636F6C63007963, 64'h6E6575716572662D, 64'h65736162656D6974, 64'h687461702D7475, 64'h6F64747300306C61, 64'h69726573006C6564, 64'h6F6D00656C626974, 64'h61706D6F6300736C, 64'h6C65632D657A6973, 64'h2300736C6C65632D, 64'h7373657264646123, 64'h900000002000000, 64'h200000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h11002E010000, 64'h800000003000000, 64'h30303030, 64'h3131407265747465, 64'h732D74657365722D, 64'h656C697401000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000000210, 64'h2E01000008000000, 64'h300000001000000, 64'h5502000004000000, 64'h300000006000000, 64'h4402000004000000, 64'h300000000000000, 64'h30747261752C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h50000003D020000, 64'h400000003000000, 64'h30303030323030, 64'h31406C6169726573, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h73756273EB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375627301000000, 64'h2000000006D656D, 64'hA801000004000000, 64'h300000000000100, 64'h1002E010000, 64'h800000003000000, 64'h306D6F722C6576, 64'h696669731B000000, 64'hC00000003000000, 64'h3030303031, 64'h406D6F7201000000, 64'h200000005000000, 64'h9901000004000000, 64'h3000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'hEB0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'hDE01000004000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h7375626DEB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626D01000000, 64'h200000006000000, 64'h9901000004000000, 64'h300000001000000, 64'h3202000004000000, 64'h300000001000000, 64'h1F02000004000000, 64'h3000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h40000000C, 64'h2E01000008000000, 64'h300000009000000, 64'h40000000B000000, 64'h4000000FE010000, 64'h1000000003000000, 64'h8401000000000000, 64'h300000000306369, 64'h6C702C7663736972, 64'h1B0000000C000000, 64'h300000001000000, 64'h7301000004000000, 64'h300000000000000, 64'h3030303030306340, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6901000000, 64'h2000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756266, 64'hEB0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'hDE01000004000000, 64'h300000000006B63, 64'h6F6C635F73756266, 64'h100000002000000, 64'h10000000300000, 64'h2E01000008000000, 64'h300000000000030, 64'h726F7272652C6576, 64'h696669731B000000, 64'hE00000003000000, 64'h3030303340, 64'h6563697665642D72, 64'h6F72726501000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000000000, 64'h2E01000008000000, 64'h3000000FFFF0000, 64'h4000000FE010000, 64'h800000003000000, 64'h6761746A, 64'h1202000005000000, 64'h300000000000000, 64'h3331302D67756265, 64'h642C766373697200, 64'h3331302D67756265, 64'h642C657669666973, 64'h1B00000021000000, 64'h300000000003040, 64'h72656C6C6F72746E, 64'h6F632D6775626564, 64'h100000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h10002E010000, 64'h800000003000000, 64'h303030303031, 64'h4072657461672D6B, 64'h636F6C6301000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000002, 64'h2E01000008000000, 64'h300000007000000, 64'h400000003000000, 64'h4000000FE010000, 64'h1000000003000000, 64'h30746E69, 64'h6C632C7663736972, 64'h1B0000000D000000, 64'h300000000000030, 64'h3030303030324074, 64'h6E696C6301000000, 64'h2000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756263, 64'hEB0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'hDE01000004000000, 64'h300000000006B63, 64'h6F6C635F73756263, 64'h100000002000000, 64'h100000099010000, 64'h400000003000000, 64'hC000000CC010000, 64'h400000003000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h1022E010000, 64'h800000003000000, 64'h300000002000000, 64'h1D01000008000000, 64'h300000000000000, 64'h6568636163003065, 64'h6863616365766973, 64'h756C636E692C6576, 64'h696669731B000000, 64'h1D00000003000000, 64'hBE01000000000000, 64'h300000000000800, 64'h8500000004000000, 64'h300000000040000, 64'h7800000004000000, 64'h300000002000000, 64'hB201000004000000, 64'h300000040000000, 64'h6500000004000000, 64'h300000000000000, 64'h3030303031303240, 64'h72656C6C6F72746E, 64'h6F632D6568636163, 64'h100000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h1000002E010000, 64'h800000003000000, 64'h3030303140, 64'h6765722D73736572, 64'h6464612D746F6F62, 64'h1000000A1010000, 64'h3000000, 64'h7375622D656C70, 64'h6D697300636F732D, 64'h6472617970696863, 64'h2C7261622D626375, 64'h1B00000020000000, 64'h300000001000000, 64'hF00000004000000, 64'h300000001000000, 64'h4000000, 64'h300000000636F73, 64'h100000002000000, 64'h200000099010000, 64'h400000003000000, 64'h1000000080, 64'h2E01000008000000, 64'h300000000007972, 64'h6F6D656DA6000000, 64'h700000003000000, 64'h30303030303030, 64'h384079726F6D656D, 64'h100000002000000, 64'h300000099010000, 64'h400000003000000, 64'h64656C62, 64'h6173696462010000, 64'h900000003000000, 64'h10000000008, 64'h2E01000008000000, 64'h300000000007972, 64'h6F6D656DA6000000, 64'h700000003000000, 64'h303030303030, 64'h384079726F6D656D, 64'h100000002000000, 64'h3066697468, 64'h2C6263751B000000, 64'hA00000003000000, 64'h66697468, 64'h100000002000000, 64'h200000002000000, 64'h400000099010000, 64'h400000003000000, 64'h8401000000000000, 64'h300000000006374, 64'h6E692D7570632C76, 64'h637369721B000000, 64'hF00000003000000, 64'h100000073010000, 64'h400000003000000, 64'h72656C6C, 64'h6F72746E6F632D74, 64'h7075727265746E69, 64'h100000069010000, 64'h3000000, 64'h20A1070040000000, 64'h400000003000000, 64'h79616B6F, 64'h6201000005000000, 64'h300000008000000, 64'h5101000004000000, 64'h300000004000000, 64'h3C01000004000000, 64'h30000000073627A, 64'h5F62627A5F61627A, 64'h5F6D7068697A5F69, 64'h65636E6566697A5F, 64'h727363697A626364, 64'h66616D6934367672, 64'h320100002C000000, 64'h300000000000000, 64'h2E01000004000000, 64'h300000001000000, 64'h1D01000004000000, 64'h300000000003933, 64'h76732C7663736972, 64'h140100000B000000, 64'h300000020000000, 64'h901000004000000, 64'h300000001000000, 64'hFE00000004000000, 64'h300000000800000, 64'hF100000004000000, 64'h300000040000000, 64'hE400000004000000, 64'h300000040000000, 64'hD100000004000000, 64'h300000000000000, 64'hB200000004000000, 64'h300000000757063, 64'hA600000004000000, 64'h300000010000000, 64'h9B00000004000000, 64'h300000001000000, 64'h9000000004000000, 64'h300000000800000, 64'h8300000004000000, 64'h300000040000000, 64'h7600000004000000, 64'h300000040000000, 64'h6300000004000000, 64'h300000000766373, 64'h697200306D6F6F62, 64'h2C7261622D626375, 64'h1B00000014000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000030, 64'h4075706301000000, 64'h20A1070040000000, 64'h400000003000000, 64'hF000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h73757063, 64'h100000002000000, 64'h30303030, 64'h32303031406C6169, 64'h7265732F636F732F, 64'h3400000015000000, 64'h300000000006E65, 64'h736F686301000000, 64'h200000000000000, 64'h3030303032303031, 64'h406C61697265732F, 64'h636F732F2C000000, 64'h1500000003000000, 64'h73657361696C61, 64'h100000000000000, 64'h6472617970696863, 64'h2C7261622D626375, 64'h2600000011000000, 64'h300000000000000, 64'h7665642D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h1500000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h1000000, 64'h0, 64'h0, 64'h680B000060020000, 64'h10000000, 64'h1100000028000000, 64'hA00B000038000000, 64'hE0000EDFE0DD0, 64'h1330200073, 64'h3006307308000613, 64'h185859300000597, 64'hF140257334151073, 64'h5350300001537, 64'h5A02300B505B3, 64'h251513FE029EE3, 64'h5A283F81FF06F, 64'h0, 64'h0, 64'h2C0006F, 64'hFE069AE3FFC62683, 64'h46061300D62023, 64'h10069300458613, 64'h380006F00050463, 64'hF1402573020005B7, 64'hFFDFF06F, 64'h1050007330052073, 64'h3045107300800513, 64'h3445307322200513, 64'h3030107300028863, 64'h12F2934122D293, 64'h301022F330551073, 64'h405051300000517}; wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22] wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22] wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22] wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22] wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22] wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22] wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22] wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22] wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22] wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22] wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22] wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22] wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22] wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22] wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22] wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22] wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22] wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22] wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22] wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22] wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22] wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22] wire [63:0] rom_24 = 64'hE0000EDFE0DD0; // @[BootROM.scala:50:22] wire [63:0] rom_25 = 64'hA00B000038000000; // @[BootROM.scala:50:22] wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22] wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22] wire [63:0] rom_28 = 64'h680B000060020000; // @[BootROM.scala:50:22] wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22] wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22] wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22] wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22] wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22] wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22] wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22] wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22] wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22] wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22] wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22] wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22] wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_69 = 64'h1B00000014000000; // @[BootROM.scala:50:22] wire [63:0] rom_71 = 64'h697200306D6F6F62; // @[BootROM.scala:50:22] wire [63:0] rom_72 = 64'h300000000766373; // @[BootROM.scala:50:22] wire [63:0] rom_73 = 64'h6300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_75 = 64'h7600000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_77 = 64'h8300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_79 = 64'h9000000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_81 = 64'h9B00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_82 = 64'h300000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_83 = 64'hA600000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_84 = 64'h300000000757063; // @[BootROM.scala:50:22] wire [63:0] rom_85 = 64'hB200000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_87 = 64'hD100000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_89 = 64'hE400000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_91 = 64'hF100000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_78 = 64'h300000000800000; // @[BootROM.scala:50:22] wire [63:0] rom_92 = 64'h300000000800000; // @[BootROM.scala:50:22] wire [63:0] rom_93 = 64'hFE00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_95 = 64'h901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_96 = 64'h300000020000000; // @[BootROM.scala:50:22] wire [63:0] rom_97 = 64'h140100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_98 = 64'h76732C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_99 = 64'h300000000003933; // @[BootROM.scala:50:22] wire [63:0] rom_100 = 64'h1D01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_102 = 64'h2E01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_104 = 64'h320100002C000000; // @[BootROM.scala:50:22] wire [63:0] rom_105 = 64'h66616D6934367672; // @[BootROM.scala:50:22] wire [63:0] rom_106 = 64'h727363697A626364; // @[BootROM.scala:50:22] wire [63:0] rom_107 = 64'h65636E6566697A5F; // @[BootROM.scala:50:22] wire [63:0] rom_108 = 64'h5F6D7068697A5F69; // @[BootROM.scala:50:22] wire [63:0] rom_109 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22] wire [63:0] rom_110 = 64'h30000000073627A; // @[BootROM.scala:50:22] wire [63:0] rom_111 = 64'h3C01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_112 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_113 = 64'h5101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_114 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_115 = 64'h6201000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_116 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_118 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_120 = 64'h100000069010000; // @[BootROM.scala:50:22] wire [63:0] rom_121 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_122 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_123 = 64'h72656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_125 = 64'h100000073010000; // @[BootROM.scala:50:22] wire [63:0] rom_126 = 64'hF00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_127 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_128 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22] wire [63:0] rom_129 = 64'h300000000006374; // @[BootROM.scala:50:22] wire [63:0] rom_132 = 64'h400000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_135 = 64'h66697468; // @[BootROM.scala:50:22] wire [63:0] rom_136 = 64'hA00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_137 = 64'h2C6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_138 = 64'h3066697468; // @[BootROM.scala:50:22] wire [63:0] rom_141 = 64'h303030303030; // @[BootROM.scala:50:22] wire [63:0] rom_146 = 64'h10000000008; // @[BootROM.scala:50:22] wire [63:0] rom_147 = 64'h900000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_148 = 64'h6173696462010000; // @[BootROM.scala:50:22] wire [63:0] rom_149 = 64'h64656C62; // @[BootROM.scala:50:22] wire [63:0] rom_151 = 64'h300000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_140 = 64'h384079726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_153 = 64'h384079726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_154 = 64'h30303030303030; // @[BootROM.scala:50:22] wire [63:0] rom_142 = 64'h700000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_155 = 64'h700000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_143 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22] wire [63:0] rom_156 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22] wire [63:0] rom_144 = 64'h300000000007972; // @[BootROM.scala:50:22] wire [63:0] rom_157 = 64'h300000000007972; // @[BootROM.scala:50:22] wire [63:0] rom_159 = 64'h1000000080; // @[BootROM.scala:50:22] wire [63:0] rom_161 = 64'h200000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_163 = 64'h300000000636F73; // @[BootROM.scala:50:22] wire [63:0] rom_164 = 64'h4000000; // @[BootROM.scala:50:22] wire [63:0] rom_166 = 64'hF00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_168 = 64'h1B00000020000000; // @[BootROM.scala:50:22] wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_70 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_169 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_170 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_171 = 64'h6D697300636F732D; // @[BootROM.scala:50:22] wire [63:0] rom_172 = 64'h7375622D656C70; // @[BootROM.scala:50:22] wire [63:0] rom_119 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_173 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_174 = 64'h1000000A1010000; // @[BootROM.scala:50:22] wire [63:0] rom_175 = 64'h6464612D746F6F62; // @[BootROM.scala:50:22] wire [63:0] rom_176 = 64'h6765722D73736572; // @[BootROM.scala:50:22] wire [63:0] rom_177 = 64'h3030303140; // @[BootROM.scala:50:22] wire [63:0] rom_179 = 64'h1000002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_184 = 64'h6F632D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_186 = 64'h3030303031303240; // @[BootROM.scala:50:22] wire [63:0] rom_188 = 64'h6500000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_74 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_76 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_88 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_90 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_189 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_190 = 64'hB201000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_192 = 64'h7800000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_193 = 64'h300000000040000; // @[BootROM.scala:50:22] wire [63:0] rom_194 = 64'h8500000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_195 = 64'h300000000000800; // @[BootROM.scala:50:22] wire [63:0] rom_196 = 64'hBE01000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_197 = 64'h1D00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_199 = 64'h756C636E692C6576; // @[BootROM.scala:50:22] wire [63:0] rom_200 = 64'h6863616365766973; // @[BootROM.scala:50:22] wire [63:0] rom_201 = 64'h6568636163003065; // @[BootROM.scala:50:22] wire [63:0] rom_203 = 64'h1D01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_191 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_204 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_206 = 64'h1022E010000; // @[BootROM.scala:50:22] wire [63:0] rom_211 = 64'hC000000CC010000; // @[BootROM.scala:50:22] wire [63:0] rom_213 = 64'h100000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_215 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22] wire [63:0] rom_222 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22] wire [63:0] rom_227 = 64'h6E696C6301000000; // @[BootROM.scala:50:22] wire [63:0] rom_228 = 64'h3030303030324074; // @[BootROM.scala:50:22] wire [63:0] rom_230 = 64'h1B0000000D000000; // @[BootROM.scala:50:22] wire [63:0] rom_231 = 64'h6C632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_232 = 64'h30746E69; // @[BootROM.scala:50:22] wire [63:0] rom_236 = 64'h300000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_238 = 64'h10000000002; // @[BootROM.scala:50:22] wire [63:0] rom_242 = 64'h636F6C6301000000; // @[BootROM.scala:50:22] wire [63:0] rom_243 = 64'h4072657461672D6B; // @[BootROM.scala:50:22] wire [63:0] rom_244 = 64'h303030303031; // @[BootROM.scala:50:22] wire [63:0] rom_246 = 64'h10002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_251 = 64'h6F632D6775626564; // @[BootROM.scala:50:22] wire [63:0] rom_253 = 64'h300000000003040; // @[BootROM.scala:50:22] wire [63:0] rom_254 = 64'h1B00000021000000; // @[BootROM.scala:50:22] wire [63:0] rom_255 = 64'h642C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_257 = 64'h642C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_256 = 64'h3331302D67756265; // @[BootROM.scala:50:22] wire [63:0] rom_258 = 64'h3331302D67756265; // @[BootROM.scala:50:22] wire [63:0] rom_260 = 64'h1202000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_261 = 64'h6761746A; // @[BootROM.scala:50:22] wire [63:0] rom_264 = 64'h3000000FFFF0000; // @[BootROM.scala:50:22] wire [63:0] rom_266 = 64'h10000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_270 = 64'h6F72726501000000; // @[BootROM.scala:50:22] wire [63:0] rom_271 = 64'h6563697665642D72; // @[BootROM.scala:50:22] wire [63:0] rom_272 = 64'h3030303340; // @[BootROM.scala:50:22] wire [63:0] rom_273 = 64'hE00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_275 = 64'h726F7272652C6576; // @[BootROM.scala:50:22] wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_229 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_276 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_278 = 64'h10000000300000; // @[BootROM.scala:50:22] wire [63:0] rom_280 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22] wire [63:0] rom_287 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22] wire [63:0] rom_226 = 64'h2000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_291 = 64'h2000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_292 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_295 = 64'h3030303030306340; // @[BootROM.scala:50:22] wire [63:0] rom_297 = 64'h7301000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_300 = 64'h6C702C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_301 = 64'h300000000306369; // @[BootROM.scala:50:22] wire [63:0] rom_130 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_302 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_233 = 64'h1000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_303 = 64'h1000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_234 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_263 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_304 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_305 = 64'h40000000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_306 = 64'h300000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_308 = 64'h40000000C; // @[BootROM.scala:50:22] wire [63:0] rom_311 = 64'h3000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_312 = 64'h1F02000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_314 = 64'h3202000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_317 = 64'h200000006000000; // @[BootROM.scala:50:22] wire [63:0] rom_318 = 64'h7375626D01000000; // @[BootROM.scala:50:22] wire [63:0] rom_325 = 64'h7375626DEB010000; // @[BootROM.scala:50:22] wire [63:0] rom_217 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_282 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_333 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_219 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_284 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_335 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_220 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_285 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_336 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_221 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_286 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_337 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_331 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_338 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_216 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_223 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_281 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_288 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_332 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_339 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_224 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_289 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_299 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_340 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_225 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_290 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_341 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_342 = 64'h3000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_316 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_343 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_344 = 64'h200000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_345 = 64'h406D6F7201000000; // @[BootROM.scala:50:22] wire [63:0] rom_346 = 64'h3030303031; // @[BootROM.scala:50:22] wire [63:0] rom_349 = 64'h306D6F722C6576; // @[BootROM.scala:50:22] wire [63:0] rom_351 = 64'h1002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_352 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_353 = 64'hA801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_354 = 64'h2000000006D656D; // @[BootROM.scala:50:22] wire [63:0] rom_355 = 64'h7375627301000000; // @[BootROM.scala:50:22] wire [63:0] rom_321 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_358 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_323 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_360 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_324 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_361 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_362 = 64'h73756273EB010000; // @[BootROM.scala:50:22] wire [63:0] rom_319 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_326 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_356 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_363 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_327 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_347 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_364 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_328 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_365 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_329 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_366 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_134 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_139 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_152 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_162 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_183 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_214 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_250 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_279 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_330 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_367 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_368 = 64'h31406C6169726573; // @[BootROM.scala:50:22] wire [63:0] rom_369 = 64'h30303030323030; // @[BootROM.scala:50:22] wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_117 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_124 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_131 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_150 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_160 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_210 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_212 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_235 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_320 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_322 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_357 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_359 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_370 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_371 = 64'h50000003D020000; // @[BootROM.scala:50:22] wire [63:0] rom_372 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_198 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_274 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_348 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_373 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_374 = 64'h30747261752C6576; // @[BootROM.scala:50:22] wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_86 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_103 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_187 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_202 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_218 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_259 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_283 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_296 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_334 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_375 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_376 = 64'h4402000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_377 = 64'h300000006000000; // @[BootROM.scala:50:22] wire [63:0] rom_378 = 64'h5502000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_80 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_94 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_101 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_165 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_167 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_298 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_313 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_315 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_379 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_145 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_158 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_237 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_265 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_277 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_307 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_380 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_381 = 64'h10000000000210; // @[BootROM.scala:50:22] wire [63:0] rom_240 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_268 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_310 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_383 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_241 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_269 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_384 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_385 = 64'h656C697401000000; // @[BootROM.scala:50:22] wire [63:0] rom_386 = 64'h732D74657365722D; // @[BootROM.scala:50:22] wire [63:0] rom_387 = 64'h3131407265747465; // @[BootROM.scala:50:22] wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_388 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_178 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_205 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_239 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_245 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_262 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_267 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_309 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_350 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_382 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_389 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_390 = 64'h11002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_180 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_207 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_247 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_391 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_181 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_208 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_248 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_392 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_182 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_209 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_249 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_393 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_133 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_394 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_395 = 64'h900000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_396 = 64'h7373657264646123; // @[BootROM.scala:50:22] wire [63:0] rom_397 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22] wire [63:0] rom_398 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22] wire [63:0] rom_399 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_400 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22] wire [63:0] rom_401 = 64'h69726573006C6564; // @[BootROM.scala:50:22] wire [63:0] rom_402 = 64'h6F64747300306C61; // @[BootROM.scala:50:22] wire [63:0] rom_403 = 64'h687461702D7475; // @[BootROM.scala:50:22] wire [63:0] rom_404 = 64'h65736162656D6974; // @[BootROM.scala:50:22] wire [63:0] rom_406 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22] wire [63:0] rom_405 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_407 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_408 = 64'h6361632D64007963; // @[BootROM.scala:50:22] wire [63:0] rom_409 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22] wire [63:0] rom_410 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_411 = 64'h65732D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_412 = 64'h6361632D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_413 = 64'h657A69732D6568; // @[BootROM.scala:50:22] wire [63:0] rom_414 = 64'h65732D626C742D64; // @[BootROM.scala:50:22] wire [63:0] rom_415 = 64'h626C742D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_416 = 64'h656400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_417 = 64'h7079745F65636976; // @[BootROM.scala:50:22] wire [63:0] rom_418 = 64'h6177647261680065; // @[BootROM.scala:50:22] wire [63:0] rom_419 = 64'h2D636578652D6572; // @[BootROM.scala:50:22] wire [63:0] rom_420 = 64'h696F706B61657262; // @[BootROM.scala:50:22] wire [63:0] rom_421 = 64'h746E756F632D746E; // @[BootROM.scala:50:22] wire [63:0] rom_423 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22] wire [63:0] rom_424 = 64'h61632D6900657A69; // @[BootROM.scala:50:22] wire [63:0] rom_425 = 64'h737465732D656863; // @[BootROM.scala:50:22] wire [63:0] rom_422 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_426 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_427 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_428 = 64'h737465732D626C74; // @[BootROM.scala:50:22] wire [63:0] rom_429 = 64'h732D626C742D6900; // @[BootROM.scala:50:22] wire [63:0] rom_430 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22] wire [63:0] rom_431 = 64'h78656E0065707974; // @[BootROM.scala:50:22] wire [63:0] rom_432 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22] wire [63:0] rom_433 = 64'h6572006568636163; // @[BootROM.scala:50:22] wire [63:0] rom_434 = 64'h2C76637369720067; // @[BootROM.scala:50:22] wire [63:0] rom_435 = 64'h6373697200617369; // @[BootROM.scala:50:22] wire [63:0] rom_436 = 64'h617267706D702C76; // @[BootROM.scala:50:22] wire [63:0] rom_437 = 64'h79746972616C756E; // @[BootROM.scala:50:22] wire [63:0] rom_438 = 64'h702C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_439 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22] wire [63:0] rom_440 = 64'h7375746174730073; // @[BootROM.scala:50:22] wire [63:0] rom_441 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22] wire [63:0] rom_442 = 64'h65746E6923007469; // @[BootROM.scala:50:22] wire [63:0] rom_443 = 64'h65632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_444 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22] wire [63:0] rom_293 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_445 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_185 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_252 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_294 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_446 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_447 = 64'h656C646E61687000; // @[BootROM.scala:50:22] wire [63:0] rom_448 = 64'h7365676E617200; // @[BootROM.scala:50:22] wire [63:0] rom_449 = 64'h656D616E2D676572; // @[BootROM.scala:50:22] wire [63:0] rom_450 = 64'h2D65686361630073; // @[BootROM.scala:50:22] wire [63:0] rom_451 = 64'h6163006C6576656C; // @[BootROM.scala:50:22] wire [63:0] rom_452 = 64'h66696E752D656863; // @[BootROM.scala:50:22] wire [63:0] rom_453 = 64'h6966697300646569; // @[BootROM.scala:50:22] wire [63:0] rom_454 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22] wire [63:0] rom_455 = 64'h632300746E756F63; // @[BootROM.scala:50:22] wire [63:0] rom_456 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22] wire [63:0] rom_457 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_458 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22] wire [63:0] rom_459 = 64'h6E690073656D616E; // @[BootROM.scala:50:22] wire [63:0] rom_460 = 64'h7374707572726574; // @[BootROM.scala:50:22] wire [63:0] rom_461 = 64'h65646E657478652D; // @[BootROM.scala:50:22] wire [63:0] rom_462 = 64'h2D67756265640064; // @[BootROM.scala:50:22] wire [63:0] rom_463 = 64'h7200686361747461; // @[BootROM.scala:50:22] wire [63:0] rom_464 = 64'h78616D2C76637369; // @[BootROM.scala:50:22] wire [63:0] rom_465 = 64'h7469726F6972702D; // @[BootROM.scala:50:22] wire [63:0] rom_466 = 64'h2C76637369720079; // @[BootROM.scala:50:22] wire [63:0] rom_467 = 64'h6F6C63007665646E; // @[BootROM.scala:50:22] wire [63:0] rom_468 = 64'h65746E6900736B63; // @[BootROM.scala:50:22] wire [63:0] rom_469 = 64'h61702D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_470 = 64'h746E6900746E6572; // @[BootROM.scala:50:22] wire [63:0] rom_471 = 64'h73747075727265; // @[BootROM.scala:50:22] wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_472 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_473 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22] wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17] wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9] wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[BootROM.scala:41:9] wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9] wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9] wire auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9] assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17] wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17] assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9] wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9] wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34] wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64] wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53] wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}] assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17] assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17] TLMonitor_55 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ProbePicker : input clock : Clock input reset : Reset output auto : { flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_1.d.bits.corrupt invalidate nodeIn_1.d.bits.data invalidate nodeIn_1.d.bits.denied invalidate nodeIn_1.d.bits.sink invalidate nodeIn_1.d.bits.source invalidate nodeIn_1.d.bits.size invalidate nodeIn_1.d.bits.param invalidate nodeIn_1.d.bits.opcode invalidate nodeIn_1.d.valid invalidate nodeIn_1.d.ready invalidate nodeIn_1.a.bits.corrupt invalidate nodeIn_1.a.bits.data invalidate nodeIn_1.a.bits.mask invalidate nodeIn_1.a.bits.address invalidate nodeIn_1.a.bits.source invalidate nodeIn_1.a.bits.size invalidate nodeIn_1.a.bits.param invalidate nodeIn_1.a.bits.opcode invalidate nodeIn_1.a.valid invalidate nodeIn_1.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready inst monitor_1 of TLMonitor_39 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, nodeIn_1.d.valid connect monitor_1.io.in.d.ready, nodeIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, nodeIn_1.a.valid connect monitor_1.io.in.a.ready, nodeIn_1.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeOut, nodeIn connect x1_nodeOut, nodeIn_1
module ProbePicker( // @[ProbePicker.scala:42:9] input clock, // @[ProbePicker.scala:42:9] input reset, // @[ProbePicker.scala:42:9] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLMonitor_38 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_0_a_ready), .io_in_a_valid (auto_in_0_a_valid), .io_in_a_bits_opcode (auto_in_0_a_bits_opcode), .io_in_a_bits_param (auto_in_0_a_bits_param), .io_in_a_bits_size (auto_in_0_a_bits_size), .io_in_a_bits_source (auto_in_0_a_bits_source), .io_in_a_bits_address (auto_in_0_a_bits_address), .io_in_a_bits_mask (auto_in_0_a_bits_mask), .io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt), .io_in_d_ready (auto_in_0_d_ready), .io_in_d_valid (auto_out_0_d_valid), .io_in_d_bits_opcode (auto_out_0_d_bits_opcode), .io_in_d_bits_size (auto_out_0_d_bits_size), .io_in_d_bits_source (auto_out_0_d_bits_source), .io_in_d_bits_denied (auto_out_0_d_bits_denied), .io_in_d_bits_corrupt (auto_out_0_d_bits_corrupt) ); // @[Nodes.scala:27:25] TLMonitor_39 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_1_a_ready), .io_in_a_valid (auto_in_1_a_valid), .io_in_a_bits_opcode (auto_in_1_a_bits_opcode), .io_in_a_bits_param (auto_in_1_a_bits_param), .io_in_a_bits_size (auto_in_1_a_bits_size), .io_in_a_bits_source (auto_in_1_a_bits_source), .io_in_a_bits_address (auto_in_1_a_bits_address), .io_in_a_bits_mask (auto_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt), .io_in_d_ready (auto_in_1_d_ready), .io_in_d_valid (auto_out_1_d_valid), .io_in_d_bits_opcode (auto_out_1_d_bits_opcode), .io_in_d_bits_param (auto_out_1_d_bits_param), .io_in_d_bits_size (auto_out_1_d_bits_size), .io_in_d_bits_source (auto_out_1_d_bits_source), .io_in_d_bits_sink (auto_out_1_d_bits_sink), .io_in_d_bits_denied (auto_out_1_d_bits_denied), .io_in_d_bits_corrupt (auto_out_1_d_bits_corrupt) ); // @[Nodes.scala:27:25] assign auto_in_1_a_ready = auto_out_1_a_ready; // @[ProbePicker.scala:42:9] assign auto_in_1_d_valid = auto_out_1_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_sink = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_in_0_a_ready = auto_out_0_a_ready; // @[ProbePicker.scala:42:9] assign auto_in_0_d_valid = auto_out_0_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_source = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_1_a_valid = auto_in_1_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_1_d_ready = auto_in_1_d_ready; // @[ProbePicker.scala:42:9] assign auto_out_0_a_valid = auto_in_0_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_0_d_ready = auto_in_0_d_ready; // @[ProbePicker.scala:42:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleD_a32d128s5k6z4u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)
module Repeater_TLBundleD_a32d128s5k6z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [5:0] io_enq_bits_sink, // @[Repeater.scala:13:14] input io_enq_bits_denied, // @[Repeater.scala:13:14] input [127:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [5:0] io_deq_bits_sink, // @[Repeater.scala:13:14] output io_deq_bits_denied, // @[Repeater.scala:13:14] output [127:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [1:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [5:0] saved_sink; // @[Repeater.scala:21:18] reg saved_denied; // @[Repeater.scala:21:18] reg [127:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_sink <= io_enq_bits_sink; // @[Repeater.scala:21:18] saved_denied <= io_enq_bits_denied; // @[Repeater.scala:21:18] saved_data <= io_enq_bits_data; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_72 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<19>(0h40000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_27, _T_32) node _T_69 = or(_T_68, _T_37) node _T_70 = or(_T_69, _T_42) node _T_71 = or(_T_70, _T_47) node _T_72 = or(_T_71, _T_52) node _T_73 = or(_T_72, _T_57) node _T_74 = or(_T_73, _T_62) node _T_75 = or(_T_74, _T_67) node _T_76 = and(_T_22, _T_75) node _T_77 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_78 = or(UInt<1>(0h0), _T_77) node _T_79 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<17>(0h10000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<29>(0h10000000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = and(_T_78, _T_89) node _T_91 = or(UInt<1>(0h0), _T_76) node _T_92 = or(_T_91, _T_90) node _T_93 = and(_T_21, _T_92) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_93, UInt<1>(0h1), "") : assert_2 node _T_97 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_98 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(UInt<1>(0h0), _T_99) node _T_101 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<14>(0h2000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<13>(0h1000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<18>(0h2f000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<17>(0h10000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<17>(0h10000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<19>(0h40000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_105, _T_110) node _T_157 = or(_T_156, _T_115) node _T_158 = or(_T_157, _T_120) node _T_159 = or(_T_158, _T_125) node _T_160 = or(_T_159, _T_130) node _T_161 = or(_T_160, _T_135) node _T_162 = or(_T_161, _T_140) node _T_163 = or(_T_162, _T_145) node _T_164 = or(_T_163, _T_150) node _T_165 = or(_T_164, _T_155) node _T_166 = and(_T_100, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(UInt<1>(0h0), _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_168, UInt<1>(0h1), "") : assert_3 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_175 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_175, UInt<1>(0h1), "") : assert_5 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(is_aligned, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_182 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_183 = asUInt(reset) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : node _T_185 = eq(_T_182, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_182, UInt<1>(0h1), "") : assert_7 node _T_186 = not(io.in.a.bits.mask) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_187, UInt<1>(0h1), "") : assert_8 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_191, UInt<1>(0h1), "") : assert_9 node _T_195 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<14>(0h2000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<18>(0h2f000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<17>(0h10000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_234 = cvt(_T_233) node _T_235 = and(_T_234, asSInt(UInt<27>(0h4000000))) node _T_236 = asSInt(_T_235) node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0))) node _T_238 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_239 = cvt(_T_238) node _T_240 = and(_T_239, asSInt(UInt<13>(0h1000))) node _T_241 = asSInt(_T_240) node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<19>(0h40000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = or(_T_207, _T_212) node _T_249 = or(_T_248, _T_217) node _T_250 = or(_T_249, _T_222) node _T_251 = or(_T_250, _T_227) node _T_252 = or(_T_251, _T_232) node _T_253 = or(_T_252, _T_237) node _T_254 = or(_T_253, _T_242) node _T_255 = or(_T_254, _T_247) node _T_256 = and(_T_202, _T_255) node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<29>(0h10000000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = or(_T_263, _T_268) node _T_270 = and(_T_258, _T_269) node _T_271 = or(UInt<1>(0h0), _T_256) node _T_272 = or(_T_271, _T_270) node _T_273 = and(_T_201, _T_272) node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_T_273, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_273, UInt<1>(0h1), "") : assert_10 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<18>(0h2f000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<19>(0h40000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<29>(0h10000000))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = or(_T_285, _T_290) node _T_337 = or(_T_336, _T_295) node _T_338 = or(_T_337, _T_300) node _T_339 = or(_T_338, _T_305) node _T_340 = or(_T_339, _T_310) node _T_341 = or(_T_340, _T_315) node _T_342 = or(_T_341, _T_320) node _T_343 = or(_T_342, _T_325) node _T_344 = or(_T_343, _T_330) node _T_345 = or(_T_344, _T_335) node _T_346 = and(_T_280, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_348, UInt<1>(0h1), "") : assert_11 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_355 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_355, UInt<1>(0h1), "") : assert_13 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_362, UInt<1>(0h1), "") : assert_15 node _T_366 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_366, UInt<1>(0h1), "") : assert_16 node _T_370 = not(io.in.a.bits.mask) node _T_371 = eq(_T_370, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_371, UInt<1>(0h1), "") : assert_17 node _T_375 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_375, UInt<1>(0h1), "") : assert_18 node _T_379 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_379 : node _T_380 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_381 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = or(UInt<1>(0h0), _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_385, UInt<1>(0h1), "") : assert_19 node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_391 = and(_T_389, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_394 = cvt(_T_393) node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000))) node _T_396 = asSInt(_T_395) node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0))) node _T_398 = and(_T_392, _T_397) node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_400 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_401 = and(_T_399, _T_400) node _T_402 = or(UInt<1>(0h0), _T_401) node _T_403 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_404 = cvt(_T_403) node _T_405 = and(_T_404, asSInt(UInt<14>(0h2000))) node _T_406 = asSInt(_T_405) node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0))) node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_409 = cvt(_T_408) node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000))) node _T_411 = asSInt(_T_410) node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0))) node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_414 = cvt(_T_413) node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000))) node _T_416 = asSInt(_T_415) node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0))) node _T_418 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_419 = cvt(_T_418) node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000))) node _T_421 = asSInt(_T_420) node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0))) node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_424 = cvt(_T_423) node _T_425 = and(_T_424, asSInt(UInt<13>(0h1000))) node _T_426 = asSInt(_T_425) node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0))) node _T_428 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_429 = cvt(_T_428) node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000))) node _T_431 = asSInt(_T_430) node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0))) node _T_433 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_434 = cvt(_T_433) node _T_435 = and(_T_434, asSInt(UInt<27>(0h4000000))) node _T_436 = asSInt(_T_435) node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0))) node _T_438 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_439 = cvt(_T_438) node _T_440 = and(_T_439, asSInt(UInt<13>(0h1000))) node _T_441 = asSInt(_T_440) node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0))) node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_444 = cvt(_T_443) node _T_445 = and(_T_444, asSInt(UInt<19>(0h40000))) node _T_446 = asSInt(_T_445) node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0))) node _T_448 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<29>(0h10000000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = or(_T_407, _T_412) node _T_454 = or(_T_453, _T_417) node _T_455 = or(_T_454, _T_422) node _T_456 = or(_T_455, _T_427) node _T_457 = or(_T_456, _T_432) node _T_458 = or(_T_457, _T_437) node _T_459 = or(_T_458, _T_442) node _T_460 = or(_T_459, _T_447) node _T_461 = or(_T_460, _T_452) node _T_462 = and(_T_402, _T_461) node _T_463 = or(UInt<1>(0h0), _T_398) node _T_464 = or(_T_463, _T_462) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_464, UInt<1>(0h1), "") : assert_20 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(is_aligned, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_474 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_474, UInt<1>(0h1), "") : assert_23 node _T_478 = eq(io.in.a.bits.mask, mask) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_478, UInt<1>(0h1), "") : assert_24 node _T_482 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_482, UInt<1>(0h1), "") : assert_25 node _T_486 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_486 : node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_488 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_489 = and(_T_487, _T_488) node _T_490 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(UInt<1>(0h0), _T_495) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = and(_T_496, _T_501) node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_505 = and(_T_503, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<14>(0h2000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<18>(0h2f000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<17>(0h10000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<13>(0h1000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<27>(0h4000000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<13>(0h1000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<19>(0h40000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<29>(0h10000000))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = or(_T_511, _T_516) node _T_553 = or(_T_552, _T_521) node _T_554 = or(_T_553, _T_526) node _T_555 = or(_T_554, _T_531) node _T_556 = or(_T_555, _T_536) node _T_557 = or(_T_556, _T_541) node _T_558 = or(_T_557, _T_546) node _T_559 = or(_T_558, _T_551) node _T_560 = and(_T_506, _T_559) node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_562 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<17>(0h10000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = and(_T_561, _T_566) node _T_568 = or(UInt<1>(0h0), _T_502) node _T_569 = or(_T_568, _T_560) node _T_570 = or(_T_569, _T_567) node _T_571 = and(_T_492, _T_570) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_571, UInt<1>(0h1), "") : assert_26 node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(is_aligned, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_581 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_581, UInt<1>(0h1), "") : assert_29 node _T_585 = eq(io.in.a.bits.mask, mask) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_585, UInt<1>(0h1), "") : assert_30 node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_589 : node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) node _T_595 = or(UInt<1>(0h0), _T_594) node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_598 = and(_T_596, _T_597) node _T_599 = or(UInt<1>(0h0), _T_598) node _T_600 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_601 = cvt(_T_600) node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000))) node _T_603 = asSInt(_T_602) node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0))) node _T_605 = and(_T_599, _T_604) node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<14>(0h2000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<18>(0h2f000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<13>(0h1000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<17>(0h10000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<27>(0h4000000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<13>(0h1000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<19>(0h40000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<29>(0h10000000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = or(_T_614, _T_619) node _T_656 = or(_T_655, _T_624) node _T_657 = or(_T_656, _T_629) node _T_658 = or(_T_657, _T_634) node _T_659 = or(_T_658, _T_639) node _T_660 = or(_T_659, _T_644) node _T_661 = or(_T_660, _T_649) node _T_662 = or(_T_661, _T_654) node _T_663 = and(_T_609, _T_662) node _T_664 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_665 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_605) node _T_672 = or(_T_671, _T_663) node _T_673 = or(_T_672, _T_670) node _T_674 = and(_T_595, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_674, UInt<1>(0h1), "") : assert_31 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_684, UInt<1>(0h1), "") : assert_34 node _T_688 = not(mask) node _T_689 = and(io.in.a.bits.mask, _T_688) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_690, UInt<1>(0h1), "") : assert_35 node _T_694 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_699 = and(_T_697, _T_698) node _T_700 = or(UInt<1>(0h0), _T_699) node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<14>(0h2000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<18>(0h2f000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<17>(0h10000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<13>(0h1000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<17>(0h10000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<27>(0h4000000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<13>(0h1000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<19>(0h40000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<29>(0h10000000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = or(_T_709, _T_714) node _T_756 = or(_T_755, _T_719) node _T_757 = or(_T_756, _T_724) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_739) node _T_761 = or(_T_760, _T_744) node _T_762 = or(_T_761, _T_749) node _T_763 = or(_T_762, _T_754) node _T_764 = and(_T_704, _T_763) node _T_765 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_766 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_764) node _T_773 = or(_T_772, _T_771) node _T_774 = and(_T_700, _T_773) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_774, UInt<1>(0h1), "") : assert_36 node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(is_aligned, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_784 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_784, UInt<1>(0h1), "") : assert_39 node _T_788 = eq(io.in.a.bits.mask, mask) node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(_T_788, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_788, UInt<1>(0h1), "") : assert_40 node _T_792 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_792 : node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_794 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_797 = and(_T_795, _T_796) node _T_798 = or(UInt<1>(0h0), _T_797) node _T_799 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_800 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_801 = and(_T_799, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<14>(0h2000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<13>(0h1000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<18>(0h2f000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<17>(0h10000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<13>(0h1000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<17>(0h10000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_834 = cvt(_T_833) node _T_835 = and(_T_834, asSInt(UInt<27>(0h4000000))) node _T_836 = asSInt(_T_835) node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) node _T_838 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<19>(0h40000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<29>(0h10000000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = or(_T_807, _T_812) node _T_854 = or(_T_853, _T_817) node _T_855 = or(_T_854, _T_822) node _T_856 = or(_T_855, _T_827) node _T_857 = or(_T_856, _T_832) node _T_858 = or(_T_857, _T_837) node _T_859 = or(_T_858, _T_842) node _T_860 = or(_T_859, _T_847) node _T_861 = or(_T_860, _T_852) node _T_862 = and(_T_802, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<17>(0h10000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = and(_T_863, _T_868) node _T_870 = or(UInt<1>(0h0), _T_862) node _T_871 = or(_T_870, _T_869) node _T_872 = and(_T_798, _T_871) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_872, UInt<1>(0h1), "") : assert_41 node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(is_aligned, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_882 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_882, UInt<1>(0h1), "") : assert_44 node _T_886 = eq(io.in.a.bits.mask, mask) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_886, UInt<1>(0h1), "") : assert_45 node _T_890 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_890 : node _T_891 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_892 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_893 = and(_T_891, _T_892) node _T_894 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_895 = and(_T_893, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = and(_T_900, _T_905) node _T_907 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_908 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_909 = cvt(_T_908) node _T_910 = and(_T_909, asSInt(UInt<14>(0h2000))) node _T_911 = asSInt(_T_910) node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0))) node _T_913 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<17>(0h10000))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<18>(0h2f000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<17>(0h10000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<13>(0h1000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<27>(0h4000000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_939 = cvt(_T_938) node _T_940 = and(_T_939, asSInt(UInt<13>(0h1000))) node _T_941 = asSInt(_T_940) node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0))) node _T_943 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_944 = cvt(_T_943) node _T_945 = and(_T_944, asSInt(UInt<19>(0h40000))) node _T_946 = asSInt(_T_945) node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0))) node _T_948 = or(_T_912, _T_917) node _T_949 = or(_T_948, _T_922) node _T_950 = or(_T_949, _T_927) node _T_951 = or(_T_950, _T_932) node _T_952 = or(_T_951, _T_937) node _T_953 = or(_T_952, _T_942) node _T_954 = or(_T_953, _T_947) node _T_955 = and(_T_907, _T_954) node _T_956 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_957 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_958 = and(_T_956, _T_957) node _T_959 = or(UInt<1>(0h0), _T_958) node _T_960 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_961 = cvt(_T_960) node _T_962 = and(_T_961, asSInt(UInt<17>(0h10000))) node _T_963 = asSInt(_T_962) node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0))) node _T_965 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_966 = cvt(_T_965) node _T_967 = and(_T_966, asSInt(UInt<29>(0h10000000))) node _T_968 = asSInt(_T_967) node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0))) node _T_970 = or(_T_964, _T_969) node _T_971 = and(_T_959, _T_970) node _T_972 = or(UInt<1>(0h0), _T_906) node _T_973 = or(_T_972, _T_955) node _T_974 = or(_T_973, _T_971) node _T_975 = and(_T_896, _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_975, UInt<1>(0h1), "") : assert_46 node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(is_aligned, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_985 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_985, UInt<1>(0h1), "") : assert_49 node _T_989 = eq(io.in.a.bits.mask, mask) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_989, UInt<1>(0h1), "") : assert_50 node _T_993 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_993, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_997 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_997, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1001 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1001 : node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_54 node _T_1009 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_55 node _T_1013 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_56 node _T_1017 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_57 node _T_1021 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1021 : node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(sink_ok, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1028 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_60 node _T_1032 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_61 node _T_1036 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_62 node _T_1040 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_63 node _T_1044 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1045 = or(UInt<1>(0h1), _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_64 node _T_1049 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1049 : node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(sink_ok, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1056 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_67 node _T_1060 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_68 node _T_1064 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_69 node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1069 = or(_T_1068, io.in.d.bits.corrupt) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_70 node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1074 = or(UInt<1>(0h1), _T_1073) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_71 node _T_1078 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1078 : node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_73 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_74 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = or(UInt<1>(0h1), _T_1090) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_75 node _T_1095 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1095 : node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1099 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_77 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(_T_1103, io.in.d.bits.corrupt) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_78 node _T_1108 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1109 = or(UInt<1>(0h1), _T_1108) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_79 node _T_1113 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1117 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_81 node _T_1121 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_82 node _T_1125 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1126 = or(UInt<1>(0h1), _T_1125) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1130 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1134 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1138 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1142 = eq(a_first, UInt<1>(0h0)) node _T_1143 = and(io.in.a.valid, _T_1142) when _T_1143 : node _T_1144 = eq(io.in.a.bits.opcode, opcode) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_87 node _T_1148 = eq(io.in.a.bits.param, param) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_88 node _T_1152 = eq(io.in.a.bits.size, size) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_89 node _T_1156 = eq(io.in.a.bits.source, source) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_90 node _T_1160 = eq(io.in.a.bits.address, address) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_91 node _T_1164 = and(io.in.a.ready, io.in.a.valid) node _T_1165 = and(_T_1164, a_first) when _T_1165 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1166 = eq(d_first, UInt<1>(0h0)) node _T_1167 = and(io.in.d.valid, _T_1166) when _T_1167 : node _T_1168 = eq(io.in.d.bits.opcode, opcode_1) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_92 node _T_1172 = eq(io.in.d.bits.param, param_1) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_93 node _T_1176 = eq(io.in.d.bits.size, size_1) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_94 node _T_1180 = eq(io.in.d.bits.source, source_1) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_95 node _T_1184 = eq(io.in.d.bits.sink, sink) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_96 node _T_1188 = eq(io.in.d.bits.denied, denied) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_97 node _T_1192 = and(io.in.d.ready, io.in.d.valid) node _T_1193 = and(_T_1192, d_first) when _T_1193 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1194 = and(io.in.a.valid, a_first_1) node _T_1195 = and(_T_1194, UInt<1>(0h1)) when _T_1195 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1196 = and(io.in.a.ready, io.in.a.valid) node _T_1197 = and(_T_1196, a_first_1) node _T_1198 = and(_T_1197, UInt<1>(0h1)) when _T_1198 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1199 = dshr(inflight, io.in.a.bits.source) node _T_1200 = bits(_T_1199, 0, 0) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1205 = and(io.in.d.valid, d_first_1) node _T_1206 = and(_T_1205, UInt<1>(0h1)) node _T_1207 = eq(d_release_ack, UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) when _T_1208 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1209 = and(io.in.d.ready, io.in.d.valid) node _T_1210 = and(_T_1209, d_first_1) node _T_1211 = and(_T_1210, UInt<1>(0h1)) node _T_1212 = eq(d_release_ack, UInt<1>(0h0)) node _T_1213 = and(_T_1211, _T_1212) when _T_1213 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1214 = and(io.in.d.valid, d_first_1) node _T_1215 = and(_T_1214, UInt<1>(0h1)) node _T_1216 = eq(d_release_ack, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1218 = dshr(inflight, io.in.d.bits.source) node _T_1219 = bits(_T_1218, 0, 0) node _T_1220 = or(_T_1219, same_cycle_resp) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1224 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1225 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1226 = or(_T_1224, _T_1225) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_100 node _T_1230 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_101 else : node _T_1234 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1236 = or(_T_1234, _T_1235) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_102 node _T_1240 = eq(io.in.d.bits.size, a_size_lookup) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_103 node _T_1244 = and(io.in.d.valid, d_first_1) node _T_1245 = and(_T_1244, a_first_1) node _T_1246 = and(_T_1245, io.in.a.valid) node _T_1247 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1248 = and(_T_1246, _T_1247) node _T_1249 = eq(d_release_ack, UInt<1>(0h0)) node _T_1250 = and(_T_1248, _T_1249) when _T_1250 : node _T_1251 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1252 = or(_T_1251, io.in.a.ready) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_104 node _T_1256 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1257 = orr(a_set_wo_ready) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) node _T_1259 = or(_T_1256, _T_1258) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_149 node _T_1263 = orr(inflight) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1266 = or(_T_1264, _T_1265) node _T_1267 = lt(watchdog, plusarg_reader.out) node _T_1268 = or(_T_1266, _T_1267) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1272 = and(io.in.a.ready, io.in.a.valid) node _T_1273 = and(io.in.d.ready, io.in.d.valid) node _T_1274 = or(_T_1272, _T_1273) when _T_1274 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1275 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1276 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1277 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = and(_T_1275, _T_1278) when _T_1279 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1280 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1281 = and(_T_1280, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1282 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1283 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1284 = and(_T_1282, _T_1283) node _T_1285 = and(_T_1281, _T_1284) when _T_1285 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1286 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1287 = bits(_T_1286, 0, 0) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1292 = and(io.in.d.valid, d_first_2) node _T_1293 = and(_T_1292, UInt<1>(0h1)) node _T_1294 = and(_T_1293, d_release_ack_1) when _T_1294 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1295 = and(io.in.d.ready, io.in.d.valid) node _T_1296 = and(_T_1295, d_first_2) node _T_1297 = and(_T_1296, UInt<1>(0h1)) node _T_1298 = and(_T_1297, d_release_ack_1) when _T_1298 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1299 = and(io.in.d.valid, d_first_2) node _T_1300 = and(_T_1299, UInt<1>(0h1)) node _T_1301 = and(_T_1300, d_release_ack_1) when _T_1301 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1302 = dshr(inflight_1, io.in.d.bits.source) node _T_1303 = bits(_T_1302, 0, 0) node _T_1304 = or(_T_1303, same_cycle_resp_1) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1308 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_109 else : node _T_1312 = eq(io.in.d.bits.size, c_size_lookup) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_110 node _T_1316 = and(io.in.d.valid, d_first_2) node _T_1317 = and(_T_1316, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1318 = and(_T_1317, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1319 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = and(_T_1320, d_release_ack_1) node _T_1322 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1323 = and(_T_1321, _T_1322) when _T_1323 : node _T_1324 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1325 = or(_T_1324, _WIRE_23.ready) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_111 node _T_1329 = orr(c_set_wo_ready) when _T_1329 : node _T_1330 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_150 node _T_1334 = orr(inflight_1) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) node _T_1336 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1337 = or(_T_1335, _T_1336) node _T_1338 = lt(watchdog_1, plusarg_reader_1.out) node _T_1339 = or(_T_1337, _T_1338) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1343 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1344 = and(io.in.d.ready, io.in.d.valid) node _T_1345 = or(_T_1343, _T_1344) when _T_1345 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_72( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SimpleHellaCacheIF_1 : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, cache : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} invalidate io.cache.clock_enabled invalidate io.cache.keep_clock_enabled invalidate io.cache.perf.storeBufferEmptyAfterStore invalidate io.cache.perf.storeBufferEmptyAfterLoad invalidate io.cache.perf.canAcceptLoadThenLoad invalidate io.cache.perf.canAcceptStoreThenRMW invalidate io.cache.perf.canAcceptStoreThenLoad invalidate io.cache.perf.blocked invalidate io.cache.perf.tlbMiss invalidate io.cache.perf.grant invalidate io.cache.perf.release invalidate io.cache.perf.acquire invalidate io.cache.store_pending invalidate io.cache.ordered invalidate io.cache.s2_gpa_is_pte invalidate io.cache.s2_gpa invalidate io.cache.s2_xcpt.ae.st invalidate io.cache.s2_xcpt.ae.ld invalidate io.cache.s2_xcpt.gf.st invalidate io.cache.s2_xcpt.gf.ld invalidate io.cache.s2_xcpt.pf.st invalidate io.cache.s2_xcpt.pf.ld invalidate io.cache.s2_xcpt.ma.st invalidate io.cache.s2_xcpt.ma.ld invalidate io.cache.replay_next invalidate io.cache.resp.bits.store_data invalidate io.cache.resp.bits.data_raw invalidate io.cache.resp.bits.data_word_bypass invalidate io.cache.resp.bits.has_data invalidate io.cache.resp.bits.replay invalidate io.cache.resp.bits.mask invalidate io.cache.resp.bits.data invalidate io.cache.resp.bits.dv invalidate io.cache.resp.bits.dprv invalidate io.cache.resp.bits.signed invalidate io.cache.resp.bits.size invalidate io.cache.resp.bits.cmd invalidate io.cache.resp.bits.tag invalidate io.cache.resp.bits.addr invalidate io.cache.resp.valid invalidate io.cache.s2_paddr invalidate io.cache.s2_uncached invalidate io.cache.s2_kill invalidate io.cache.s2_nack_cause_raw invalidate io.cache.s2_nack invalidate io.cache.s1_data.mask invalidate io.cache.s1_data.data invalidate io.cache.s1_kill invalidate io.cache.req.bits.mask invalidate io.cache.req.bits.data invalidate io.cache.req.bits.no_xcpt invalidate io.cache.req.bits.no_alloc invalidate io.cache.req.bits.no_resp invalidate io.cache.req.bits.phys invalidate io.cache.req.bits.dv invalidate io.cache.req.bits.dprv invalidate io.cache.req.bits.signed invalidate io.cache.req.bits.size invalidate io.cache.req.bits.cmd invalidate io.cache.req.bits.tag invalidate io.cache.req.bits.addr invalidate io.cache.req.valid invalidate io.cache.req.ready invalidate io.requestor.clock_enabled invalidate io.requestor.keep_clock_enabled invalidate io.requestor.perf.storeBufferEmptyAfterStore invalidate io.requestor.perf.storeBufferEmptyAfterLoad invalidate io.requestor.perf.canAcceptLoadThenLoad invalidate io.requestor.perf.canAcceptStoreThenRMW invalidate io.requestor.perf.canAcceptStoreThenLoad invalidate io.requestor.perf.blocked invalidate io.requestor.perf.tlbMiss invalidate io.requestor.perf.grant invalidate io.requestor.perf.release invalidate io.requestor.perf.acquire invalidate io.requestor.store_pending invalidate io.requestor.ordered invalidate io.requestor.s2_gpa_is_pte invalidate io.requestor.s2_gpa invalidate io.requestor.s2_xcpt.ae.st invalidate io.requestor.s2_xcpt.ae.ld invalidate io.requestor.s2_xcpt.gf.st invalidate io.requestor.s2_xcpt.gf.ld invalidate io.requestor.s2_xcpt.pf.st invalidate io.requestor.s2_xcpt.pf.ld invalidate io.requestor.s2_xcpt.ma.st invalidate io.requestor.s2_xcpt.ma.ld invalidate io.requestor.replay_next invalidate io.requestor.resp.bits.store_data invalidate io.requestor.resp.bits.data_raw invalidate io.requestor.resp.bits.data_word_bypass invalidate io.requestor.resp.bits.has_data invalidate io.requestor.resp.bits.replay invalidate io.requestor.resp.bits.mask invalidate io.requestor.resp.bits.data invalidate io.requestor.resp.bits.dv invalidate io.requestor.resp.bits.dprv invalidate io.requestor.resp.bits.signed invalidate io.requestor.resp.bits.size invalidate io.requestor.resp.bits.cmd invalidate io.requestor.resp.bits.tag invalidate io.requestor.resp.bits.addr invalidate io.requestor.resp.valid invalidate io.requestor.s2_paddr invalidate io.requestor.s2_uncached invalidate io.requestor.s2_kill invalidate io.requestor.s2_nack_cause_raw invalidate io.requestor.s2_nack invalidate io.requestor.s1_data.mask invalidate io.requestor.s1_data.data invalidate io.requestor.s1_kill invalidate io.requestor.req.bits.mask invalidate io.requestor.req.bits.data invalidate io.requestor.req.bits.no_xcpt invalidate io.requestor.req.bits.no_alloc invalidate io.requestor.req.bits.no_resp invalidate io.requestor.req.bits.phys invalidate io.requestor.req.bits.dv invalidate io.requestor.req.bits.dprv invalidate io.requestor.req.bits.signed invalidate io.requestor.req.bits.size invalidate io.requestor.req.bits.cmd invalidate io.requestor.req.bits.tag invalidate io.requestor.req.bits.addr invalidate io.requestor.req.valid invalidate io.requestor.req.ready inst replayq of SimpleHellaCacheIFReplayQueue_1 connect replayq.clock, clock connect replayq.reset, reset inst req_arb of Arbiter2_HellaCacheReq_1 connect req_arb.clock, clock connect req_arb.reset, reset connect req_arb.io.in[0], replayq.io.replay node _req_arb_io_in_1_valid_T = and(replayq.io.req.ready, io.requestor.req.valid) connect req_arb.io.in[1].valid, _req_arb_io_in_1_valid_T connect req_arb.io.in[1].bits.mask, io.requestor.req.bits.mask connect req_arb.io.in[1].bits.data, io.requestor.req.bits.data connect req_arb.io.in[1].bits.no_xcpt, io.requestor.req.bits.no_xcpt connect req_arb.io.in[1].bits.no_alloc, io.requestor.req.bits.no_alloc connect req_arb.io.in[1].bits.no_resp, io.requestor.req.bits.no_resp connect req_arb.io.in[1].bits.phys, io.requestor.req.bits.phys connect req_arb.io.in[1].bits.dv, io.requestor.req.bits.dv connect req_arb.io.in[1].bits.dprv, io.requestor.req.bits.dprv connect req_arb.io.in[1].bits.signed, io.requestor.req.bits.signed connect req_arb.io.in[1].bits.size, io.requestor.req.bits.size connect req_arb.io.in[1].bits.cmd, io.requestor.req.bits.cmd connect req_arb.io.in[1].bits.tag, io.requestor.req.bits.tag connect req_arb.io.in[1].bits.addr, io.requestor.req.bits.addr node _io_requestor_req_ready_T = and(req_arb.io.in[1].ready, replayq.io.req.ready) connect io.requestor.req.ready, _io_requestor_req_ready_T node _replayq_io_req_valid_T = and(req_arb.io.in[1].ready, io.requestor.req.valid) connect replayq.io.req.valid, _replayq_io_req_valid_T connect replayq.io.req.bits.mask, io.requestor.req.bits.mask connect replayq.io.req.bits.data, io.requestor.req.bits.data connect replayq.io.req.bits.no_xcpt, io.requestor.req.bits.no_xcpt connect replayq.io.req.bits.no_alloc, io.requestor.req.bits.no_alloc connect replayq.io.req.bits.no_resp, io.requestor.req.bits.no_resp connect replayq.io.req.bits.phys, io.requestor.req.bits.phys connect replayq.io.req.bits.dv, io.requestor.req.bits.dv connect replayq.io.req.bits.dprv, io.requestor.req.bits.dprv connect replayq.io.req.bits.signed, io.requestor.req.bits.signed connect replayq.io.req.bits.size, io.requestor.req.bits.size connect replayq.io.req.bits.cmd, io.requestor.req.bits.cmd connect replayq.io.req.bits.tag, io.requestor.req.bits.tag connect replayq.io.req.bits.addr, io.requestor.req.bits.addr node s0_req_fire = and(io.cache.req.ready, io.cache.req.valid) reg s1_req_fire : UInt<1>, clock connect s1_req_fire, s0_req_fire reg s2_req_fire : UInt<1>, clock connect s2_req_fire, s1_req_fire reg s1_req_tag : UInt, clock connect s1_req_tag, io.cache.req.bits.tag reg s2_req_tag : UInt, clock connect s2_req_tag, s1_req_tag reg REG : UInt<1>, clock connect REG, io.cache.s2_nack node _T = eq(REG, UInt<1>(0h0)) node _T_1 = eq(s2_req_fire, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = or(_T_2, io.cache.s2_nack) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SimpleHellaCacheIF.scala:124 assert(!RegNext(io.cache.s2_nack) || !s2_req_fire || io.cache.s2_nack)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _T_7 = eq(io.cache.s2_nack, UInt<1>(0h0)) node _T_8 = eq(io.cache.req.ready, UInt<1>(0h0)) node _T_9 = or(_T_7, _T_8) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SimpleHellaCacheIF.scala:125 assert(!io.cache.s2_nack || !io.cache.req.ready)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 connect io.cache.req.bits, req_arb.io.out.bits connect io.cache.req.valid, req_arb.io.out.valid connect req_arb.io.out.ready, io.cache.req.ready connect io.cache.s1_kill, UInt<1>(0h0) reg io_cache_s1_data_r : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock when s0_req_fire : connect io_cache_s1_data_r, req_arb.io.out.bits connect io.cache.s1_data.mask, io_cache_s1_data_r.mask connect io.cache.s1_data.data, io_cache_s1_data_r.data connect io.cache.s2_kill, UInt<1>(0h0) node _replayq_io_nack_valid_T = and(io.cache.s2_nack, s2_req_fire) connect replayq.io.nack.valid, _replayq_io_nack_valid_T connect replayq.io.nack.bits, s2_req_tag connect replayq.io.resp.bits.store_data, io.cache.resp.bits.store_data connect replayq.io.resp.bits.data_raw, io.cache.resp.bits.data_raw connect replayq.io.resp.bits.data_word_bypass, io.cache.resp.bits.data_word_bypass connect replayq.io.resp.bits.has_data, io.cache.resp.bits.has_data connect replayq.io.resp.bits.replay, io.cache.resp.bits.replay connect replayq.io.resp.bits.mask, io.cache.resp.bits.mask connect replayq.io.resp.bits.data, io.cache.resp.bits.data connect replayq.io.resp.bits.dv, io.cache.resp.bits.dv connect replayq.io.resp.bits.dprv, io.cache.resp.bits.dprv connect replayq.io.resp.bits.signed, io.cache.resp.bits.signed connect replayq.io.resp.bits.size, io.cache.resp.bits.size connect replayq.io.resp.bits.cmd, io.cache.resp.bits.cmd connect replayq.io.resp.bits.tag, io.cache.resp.bits.tag connect replayq.io.resp.bits.addr, io.cache.resp.bits.addr connect replayq.io.resp.valid, io.cache.resp.valid connect io.requestor.resp, io.cache.resp node _T_13 = eq(s2_req_fire, UInt<1>(0h0)) node _T_14 = cat(io.cache.s2_xcpt.ae.ld, io.cache.s2_xcpt.ae.st) node _T_15 = cat(io.cache.s2_xcpt.gf.ld, io.cache.s2_xcpt.gf.st) node _T_16 = cat(io.cache.s2_xcpt.pf.ld, io.cache.s2_xcpt.pf.st) node _T_17 = cat(io.cache.s2_xcpt.ma.ld, io.cache.s2_xcpt.ma.st) node lo = cat(_T_15, _T_14) node hi = cat(_T_17, _T_16) node _T_18 = cat(hi, lo) node _T_19 = orr(_T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = or(_T_13, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed: SimpleHellaCacheIF exception\n at SimpleHellaCacheIF.scala:137 assert(!s2_req_fire || !io.cache.s2_xcpt.asUInt.orR, \"SimpleHellaCacheIF exception\")\n") : printf_2 assert(clock, _T_21, UInt<1>(0h1), "") : assert_2
module SimpleHellaCacheIF_1( // @[SimpleHellaCacheIF.scala:95:7] input clock, // @[SimpleHellaCacheIF.scala:95:7] input reset, // @[SimpleHellaCacheIF.scala:95:7] output io_requestor_req_ready, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_valid, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_requestor_req_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_requestor_req_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_requestor_req_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] output [39:0] io_requestor_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_requestor_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] output [4:0] io_requestor_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_requestor_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_requestor_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_requestor_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_req_ready, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_valid, // @[SimpleHellaCacheIF.scala:97:14] output [39:0] io_cache_req_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_cache_req_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_cache_req_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_cache_s1_data_data, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_cache_s1_data_mask, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_nack, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_nack_cause_raw, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_uncached, // @[SimpleHellaCacheIF.scala:97:14] input [31:0] io_cache_s2_paddr, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_cache_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_cache_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] input [4:0] io_cache_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_cache_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_cache_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_cache_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_replay_next, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_st, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_cache_s2_gpa, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_ordered, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_store_pending, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_acquire, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_release, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_grant, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_tlbMiss, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_blocked, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptStoreThenLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptStoreThenRMW, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptLoadThenLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_storeBufferEmptyAfterLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_storeBufferEmptyAfterStore // @[SimpleHellaCacheIF.scala:97:14] ); wire _req_arb_io_in_0_ready; // @[SimpleHellaCacheIF.scala:104:23] wire _req_arb_io_in_1_ready; // @[SimpleHellaCacheIF.scala:104:23] wire [39:0] _req_arb_io_out_bits_addr; // @[SimpleHellaCacheIF.scala:104:23] wire [7:0] _req_arb_io_out_bits_tag; // @[SimpleHellaCacheIF.scala:104:23] wire [1:0] _req_arb_io_out_bits_dprv; // @[SimpleHellaCacheIF.scala:104:23] wire _req_arb_io_out_bits_dv; // @[SimpleHellaCacheIF.scala:104:23] wire _replayq_io_req_ready; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_valid; // @[SimpleHellaCacheIF.scala:103:23] wire [39:0] _replayq_io_replay_bits_addr; // @[SimpleHellaCacheIF.scala:103:23] wire [7:0] _replayq_io_replay_bits_tag; // @[SimpleHellaCacheIF.scala:103:23] wire [1:0] _replayq_io_replay_bits_dprv; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_bits_dv; // @[SimpleHellaCacheIF.scala:103:23] wire io_requestor_req_valid_0 = io_requestor_req_valid; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_req_bits_addr_0 = io_requestor_req_bits_addr; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_req_bits_tag_0 = io_requestor_req_bits_tag; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_req_bits_dprv_0 = io_requestor_req_bits_dprv; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_dv_0 = io_requestor_req_bits_dv; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_ready_0 = io_cache_req_ready; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_nack_0 = io_cache_s2_nack; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_nack_cause_raw_0 = io_cache_s2_nack_cause_raw; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_uncached_0 = io_cache_s2_uncached; // @[SimpleHellaCacheIF.scala:95:7] wire [31:0] io_cache_s2_paddr_0 = io_cache_s2_paddr; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_valid_0 = io_cache_resp_valid; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_resp_bits_addr_0 = io_cache_resp_bits_addr; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_resp_bits_tag_0 = io_cache_resp_bits_tag; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_cache_resp_bits_cmd_0 = io_cache_resp_bits_cmd; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_resp_bits_size_0 = io_cache_resp_bits_size; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_signed_0 = io_cache_resp_bits_signed; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_resp_bits_dprv_0 = io_cache_resp_bits_dprv; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_dv_0 = io_cache_resp_bits_dv; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_0 = io_cache_resp_bits_data; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_resp_bits_mask_0 = io_cache_resp_bits_mask; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_replay_0 = io_cache_resp_bits_replay; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_has_data_0 = io_cache_resp_bits_has_data; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_store_data_0 = io_cache_resp_bits_store_data; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_replay_next_0 = io_cache_replay_next; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ma_ld_0 = io_cache_s2_xcpt_ma_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ma_st_0 = io_cache_s2_xcpt_ma_st; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_pf_ld_0 = io_cache_s2_xcpt_pf_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_pf_st_0 = io_cache_s2_xcpt_pf_st; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ae_ld_0 = io_cache_s2_xcpt_ae_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ae_st_0 = io_cache_s2_xcpt_ae_st; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_s2_gpa_0 = io_cache_s2_gpa; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_ordered_0 = io_cache_ordered; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_store_pending_0 = io_cache_store_pending; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_acquire_0 = io_cache_perf_acquire; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_release_0 = io_cache_perf_release; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_grant_0 = io_cache_perf_grant; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_tlbMiss_0 = io_cache_perf_tlbMiss; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_blocked_0 = io_cache_perf_blocked; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptStoreThenLoad_0 = io_cache_perf_canAcceptStoreThenLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptStoreThenRMW_0 = io_cache_perf_canAcceptStoreThenRMW; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptLoadThenLoad_0 = io_cache_perf_canAcceptLoadThenLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_storeBufferEmptyAfterLoad_0 = io_cache_perf_storeBufferEmptyAfterLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_storeBufferEmptyAfterStore_0 = io_cache_perf_storeBufferEmptyAfterStore; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_requestor_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_cache_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_req_bits_size = 2'h3; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_req_bits_size = 2'h3; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_nack = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_nack_cause_raw = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_uncached = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_replay_next = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ma_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ma_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_pf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_pf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ae_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ae_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_ordered = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_store_pending = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_acquire = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_release = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_grant = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_tlbMiss = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_blocked = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptStoreThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptStoreThenRMW = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptLoadThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_storeBufferEmptyAfterLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_storeBufferEmptyAfterStore = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_keep_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_keep_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_s1_data_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_s1_data_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_clock_enabled = 1'h1; // @[SimpleHellaCacheIF.scala:95:7] wire [31:0] io_requestor_s2_paddr = 32'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_s2_gpa = 40'h0; // @[SimpleHellaCacheIF.scala:95:7] wire _io_requestor_req_ready_T; // @[Misc.scala:26:53] wire io_requestor_resp_valid_0 = io_cache_resp_valid_0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_resp_bits_addr_0 = io_cache_resp_bits_addr_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_resp_bits_tag_0 = io_cache_resp_bits_tag_0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_requestor_resp_bits_cmd_0 = io_cache_resp_bits_cmd_0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_resp_bits_size_0 = io_cache_resp_bits_size_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_signed_0 = io_cache_resp_bits_signed_0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_resp_bits_dprv_0 = io_cache_resp_bits_dprv_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_dv_0 = io_cache_resp_bits_dv_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_0 = io_cache_resp_bits_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_resp_bits_mask_0 = io_cache_resp_bits_mask_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_replay_0 = io_cache_resp_bits_replay_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_has_data_0 = io_cache_resp_bits_has_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_store_data_0 = io_cache_resp_bits_store_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_ready_0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_req_bits_addr_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_req_bits_tag_0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_req_bits_dprv_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_dv_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_valid_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_s1_data_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_s1_data_mask_0; // @[SimpleHellaCacheIF.scala:95:7] wire _req_arb_io_in_1_valid_T = _replayq_io_req_ready & io_requestor_req_valid_0; // @[Misc.scala:26:53] assign _io_requestor_req_ready_T = _req_arb_io_in_1_ready & _replayq_io_req_ready; // @[Misc.scala:26:53] assign io_requestor_req_ready_0 = _io_requestor_req_ready_T; // @[Misc.scala:26:53] wire _replayq_io_req_valid_T = _req_arb_io_in_1_ready & io_requestor_req_valid_0; // @[Misc.scala:26:53] wire s0_req_fire = io_cache_req_ready_0 & io_cache_req_valid_0; // @[Decoupled.scala:51:35] reg s1_req_fire; // @[SimpleHellaCacheIF.scala:119:28] reg s2_req_fire; // @[SimpleHellaCacheIF.scala:120:28] reg [7:0] s1_req_tag; // @[SimpleHellaCacheIF.scala:121:27] reg [7:0] s2_req_tag; // @[SimpleHellaCacheIF.scala:122:27] reg REG; // @[SimpleHellaCacheIF.scala:124:18] reg [39:0] io_cache_s1_data_r_addr; // @[SimpleHellaCacheIF.scala:129:32] reg [7:0] io_cache_s1_data_r_tag; // @[SimpleHellaCacheIF.scala:129:32] reg [4:0] io_cache_s1_data_r_cmd; // @[SimpleHellaCacheIF.scala:129:32] reg [1:0] io_cache_s1_data_r_size; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_signed; // @[SimpleHellaCacheIF.scala:129:32] reg [1:0] io_cache_s1_data_r_dprv; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_dv; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_phys; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_resp; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_alloc; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_xcpt; // @[SimpleHellaCacheIF.scala:129:32] reg [63:0] io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:129:32] assign io_cache_s1_data_data_0 = io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:95:7, :129:32] reg [7:0] io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:129:32] assign io_cache_s1_data_mask_0 = io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:95:7, :129:32] wire _replayq_io_nack_valid_T = io_cache_s2_nack_0 & s2_req_fire; // @[SimpleHellaCacheIF.scala:95:7, :120:28, :132:45] wire [3:0] lo = {2'h0, io_cache_s2_xcpt_ae_ld_0, io_cache_s2_xcpt_ae_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44] wire [3:0] hi = {io_cache_s2_xcpt_ma_ld_0, io_cache_s2_xcpt_ma_st_0, io_cache_s2_xcpt_pf_ld_0, io_cache_s2_xcpt_pf_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44]
Generate the Verilog code corresponding to this FIRRTL code module TSIToTileLink : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, state : UInt} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut reg cmd : UInt<32>, clock reg addr : UInt<64>, clock reg len : UInt<64>, clock reg body : UInt<32>[2], clock reg bodyValid : UInt<2>, clock reg idx : UInt<1>, clock regreset state : UInt<4>, clock, reset, UInt<4>(0h0) connect io.state, state node _io_tsi_in_ready_T = eq(state, UInt<4>(0h0)) node _io_tsi_in_ready_T_1 = eq(state, UInt<4>(0h1)) node _io_tsi_in_ready_T_2 = eq(state, UInt<4>(0h2)) node _io_tsi_in_ready_T_3 = eq(state, UInt<4>(0h6)) node _io_tsi_in_ready_T_4 = or(_io_tsi_in_ready_T, _io_tsi_in_ready_T_1) node _io_tsi_in_ready_T_5 = or(_io_tsi_in_ready_T_4, _io_tsi_in_ready_T_2) node _io_tsi_in_ready_T_6 = or(_io_tsi_in_ready_T_5, _io_tsi_in_ready_T_3) connect io.tsi.in.ready, _io_tsi_in_ready_T_6 node _io_tsi_out_valid_T = eq(state, UInt<4>(0h5)) connect io.tsi.out.valid, _io_tsi_out_valid_T connect io.tsi.out.bits, body[idx] node beatAddr = bits(addr, 31, 3) node _nextAddr_T = add(beatAddr, UInt<1>(0h1)) node _nextAddr_T_1 = tail(_nextAddr_T, 1) node nextAddr = cat(_nextAddr_T_1, UInt<3>(0h0)) node _wmask_T = bits(bodyValid, 0, 0) node _wmask_T_1 = bits(bodyValid, 1, 1) node _wmask_T_2 = mux(_wmask_T, UInt<4>(0hf), UInt<4>(0h0)) node _wmask_T_3 = mux(_wmask_T_1, UInt<4>(0hf), UInt<4>(0h0)) node wmask = cat(_wmask_T_3, _wmask_T_2) node _addr_size_T = sub(nextAddr, addr) node addr_size = tail(_addr_size_T, 1) node _len_size_T = add(len, UInt<1>(0h1)) node _len_size_T_1 = tail(_len_size_T, 1) node len_size = cat(_len_size_T_1, UInt<2>(0h0)) node _raw_size_T = lt(len_size, addr_size) node raw_size = mux(_raw_size_T, len_size, addr_size) node _rsize_T = eq(UInt<1>(0h1), raw_size) node _rsize_T_1 = mux(_rsize_T, UInt<1>(0h0), UInt<2>(0h3)) node _rsize_T_2 = eq(UInt<2>(0h2), raw_size) node _rsize_T_3 = mux(_rsize_T_2, UInt<1>(0h1), _rsize_T_1) node _rsize_T_4 = eq(UInt<3>(0h4), raw_size) node rsize = mux(_rsize_T_4, UInt<2>(0h2), _rsize_T_3) node _pow2size_T = bits(raw_size, 0, 0) node _pow2size_T_1 = bits(raw_size, 1, 1) node _pow2size_T_2 = bits(raw_size, 2, 2) node _pow2size_T_3 = bits(raw_size, 3, 3) node _pow2size_T_4 = bits(raw_size, 4, 4) node _pow2size_T_5 = bits(raw_size, 5, 5) node _pow2size_T_6 = bits(raw_size, 6, 6) node _pow2size_T_7 = bits(raw_size, 7, 7) node _pow2size_T_8 = bits(raw_size, 8, 8) node _pow2size_T_9 = bits(raw_size, 9, 9) node _pow2size_T_10 = bits(raw_size, 10, 10) node _pow2size_T_11 = bits(raw_size, 11, 11) node _pow2size_T_12 = bits(raw_size, 12, 12) node _pow2size_T_13 = bits(raw_size, 13, 13) node _pow2size_T_14 = bits(raw_size, 14, 14) node _pow2size_T_15 = bits(raw_size, 15, 15) node _pow2size_T_16 = bits(raw_size, 16, 16) node _pow2size_T_17 = bits(raw_size, 17, 17) node _pow2size_T_18 = bits(raw_size, 18, 18) node _pow2size_T_19 = bits(raw_size, 19, 19) node _pow2size_T_20 = bits(raw_size, 20, 20) node _pow2size_T_21 = bits(raw_size, 21, 21) node _pow2size_T_22 = bits(raw_size, 22, 22) node _pow2size_T_23 = bits(raw_size, 23, 23) node _pow2size_T_24 = bits(raw_size, 24, 24) node _pow2size_T_25 = bits(raw_size, 25, 25) node _pow2size_T_26 = bits(raw_size, 26, 26) node _pow2size_T_27 = bits(raw_size, 27, 27) node _pow2size_T_28 = bits(raw_size, 28, 28) node _pow2size_T_29 = bits(raw_size, 29, 29) node _pow2size_T_30 = bits(raw_size, 30, 30) node _pow2size_T_31 = bits(raw_size, 31, 31) node _pow2size_T_32 = bits(raw_size, 32, 32) node _pow2size_T_33 = bits(raw_size, 33, 33) node _pow2size_T_34 = bits(raw_size, 34, 34) node _pow2size_T_35 = bits(raw_size, 35, 35) node _pow2size_T_36 = bits(raw_size, 36, 36) node _pow2size_T_37 = bits(raw_size, 37, 37) node _pow2size_T_38 = bits(raw_size, 38, 38) node _pow2size_T_39 = bits(raw_size, 39, 39) node _pow2size_T_40 = bits(raw_size, 40, 40) node _pow2size_T_41 = bits(raw_size, 41, 41) node _pow2size_T_42 = bits(raw_size, 42, 42) node _pow2size_T_43 = bits(raw_size, 43, 43) node _pow2size_T_44 = bits(raw_size, 44, 44) node _pow2size_T_45 = bits(raw_size, 45, 45) node _pow2size_T_46 = bits(raw_size, 46, 46) node _pow2size_T_47 = bits(raw_size, 47, 47) node _pow2size_T_48 = bits(raw_size, 48, 48) node _pow2size_T_49 = bits(raw_size, 49, 49) node _pow2size_T_50 = bits(raw_size, 50, 50) node _pow2size_T_51 = bits(raw_size, 51, 51) node _pow2size_T_52 = bits(raw_size, 52, 52) node _pow2size_T_53 = bits(raw_size, 53, 53) node _pow2size_T_54 = bits(raw_size, 54, 54) node _pow2size_T_55 = bits(raw_size, 55, 55) node _pow2size_T_56 = bits(raw_size, 56, 56) node _pow2size_T_57 = bits(raw_size, 57, 57) node _pow2size_T_58 = bits(raw_size, 58, 58) node _pow2size_T_59 = bits(raw_size, 59, 59) node _pow2size_T_60 = bits(raw_size, 60, 60) node _pow2size_T_61 = bits(raw_size, 61, 61) node _pow2size_T_62 = bits(raw_size, 62, 62) node _pow2size_T_63 = bits(raw_size, 63, 63) node _pow2size_T_64 = bits(raw_size, 64, 64) node _pow2size_T_65 = bits(raw_size, 65, 65) node _pow2size_T_66 = add(_pow2size_T, _pow2size_T_1) node _pow2size_T_67 = bits(_pow2size_T_66, 1, 0) node _pow2size_T_68 = add(_pow2size_T_2, _pow2size_T_3) node _pow2size_T_69 = bits(_pow2size_T_68, 1, 0) node _pow2size_T_70 = add(_pow2size_T_67, _pow2size_T_69) node _pow2size_T_71 = bits(_pow2size_T_70, 2, 0) node _pow2size_T_72 = add(_pow2size_T_4, _pow2size_T_5) node _pow2size_T_73 = bits(_pow2size_T_72, 1, 0) node _pow2size_T_74 = add(_pow2size_T_6, _pow2size_T_7) node _pow2size_T_75 = bits(_pow2size_T_74, 1, 0) node _pow2size_T_76 = add(_pow2size_T_73, _pow2size_T_75) node _pow2size_T_77 = bits(_pow2size_T_76, 2, 0) node _pow2size_T_78 = add(_pow2size_T_71, _pow2size_T_77) node _pow2size_T_79 = bits(_pow2size_T_78, 3, 0) node _pow2size_T_80 = add(_pow2size_T_8, _pow2size_T_9) node _pow2size_T_81 = bits(_pow2size_T_80, 1, 0) node _pow2size_T_82 = add(_pow2size_T_10, _pow2size_T_11) node _pow2size_T_83 = bits(_pow2size_T_82, 1, 0) node _pow2size_T_84 = add(_pow2size_T_81, _pow2size_T_83) node _pow2size_T_85 = bits(_pow2size_T_84, 2, 0) node _pow2size_T_86 = add(_pow2size_T_12, _pow2size_T_13) node _pow2size_T_87 = bits(_pow2size_T_86, 1, 0) node _pow2size_T_88 = add(_pow2size_T_14, _pow2size_T_15) node _pow2size_T_89 = bits(_pow2size_T_88, 1, 0) node _pow2size_T_90 = add(_pow2size_T_87, _pow2size_T_89) node _pow2size_T_91 = bits(_pow2size_T_90, 2, 0) node _pow2size_T_92 = add(_pow2size_T_85, _pow2size_T_91) node _pow2size_T_93 = bits(_pow2size_T_92, 3, 0) node _pow2size_T_94 = add(_pow2size_T_79, _pow2size_T_93) node _pow2size_T_95 = bits(_pow2size_T_94, 4, 0) node _pow2size_T_96 = add(_pow2size_T_16, _pow2size_T_17) node _pow2size_T_97 = bits(_pow2size_T_96, 1, 0) node _pow2size_T_98 = add(_pow2size_T_18, _pow2size_T_19) node _pow2size_T_99 = bits(_pow2size_T_98, 1, 0) node _pow2size_T_100 = add(_pow2size_T_97, _pow2size_T_99) node _pow2size_T_101 = bits(_pow2size_T_100, 2, 0) node _pow2size_T_102 = add(_pow2size_T_20, _pow2size_T_21) node _pow2size_T_103 = bits(_pow2size_T_102, 1, 0) node _pow2size_T_104 = add(_pow2size_T_22, _pow2size_T_23) node _pow2size_T_105 = bits(_pow2size_T_104, 1, 0) node _pow2size_T_106 = add(_pow2size_T_103, _pow2size_T_105) node _pow2size_T_107 = bits(_pow2size_T_106, 2, 0) node _pow2size_T_108 = add(_pow2size_T_101, _pow2size_T_107) node _pow2size_T_109 = bits(_pow2size_T_108, 3, 0) node _pow2size_T_110 = add(_pow2size_T_24, _pow2size_T_25) node _pow2size_T_111 = bits(_pow2size_T_110, 1, 0) node _pow2size_T_112 = add(_pow2size_T_26, _pow2size_T_27) node _pow2size_T_113 = bits(_pow2size_T_112, 1, 0) node _pow2size_T_114 = add(_pow2size_T_111, _pow2size_T_113) node _pow2size_T_115 = bits(_pow2size_T_114, 2, 0) node _pow2size_T_116 = add(_pow2size_T_28, _pow2size_T_29) node _pow2size_T_117 = bits(_pow2size_T_116, 1, 0) node _pow2size_T_118 = add(_pow2size_T_31, _pow2size_T_32) node _pow2size_T_119 = bits(_pow2size_T_118, 1, 0) node _pow2size_T_120 = add(_pow2size_T_30, _pow2size_T_119) node _pow2size_T_121 = bits(_pow2size_T_120, 1, 0) node _pow2size_T_122 = add(_pow2size_T_117, _pow2size_T_121) node _pow2size_T_123 = bits(_pow2size_T_122, 2, 0) node _pow2size_T_124 = add(_pow2size_T_115, _pow2size_T_123) node _pow2size_T_125 = bits(_pow2size_T_124, 3, 0) node _pow2size_T_126 = add(_pow2size_T_109, _pow2size_T_125) node _pow2size_T_127 = bits(_pow2size_T_126, 4, 0) node _pow2size_T_128 = add(_pow2size_T_95, _pow2size_T_127) node _pow2size_T_129 = bits(_pow2size_T_128, 5, 0) node _pow2size_T_130 = add(_pow2size_T_33, _pow2size_T_34) node _pow2size_T_131 = bits(_pow2size_T_130, 1, 0) node _pow2size_T_132 = add(_pow2size_T_35, _pow2size_T_36) node _pow2size_T_133 = bits(_pow2size_T_132, 1, 0) node _pow2size_T_134 = add(_pow2size_T_131, _pow2size_T_133) node _pow2size_T_135 = bits(_pow2size_T_134, 2, 0) node _pow2size_T_136 = add(_pow2size_T_37, _pow2size_T_38) node _pow2size_T_137 = bits(_pow2size_T_136, 1, 0) node _pow2size_T_138 = add(_pow2size_T_39, _pow2size_T_40) node _pow2size_T_139 = bits(_pow2size_T_138, 1, 0) node _pow2size_T_140 = add(_pow2size_T_137, _pow2size_T_139) node _pow2size_T_141 = bits(_pow2size_T_140, 2, 0) node _pow2size_T_142 = add(_pow2size_T_135, _pow2size_T_141) node _pow2size_T_143 = bits(_pow2size_T_142, 3, 0) node _pow2size_T_144 = add(_pow2size_T_41, _pow2size_T_42) node _pow2size_T_145 = bits(_pow2size_T_144, 1, 0) node _pow2size_T_146 = add(_pow2size_T_43, _pow2size_T_44) node _pow2size_T_147 = bits(_pow2size_T_146, 1, 0) node _pow2size_T_148 = add(_pow2size_T_145, _pow2size_T_147) node _pow2size_T_149 = bits(_pow2size_T_148, 2, 0) node _pow2size_T_150 = add(_pow2size_T_45, _pow2size_T_46) node _pow2size_T_151 = bits(_pow2size_T_150, 1, 0) node _pow2size_T_152 = add(_pow2size_T_47, _pow2size_T_48) node _pow2size_T_153 = bits(_pow2size_T_152, 1, 0) node _pow2size_T_154 = add(_pow2size_T_151, _pow2size_T_153) node _pow2size_T_155 = bits(_pow2size_T_154, 2, 0) node _pow2size_T_156 = add(_pow2size_T_149, _pow2size_T_155) node _pow2size_T_157 = bits(_pow2size_T_156, 3, 0) node _pow2size_T_158 = add(_pow2size_T_143, _pow2size_T_157) node _pow2size_T_159 = bits(_pow2size_T_158, 4, 0) node _pow2size_T_160 = add(_pow2size_T_49, _pow2size_T_50) node _pow2size_T_161 = bits(_pow2size_T_160, 1, 0) node _pow2size_T_162 = add(_pow2size_T_51, _pow2size_T_52) node _pow2size_T_163 = bits(_pow2size_T_162, 1, 0) node _pow2size_T_164 = add(_pow2size_T_161, _pow2size_T_163) node _pow2size_T_165 = bits(_pow2size_T_164, 2, 0) node _pow2size_T_166 = add(_pow2size_T_53, _pow2size_T_54) node _pow2size_T_167 = bits(_pow2size_T_166, 1, 0) node _pow2size_T_168 = add(_pow2size_T_55, _pow2size_T_56) node _pow2size_T_169 = bits(_pow2size_T_168, 1, 0) node _pow2size_T_170 = add(_pow2size_T_167, _pow2size_T_169) node _pow2size_T_171 = bits(_pow2size_T_170, 2, 0) node _pow2size_T_172 = add(_pow2size_T_165, _pow2size_T_171) node _pow2size_T_173 = bits(_pow2size_T_172, 3, 0) node _pow2size_T_174 = add(_pow2size_T_57, _pow2size_T_58) node _pow2size_T_175 = bits(_pow2size_T_174, 1, 0) node _pow2size_T_176 = add(_pow2size_T_59, _pow2size_T_60) node _pow2size_T_177 = bits(_pow2size_T_176, 1, 0) node _pow2size_T_178 = add(_pow2size_T_175, _pow2size_T_177) node _pow2size_T_179 = bits(_pow2size_T_178, 2, 0) node _pow2size_T_180 = add(_pow2size_T_61, _pow2size_T_62) node _pow2size_T_181 = bits(_pow2size_T_180, 1, 0) node _pow2size_T_182 = add(_pow2size_T_64, _pow2size_T_65) node _pow2size_T_183 = bits(_pow2size_T_182, 1, 0) node _pow2size_T_184 = add(_pow2size_T_63, _pow2size_T_183) node _pow2size_T_185 = bits(_pow2size_T_184, 1, 0) node _pow2size_T_186 = add(_pow2size_T_181, _pow2size_T_185) node _pow2size_T_187 = bits(_pow2size_T_186, 2, 0) node _pow2size_T_188 = add(_pow2size_T_179, _pow2size_T_187) node _pow2size_T_189 = bits(_pow2size_T_188, 3, 0) node _pow2size_T_190 = add(_pow2size_T_173, _pow2size_T_189) node _pow2size_T_191 = bits(_pow2size_T_190, 4, 0) node _pow2size_T_192 = add(_pow2size_T_159, _pow2size_T_191) node _pow2size_T_193 = bits(_pow2size_T_192, 5, 0) node _pow2size_T_194 = add(_pow2size_T_129, _pow2size_T_193) node _pow2size_T_195 = bits(_pow2size_T_194, 6, 0) node pow2size = eq(_pow2size_T_195, UInt<1>(0h1)) node _byteAddr_T = bits(addr, 2, 0) node byteAddr = mux(pow2size, _byteAddr_T, UInt<1>(0h0)) node _put_acquire_T = dshl(beatAddr, UInt<2>(0h3)) node _put_acquire_T_1 = cat(body[1], body[0]) node _put_acquire_legal_T = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_1 = leq(UInt<2>(0h3), UInt<4>(0hc)) node _put_acquire_legal_T_2 = and(_put_acquire_legal_T, _put_acquire_legal_T_1) node _put_acquire_legal_T_3 = or(UInt<1>(0h0), _put_acquire_legal_T_2) node _put_acquire_legal_T_4 = xor(_put_acquire_T, UInt<14>(0h3000)) node _put_acquire_legal_T_5 = cvt(_put_acquire_legal_T_4) node _put_acquire_legal_T_6 = and(_put_acquire_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _put_acquire_legal_T_7 = asSInt(_put_acquire_legal_T_6) node _put_acquire_legal_T_8 = eq(_put_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_9 = and(_put_acquire_legal_T_3, _put_acquire_legal_T_8) node _put_acquire_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_11 = leq(UInt<2>(0h3), UInt<3>(0h6)) node _put_acquire_legal_T_12 = and(_put_acquire_legal_T_10, _put_acquire_legal_T_11) node _put_acquire_legal_T_13 = or(UInt<1>(0h0), _put_acquire_legal_T_12) node _put_acquire_legal_T_14 = xor(_put_acquire_T, UInt<1>(0h0)) node _put_acquire_legal_T_15 = cvt(_put_acquire_legal_T_14) node _put_acquire_legal_T_16 = and(_put_acquire_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _put_acquire_legal_T_17 = asSInt(_put_acquire_legal_T_16) node _put_acquire_legal_T_18 = eq(_put_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_19 = xor(_put_acquire_T, UInt<21>(0h100000)) node _put_acquire_legal_T_20 = cvt(_put_acquire_legal_T_19) node _put_acquire_legal_T_21 = and(_put_acquire_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _put_acquire_legal_T_22 = asSInt(_put_acquire_legal_T_21) node _put_acquire_legal_T_23 = eq(_put_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_24 = xor(_put_acquire_T, UInt<26>(0h2000000)) node _put_acquire_legal_T_25 = cvt(_put_acquire_legal_T_24) node _put_acquire_legal_T_26 = and(_put_acquire_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _put_acquire_legal_T_27 = asSInt(_put_acquire_legal_T_26) node _put_acquire_legal_T_28 = eq(_put_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_29 = xor(_put_acquire_T, UInt<26>(0h2010000)) node _put_acquire_legal_T_30 = cvt(_put_acquire_legal_T_29) node _put_acquire_legal_T_31 = and(_put_acquire_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _put_acquire_legal_T_32 = asSInt(_put_acquire_legal_T_31) node _put_acquire_legal_T_33 = eq(_put_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_34 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_35 = cvt(_put_acquire_legal_T_34) node _put_acquire_legal_T_36 = and(_put_acquire_legal_T_35, asSInt(UInt<33>(0h98000000))) node _put_acquire_legal_T_37 = asSInt(_put_acquire_legal_T_36) node _put_acquire_legal_T_38 = eq(_put_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_39 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_40 = cvt(_put_acquire_legal_T_39) node _put_acquire_legal_T_41 = and(_put_acquire_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _put_acquire_legal_T_42 = asSInt(_put_acquire_legal_T_41) node _put_acquire_legal_T_43 = eq(_put_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_44 = xor(_put_acquire_T, UInt<29>(0h10000000)) node _put_acquire_legal_T_45 = cvt(_put_acquire_legal_T_44) node _put_acquire_legal_T_46 = and(_put_acquire_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _put_acquire_legal_T_47 = asSInt(_put_acquire_legal_T_46) node _put_acquire_legal_T_48 = eq(_put_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_49 = xor(_put_acquire_T, UInt<32>(0h80000000)) node _put_acquire_legal_T_50 = cvt(_put_acquire_legal_T_49) node _put_acquire_legal_T_51 = and(_put_acquire_legal_T_50, asSInt(UInt<33>(0h90000000))) node _put_acquire_legal_T_52 = asSInt(_put_acquire_legal_T_51) node _put_acquire_legal_T_53 = eq(_put_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_54 = or(_put_acquire_legal_T_18, _put_acquire_legal_T_23) node _put_acquire_legal_T_55 = or(_put_acquire_legal_T_54, _put_acquire_legal_T_28) node _put_acquire_legal_T_56 = or(_put_acquire_legal_T_55, _put_acquire_legal_T_33) node _put_acquire_legal_T_57 = or(_put_acquire_legal_T_56, _put_acquire_legal_T_38) node _put_acquire_legal_T_58 = or(_put_acquire_legal_T_57, _put_acquire_legal_T_43) node _put_acquire_legal_T_59 = or(_put_acquire_legal_T_58, _put_acquire_legal_T_48) node _put_acquire_legal_T_60 = or(_put_acquire_legal_T_59, _put_acquire_legal_T_53) node _put_acquire_legal_T_61 = and(_put_acquire_legal_T_13, _put_acquire_legal_T_60) node _put_acquire_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_acquire_legal_T_63 = xor(_put_acquire_T, UInt<17>(0h10000)) node _put_acquire_legal_T_64 = cvt(_put_acquire_legal_T_63) node _put_acquire_legal_T_65 = and(_put_acquire_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _put_acquire_legal_T_66 = asSInt(_put_acquire_legal_T_65) node _put_acquire_legal_T_67 = eq(_put_acquire_legal_T_66, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_68 = and(_put_acquire_legal_T_62, _put_acquire_legal_T_67) node _put_acquire_legal_T_69 = or(UInt<1>(0h0), _put_acquire_legal_T_9) node _put_acquire_legal_T_70 = or(_put_acquire_legal_T_69, _put_acquire_legal_T_61) node put_acquire_legal = or(_put_acquire_legal_T_70, _put_acquire_legal_T_68) wire put_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect put_acquire.opcode, UInt<1>(0h1) connect put_acquire.param, UInt<1>(0h0) connect put_acquire.size, UInt<2>(0h3) connect put_acquire.source, UInt<1>(0h0) connect put_acquire.address, _put_acquire_T connect put_acquire.mask, wmask connect put_acquire.data, _put_acquire_T_1 connect put_acquire.corrupt, UInt<1>(0h0) node _get_acquire_T = cat(beatAddr, byteAddr) node _get_acquire_legal_T = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_1 = leq(rsize, UInt<4>(0hc)) node _get_acquire_legal_T_2 = and(_get_acquire_legal_T, _get_acquire_legal_T_1) node _get_acquire_legal_T_3 = or(UInt<1>(0h0), _get_acquire_legal_T_2) node _get_acquire_legal_T_4 = xor(_get_acquire_T, UInt<14>(0h3000)) node _get_acquire_legal_T_5 = cvt(_get_acquire_legal_T_4) node _get_acquire_legal_T_6 = and(_get_acquire_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _get_acquire_legal_T_7 = asSInt(_get_acquire_legal_T_6) node _get_acquire_legal_T_8 = eq(_get_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_9 = and(_get_acquire_legal_T_3, _get_acquire_legal_T_8) node _get_acquire_legal_T_10 = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_11 = leq(rsize, UInt<3>(0h6)) node _get_acquire_legal_T_12 = and(_get_acquire_legal_T_10, _get_acquire_legal_T_11) node _get_acquire_legal_T_13 = or(UInt<1>(0h0), _get_acquire_legal_T_12) node _get_acquire_legal_T_14 = xor(_get_acquire_T, UInt<1>(0h0)) node _get_acquire_legal_T_15 = cvt(_get_acquire_legal_T_14) node _get_acquire_legal_T_16 = and(_get_acquire_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _get_acquire_legal_T_17 = asSInt(_get_acquire_legal_T_16) node _get_acquire_legal_T_18 = eq(_get_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_19 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_20 = cvt(_get_acquire_legal_T_19) node _get_acquire_legal_T_21 = and(_get_acquire_legal_T_20, asSInt(UInt<33>(0h98013000))) node _get_acquire_legal_T_22 = asSInt(_get_acquire_legal_T_21) node _get_acquire_legal_T_23 = eq(_get_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_24 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_25 = cvt(_get_acquire_legal_T_24) node _get_acquire_legal_T_26 = and(_get_acquire_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _get_acquire_legal_T_27 = asSInt(_get_acquire_legal_T_26) node _get_acquire_legal_T_28 = eq(_get_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_29 = xor(_get_acquire_T, UInt<26>(0h2000000)) node _get_acquire_legal_T_30 = cvt(_get_acquire_legal_T_29) node _get_acquire_legal_T_31 = and(_get_acquire_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _get_acquire_legal_T_32 = asSInt(_get_acquire_legal_T_31) node _get_acquire_legal_T_33 = eq(_get_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_34 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_35 = cvt(_get_acquire_legal_T_34) node _get_acquire_legal_T_36 = and(_get_acquire_legal_T_35, asSInt(UInt<33>(0h98000000))) node _get_acquire_legal_T_37 = asSInt(_get_acquire_legal_T_36) node _get_acquire_legal_T_38 = eq(_get_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_39 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_40 = cvt(_get_acquire_legal_T_39) node _get_acquire_legal_T_41 = and(_get_acquire_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _get_acquire_legal_T_42 = asSInt(_get_acquire_legal_T_41) node _get_acquire_legal_T_43 = eq(_get_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_44 = xor(_get_acquire_T, UInt<29>(0h10000000)) node _get_acquire_legal_T_45 = cvt(_get_acquire_legal_T_44) node _get_acquire_legal_T_46 = and(_get_acquire_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _get_acquire_legal_T_47 = asSInt(_get_acquire_legal_T_46) node _get_acquire_legal_T_48 = eq(_get_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_49 = xor(_get_acquire_T, UInt<32>(0h80000000)) node _get_acquire_legal_T_50 = cvt(_get_acquire_legal_T_49) node _get_acquire_legal_T_51 = and(_get_acquire_legal_T_50, asSInt(UInt<33>(0h90000000))) node _get_acquire_legal_T_52 = asSInt(_get_acquire_legal_T_51) node _get_acquire_legal_T_53 = eq(_get_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_54 = or(_get_acquire_legal_T_18, _get_acquire_legal_T_23) node _get_acquire_legal_T_55 = or(_get_acquire_legal_T_54, _get_acquire_legal_T_28) node _get_acquire_legal_T_56 = or(_get_acquire_legal_T_55, _get_acquire_legal_T_33) node _get_acquire_legal_T_57 = or(_get_acquire_legal_T_56, _get_acquire_legal_T_38) node _get_acquire_legal_T_58 = or(_get_acquire_legal_T_57, _get_acquire_legal_T_43) node _get_acquire_legal_T_59 = or(_get_acquire_legal_T_58, _get_acquire_legal_T_48) node _get_acquire_legal_T_60 = or(_get_acquire_legal_T_59, _get_acquire_legal_T_53) node _get_acquire_legal_T_61 = and(_get_acquire_legal_T_13, _get_acquire_legal_T_60) node _get_acquire_legal_T_62 = or(UInt<1>(0h0), _get_acquire_legal_T_9) node get_acquire_legal = or(_get_acquire_legal_T_62, _get_acquire_legal_T_61) wire get_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect get_acquire.opcode, UInt<3>(0h4) connect get_acquire.param, UInt<1>(0h0) connect get_acquire.size, rsize connect get_acquire.source, UInt<1>(0h0) connect get_acquire.address, _get_acquire_T node _get_acquire_a_mask_sizeOH_T = or(rsize, UInt<3>(0h0)) node get_acquire_a_mask_sizeOH_shiftAmount = bits(_get_acquire_a_mask_sizeOH_T, 1, 0) node _get_acquire_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_acquire_a_mask_sizeOH_shiftAmount) node _get_acquire_a_mask_sizeOH_T_2 = bits(_get_acquire_a_mask_sizeOH_T_1, 2, 0) node get_acquire_a_mask_sizeOH = or(_get_acquire_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_acquire_a_mask_sub_sub_sub_0_1 = geq(rsize, UInt<2>(0h3)) node get_acquire_a_mask_sub_sub_size = bits(get_acquire_a_mask_sizeOH, 2, 2) node get_acquire_a_mask_sub_sub_bit = bits(_get_acquire_T, 2, 2) node get_acquire_a_mask_sub_sub_nbit = eq(get_acquire_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_nbit) node _get_acquire_a_mask_sub_sub_acc_T = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_0_2) node get_acquire_a_mask_sub_sub_0_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T) node get_acquire_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_bit) node _get_acquire_a_mask_sub_sub_acc_T_1 = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_1_2) node get_acquire_a_mask_sub_sub_1_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T_1) node get_acquire_a_mask_sub_size = bits(get_acquire_a_mask_sizeOH, 1, 1) node get_acquire_a_mask_sub_bit = bits(_get_acquire_T, 1, 1) node get_acquire_a_mask_sub_nbit = eq(get_acquire_a_mask_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_0_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_0_2) node get_acquire_a_mask_sub_0_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T) node get_acquire_a_mask_sub_1_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_1 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_1_2) node get_acquire_a_mask_sub_1_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T_1) node get_acquire_a_mask_sub_2_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T_2 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_2_2) node get_acquire_a_mask_sub_2_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_2) node get_acquire_a_mask_sub_3_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_3 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_3_2) node get_acquire_a_mask_sub_3_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_3) node get_acquire_a_mask_size = bits(get_acquire_a_mask_sizeOH, 0, 0) node get_acquire_a_mask_bit = bits(_get_acquire_T, 0, 0) node get_acquire_a_mask_nbit = eq(get_acquire_a_mask_bit, UInt<1>(0h0)) node get_acquire_a_mask_eq = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T = and(get_acquire_a_mask_size, get_acquire_a_mask_eq) node get_acquire_a_mask_acc = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T) node get_acquire_a_mask_eq_1 = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_1 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_1) node get_acquire_a_mask_acc_1 = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T_1) node get_acquire_a_mask_eq_2 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_2 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_2) node get_acquire_a_mask_acc_2 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_2) node get_acquire_a_mask_eq_3 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_3 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_3) node get_acquire_a_mask_acc_3 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_3) node get_acquire_a_mask_eq_4 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_4 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_4) node get_acquire_a_mask_acc_4 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_4) node get_acquire_a_mask_eq_5 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_5 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_5) node get_acquire_a_mask_acc_5 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_5) node get_acquire_a_mask_eq_6 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_6 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_6) node get_acquire_a_mask_acc_6 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_6) node get_acquire_a_mask_eq_7 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_7 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_7) node get_acquire_a_mask_acc_7 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_7) node get_acquire_a_mask_lo_lo = cat(get_acquire_a_mask_acc_1, get_acquire_a_mask_acc) node get_acquire_a_mask_lo_hi = cat(get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2) node get_acquire_a_mask_lo = cat(get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo) node get_acquire_a_mask_hi_lo = cat(get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4) node get_acquire_a_mask_hi_hi = cat(get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6) node get_acquire_a_mask_hi = cat(get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo) node _get_acquire_a_mask_T = cat(get_acquire_a_mask_hi, get_acquire_a_mask_lo) connect get_acquire.mask, _get_acquire_a_mask_T invalidate get_acquire.data connect get_acquire.corrupt, UInt<1>(0h0) node _nodeOut_a_valid_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_valid_T_1 = eq(state, UInt<4>(0h3)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_bits_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_bits_T_1 = mux(_nodeOut_a_bits_T, put_acquire, get_acquire) connect nodeOut.a.bits, _nodeOut_a_bits_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) node _nodeOut_d_ready_T = eq(state, UInt<4>(0h8)) node _nodeOut_d_ready_T_1 = eq(state, UInt<4>(0h4)) node _nodeOut_d_ready_T_2 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_T_1) connect nodeOut.d.ready, _nodeOut_d_ready_T_2 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T = eq(state, UInt<4>(0h0)) node _T_1 = and(_T, io.tsi.in.valid) when _T_1 : connect cmd, io.tsi.in.bits connect idx, UInt<1>(0h0) connect addr, UInt<1>(0h0) connect len, UInt<1>(0h0) connect state, UInt<4>(0h1) node _T_2 = eq(state, UInt<4>(0h1)) node _T_3 = and(_T_2, io.tsi.in.valid) when _T_3 : node _addr_T = bits(idx, 0, 0) node _addr_T_1 = cat(_addr_T, UInt<5>(0h0)) node _addr_T_2 = dshl(io.tsi.in.bits, _addr_T_1) node _addr_T_3 = or(addr, _addr_T_2) connect addr, _addr_T_3 node _idx_T = add(idx, UInt<1>(0h1)) node _idx_T_1 = tail(_idx_T, 1) connect idx, _idx_T_1 node _T_4 = eq(idx, UInt<1>(0h1)) when _T_4 : connect idx, UInt<1>(0h0) connect state, UInt<4>(0h2) node _T_5 = eq(state, UInt<4>(0h2)) node _T_6 = and(_T_5, io.tsi.in.valid) when _T_6 : node _len_T = bits(idx, 0, 0) node _len_T_1 = cat(_len_T, UInt<5>(0h0)) node _len_T_2 = dshl(io.tsi.in.bits, _len_T_1) node _len_T_3 = or(len, _len_T_2) connect len, _len_T_3 node _idx_T_2 = add(idx, UInt<1>(0h1)) node _idx_T_3 = tail(_idx_T_2, 1) connect idx, _idx_T_3 node _T_7 = eq(idx, UInt<1>(0h1)) when _T_7 : node _idx_T_4 = bits(addr, 2, 2) connect idx, _idx_T_4 node _T_8 = eq(cmd, UInt<1>(0h1)) when _T_8 : connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) else : node _T_9 = eq(cmd, UInt<1>(0h0)) when _T_9 : connect state, UInt<4>(0h3) else : node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Bad TSI command\n at TSIToTileLink.scala:137 assert(false.B, \"Bad TSI command\")\n") : printf assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert node _T_13 = eq(state, UInt<4>(0h3)) node _T_14 = and(_T_13, nodeOut.a.ready) when _T_14 : connect state, UInt<4>(0h4) node _T_15 = eq(state, UInt<4>(0h4)) node _T_16 = and(_T_15, nodeOut.d.valid) when _T_16 : wire _WIRE_6 : UInt<32>[2] wire _WIRE_7 : UInt<64> connect _WIRE_7, nodeOut.d.bits.data node _T_17 = bits(_WIRE_7, 31, 0) connect _WIRE_6[0], _T_17 node _T_18 = bits(_WIRE_7, 63, 32) connect _WIRE_6[1], _T_18 connect body, _WIRE_6 node _idx_T_5 = bits(addr, 2, 2) connect idx, _idx_T_5 connect addr, nextAddr connect state, UInt<4>(0h5) node _T_19 = eq(state, UInt<4>(0h5)) node _T_20 = and(_T_19, io.tsi.out.ready) when _T_20 : node _idx_T_6 = add(idx, UInt<1>(0h1)) node _idx_T_7 = tail(_idx_T_6, 1) connect idx, _idx_T_7 node _len_T_4 = sub(len, UInt<1>(0h1)) node _len_T_5 = tail(_len_T_4, 1) connect len, _len_T_5 node _T_21 = eq(len, UInt<1>(0h0)) when _T_21 : connect state, UInt<4>(0h0) else : node _T_22 = eq(idx, UInt<1>(0h1)) when _T_22 : connect state, UInt<4>(0h3) node _T_23 = eq(state, UInt<4>(0h6)) node _T_24 = and(_T_23, io.tsi.in.valid) when _T_24 : connect body[idx], io.tsi.in.bits node _bodyValid_T = dshl(UInt<1>(0h1), idx) node _bodyValid_T_1 = or(bodyValid, _bodyValid_T) connect bodyValid, _bodyValid_T_1 node _T_25 = eq(idx, UInt<1>(0h1)) node _T_26 = eq(len, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) when _T_27 : connect state, UInt<4>(0h7) else : node _idx_T_8 = add(idx, UInt<1>(0h1)) node _idx_T_9 = tail(_idx_T_8, 1) connect idx, _idx_T_9 node _len_T_6 = sub(len, UInt<1>(0h1)) node _len_T_7 = tail(_len_T_6, 1) connect len, _len_T_7 node _T_28 = eq(state, UInt<4>(0h7)) node _T_29 = and(_T_28, nodeOut.a.ready) when _T_29 : connect state, UInt<4>(0h8) node _T_30 = eq(state, UInt<4>(0h8)) node _T_31 = and(_T_30, nodeOut.d.valid) when _T_31 : node _T_32 = eq(len, UInt<1>(0h0)) when _T_32 : connect state, UInt<4>(0h0) else : connect addr, nextAddr node _len_T_8 = sub(len, UInt<1>(0h1)) node _len_T_9 = tail(_len_T_8, 1) connect len, _len_T_9 connect idx, UInt<1>(0h0) connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) extmodule plusarg_reader_143 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_144 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TSIToTileLink( // @[TSIToTileLink.scala:36:7] input clock, // @[TSIToTileLink.scala:36:7] input reset, // @[TSIToTileLink.scala:36:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_tsi_in_ready, // @[TSIToTileLink.scala:37:14] input io_tsi_in_valid, // @[TSIToTileLink.scala:37:14] input [31:0] io_tsi_in_bits, // @[TSIToTileLink.scala:37:14] input io_tsi_out_ready, // @[TSIToTileLink.scala:37:14] output io_tsi_out_valid, // @[TSIToTileLink.scala:37:14] output [31:0] io_tsi_out_bits, // @[TSIToTileLink.scala:37:14] output [3:0] io_state // @[TSIToTileLink.scala:37:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[TSIToTileLink.scala:36:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_a_bits_param = 3'h0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] put_acquire_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] get_acquire_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] _nodeOut_a_bits_T_1_param = 3'h0; // @[TSIToTileLink.scala:95:20] wire auto_out_a_bits_source = 1'h0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_bits_corrupt = 1'h0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _put_acquire_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_acquire_source = 1'h0; // @[Edges.scala:500:17] wire put_acquire_corrupt = 1'h0; // @[Edges.scala:500:17] wire get_acquire_source = 1'h0; // @[Edges.scala:460:17] wire get_acquire_corrupt = 1'h0; // @[Edges.scala:460:17] wire _nodeOut_a_bits_T_1_source = 1'h0; // @[TSIToTileLink.scala:95:20] wire _nodeOut_a_bits_T_1_corrupt = 1'h0; // @[TSIToTileLink.scala:95:20] wire [63:0] get_acquire_data = 64'h0; // @[Edges.scala:460:17] wire [2:0] get_acquire_opcode = 3'h4; // @[Edges.scala:460:17] wire _put_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire [3:0] put_acquire_size = 4'h3; // @[Edges.scala:500:17] wire [2:0] put_acquire_opcode = 3'h1; // @[Edges.scala:500:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[TSIToTileLink.scala:36:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[TSIToTileLink.scala:36:7] wire _io_tsi_in_ready_T_6; // @[package.scala:81:59] wire _io_tsi_out_valid_T; // @[TSIToTileLink.scala:71:29] wire [2:0] auto_out_a_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_a_bits_size_0; // @[TSIToTileLink.scala:36:7] wire [31:0] auto_out_a_bits_address_0; // @[TSIToTileLink.scala:36:7] wire [7:0] auto_out_a_bits_mask_0; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_a_bits_data_0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_valid_0; // @[TSIToTileLink.scala:36:7] wire auto_out_d_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_valid_0; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_out_bits_0; // @[TSIToTileLink.scala:36:7] wire [3:0] io_state_0; // @[TSIToTileLink.scala:36:7] wire _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [3:0] _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[TSIToTileLink.scala:36:7] wire [31:0] _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[TSIToTileLink.scala:36:7] wire [7:0] _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[TSIToTileLink.scala:36:7] wire [63:0] _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[TSIToTileLink.scala:36:7] wire _nodeOut_d_ready_T_2; // @[package.scala:81:59] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[TSIToTileLink.scala:36:7] reg [31:0] cmd; // @[TSIToTileLink.scala:56:16] reg [63:0] addr; // @[TSIToTileLink.scala:57:17] reg [63:0] len; // @[TSIToTileLink.scala:58:16] reg [31:0] body_0; // @[TSIToTileLink.scala:59:17] reg [31:0] body_1; // @[TSIToTileLink.scala:59:17] reg [1:0] bodyValid; // @[TSIToTileLink.scala:60:22] reg idx; // @[TSIToTileLink.scala:61:16] wire _addr_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] wire _len_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] reg [3:0] state; // @[TSIToTileLink.scala:67:22] assign io_state_0 = state; // @[TSIToTileLink.scala:36:7, :67:22] wire _io_tsi_in_ready_T = state == 4'h0; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_1 = state == 4'h1; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_2 = state == 4'h2; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_3 = state == 4'h6; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_4 = _io_tsi_in_ready_T | _io_tsi_in_ready_T_1; // @[package.scala:16:47, :81:59] wire _io_tsi_in_ready_T_5 = _io_tsi_in_ready_T_4 | _io_tsi_in_ready_T_2; // @[package.scala:16:47, :81:59] assign _io_tsi_in_ready_T_6 = _io_tsi_in_ready_T_5 | _io_tsi_in_ready_T_3; // @[package.scala:16:47, :81:59] assign io_tsi_in_ready_0 = _io_tsi_in_ready_T_6; // @[TSIToTileLink.scala:36:7] assign _io_tsi_out_valid_T = state == 4'h5; // @[TSIToTileLink.scala:67:22, :71:29] assign io_tsi_out_valid_0 = _io_tsi_out_valid_T; // @[TSIToTileLink.scala:36:7, :71:29] assign io_tsi_out_bits_0 = idx ? body_1 : body_0; // @[TSIToTileLink.scala:36:7, :59:17, :61:16, :72:19] wire [28:0] beatAddr = addr[31:3]; // @[TSIToTileLink.scala:57:17, :74:22] wire [29:0] _nextAddr_T = {1'h0, beatAddr} + 30'h1; // @[TSIToTileLink.scala:74:22, :75:31] wire [28:0] _nextAddr_T_1 = _nextAddr_T[28:0]; // @[TSIToTileLink.scala:75:31] wire [31:0] nextAddr = {_nextAddr_T_1, 3'h0}; // @[TSIToTileLink.scala:75:{21,31}] wire _wmask_T = bodyValid[0]; // @[TSIToTileLink.scala:60:22, :77:30] wire _wmask_T_1 = bodyValid[1]; // @[TSIToTileLink.scala:60:22, :77:30] wire [3:0] _wmask_T_2 = {4{_wmask_T}}; // @[TSIToTileLink.scala:77:30] wire [3:0] _wmask_T_3 = {4{_wmask_T_1}}; // @[TSIToTileLink.scala:77:30] wire [7:0] wmask = {_wmask_T_3, _wmask_T_2}; // @[TSIToTileLink.scala:77:30] wire [7:0] put_acquire_mask = wmask; // @[TSIToTileLink.scala:77:30] wire [64:0] _addr_size_T = {33'h0, nextAddr} - {1'h0, addr}; // @[TSIToTileLink.scala:57:17, :75:21, :78:28] wire [63:0] addr_size = _addr_size_T[63:0]; // @[TSIToTileLink.scala:78:28] wire [64:0] _GEN = {1'h0, len}; // @[TSIToTileLink.scala:58:16, :79:26] wire [64:0] _len_size_T = _GEN + 65'h1; // @[TSIToTileLink.scala:79:26] wire [63:0] _len_size_T_1 = _len_size_T[63:0]; // @[TSIToTileLink.scala:79:26] wire [65:0] len_size = {_len_size_T_1, 2'h0}; // @[TSIToTileLink.scala:79:{21,26}] wire [65:0] _GEN_0 = {2'h0, addr_size}; // @[TSIToTileLink.scala:78:28, :80:31] wire _raw_size_T = len_size < _GEN_0; // @[TSIToTileLink.scala:79:21, :80:31] wire [65:0] raw_size = _raw_size_T ? len_size : _GEN_0; // @[TSIToTileLink.scala:79:21, :80:{21,31}] wire _rsize_T = raw_size == 66'h1; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_1 = _rsize_T ? 2'h0 : 2'h3; // @[TSIToTileLink.scala:81:50] wire _rsize_T_2 = raw_size == 66'h2; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_3 = _rsize_T_2 ? 2'h1 : _rsize_T_1; // @[TSIToTileLink.scala:81:50] wire _rsize_T_4 = raw_size == 66'h4; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] rsize = _rsize_T_4 ? 2'h2 : _rsize_T_3; // @[TSIToTileLink.scala:81:50] wire _pow2size_T = raw_size[0]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_1 = raw_size[1]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_2 = raw_size[2]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_3 = raw_size[3]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_4 = raw_size[4]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_5 = raw_size[5]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_6 = raw_size[6]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_7 = raw_size[7]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_8 = raw_size[8]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_9 = raw_size[9]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_10 = raw_size[10]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_11 = raw_size[11]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_12 = raw_size[12]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_13 = raw_size[13]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_14 = raw_size[14]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_15 = raw_size[15]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_16 = raw_size[16]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_17 = raw_size[17]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_18 = raw_size[18]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_19 = raw_size[19]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_20 = raw_size[20]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_21 = raw_size[21]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_22 = raw_size[22]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_23 = raw_size[23]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_24 = raw_size[24]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_25 = raw_size[25]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_26 = raw_size[26]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_27 = raw_size[27]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_28 = raw_size[28]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_29 = raw_size[29]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_30 = raw_size[30]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_31 = raw_size[31]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_32 = raw_size[32]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_33 = raw_size[33]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_34 = raw_size[34]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_35 = raw_size[35]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_36 = raw_size[36]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_37 = raw_size[37]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_38 = raw_size[38]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_39 = raw_size[39]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_40 = raw_size[40]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_41 = raw_size[41]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_42 = raw_size[42]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_43 = raw_size[43]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_44 = raw_size[44]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_45 = raw_size[45]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_46 = raw_size[46]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_47 = raw_size[47]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_48 = raw_size[48]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_49 = raw_size[49]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_50 = raw_size[50]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_51 = raw_size[51]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_52 = raw_size[52]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_53 = raw_size[53]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_54 = raw_size[54]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_55 = raw_size[55]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_56 = raw_size[56]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_57 = raw_size[57]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_58 = raw_size[58]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_59 = raw_size[59]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_60 = raw_size[60]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_61 = raw_size[61]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_62 = raw_size[62]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_63 = raw_size[63]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_64 = raw_size[64]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_65 = raw_size[65]; // @[TSIToTileLink.scala:80:21, :84:26] wire [1:0] _pow2size_T_66 = {1'h0, _pow2size_T} + {1'h0, _pow2size_T_1}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_67 = _pow2size_T_66; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_68 = {1'h0, _pow2size_T_2} + {1'h0, _pow2size_T_3}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_69 = _pow2size_T_68; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_70 = {1'h0, _pow2size_T_67} + {1'h0, _pow2size_T_69}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_71 = _pow2size_T_70; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_72 = {1'h0, _pow2size_T_4} + {1'h0, _pow2size_T_5}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_73 = _pow2size_T_72; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_74 = {1'h0, _pow2size_T_6} + {1'h0, _pow2size_T_7}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_75 = _pow2size_T_74; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_76 = {1'h0, _pow2size_T_73} + {1'h0, _pow2size_T_75}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_77 = _pow2size_T_76; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_78 = {1'h0, _pow2size_T_71} + {1'h0, _pow2size_T_77}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_79 = _pow2size_T_78; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_80 = {1'h0, _pow2size_T_8} + {1'h0, _pow2size_T_9}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_81 = _pow2size_T_80; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_82 = {1'h0, _pow2size_T_10} + {1'h0, _pow2size_T_11}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_83 = _pow2size_T_82; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_84 = {1'h0, _pow2size_T_81} + {1'h0, _pow2size_T_83}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_85 = _pow2size_T_84; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_86 = {1'h0, _pow2size_T_12} + {1'h0, _pow2size_T_13}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_87 = _pow2size_T_86; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_88 = {1'h0, _pow2size_T_14} + {1'h0, _pow2size_T_15}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_89 = _pow2size_T_88; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_90 = {1'h0, _pow2size_T_87} + {1'h0, _pow2size_T_89}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_91 = _pow2size_T_90; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_92 = {1'h0, _pow2size_T_85} + {1'h0, _pow2size_T_91}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_93 = _pow2size_T_92; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_94 = {1'h0, _pow2size_T_79} + {1'h0, _pow2size_T_93}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_95 = _pow2size_T_94; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_96 = {1'h0, _pow2size_T_16} + {1'h0, _pow2size_T_17}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_97 = _pow2size_T_96; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_98 = {1'h0, _pow2size_T_18} + {1'h0, _pow2size_T_19}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_99 = _pow2size_T_98; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_100 = {1'h0, _pow2size_T_97} + {1'h0, _pow2size_T_99}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_101 = _pow2size_T_100; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_102 = {1'h0, _pow2size_T_20} + {1'h0, _pow2size_T_21}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_103 = _pow2size_T_102; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_104 = {1'h0, _pow2size_T_22} + {1'h0, _pow2size_T_23}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_105 = _pow2size_T_104; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_106 = {1'h0, _pow2size_T_103} + {1'h0, _pow2size_T_105}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_107 = _pow2size_T_106; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_108 = {1'h0, _pow2size_T_101} + {1'h0, _pow2size_T_107}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_109 = _pow2size_T_108; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_110 = {1'h0, _pow2size_T_24} + {1'h0, _pow2size_T_25}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_111 = _pow2size_T_110; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_112 = {1'h0, _pow2size_T_26} + {1'h0, _pow2size_T_27}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_113 = _pow2size_T_112; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_114 = {1'h0, _pow2size_T_111} + {1'h0, _pow2size_T_113}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_115 = _pow2size_T_114; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_116 = {1'h0, _pow2size_T_28} + {1'h0, _pow2size_T_29}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_117 = _pow2size_T_116; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_118 = {1'h0, _pow2size_T_31} + {1'h0, _pow2size_T_32}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_119 = _pow2size_T_118; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_120 = {2'h0, _pow2size_T_30} + {1'h0, _pow2size_T_119}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_121 = _pow2size_T_120[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_122 = {1'h0, _pow2size_T_117} + {1'h0, _pow2size_T_121}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_123 = _pow2size_T_122; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_124 = {1'h0, _pow2size_T_115} + {1'h0, _pow2size_T_123}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_125 = _pow2size_T_124; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_126 = {1'h0, _pow2size_T_109} + {1'h0, _pow2size_T_125}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_127 = _pow2size_T_126; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_128 = {1'h0, _pow2size_T_95} + {1'h0, _pow2size_T_127}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_129 = _pow2size_T_128; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_130 = {1'h0, _pow2size_T_33} + {1'h0, _pow2size_T_34}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_131 = _pow2size_T_130; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_132 = {1'h0, _pow2size_T_35} + {1'h0, _pow2size_T_36}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_133 = _pow2size_T_132; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_134 = {1'h0, _pow2size_T_131} + {1'h0, _pow2size_T_133}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_135 = _pow2size_T_134; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_136 = {1'h0, _pow2size_T_37} + {1'h0, _pow2size_T_38}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_137 = _pow2size_T_136; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_138 = {1'h0, _pow2size_T_39} + {1'h0, _pow2size_T_40}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_139 = _pow2size_T_138; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_140 = {1'h0, _pow2size_T_137} + {1'h0, _pow2size_T_139}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_141 = _pow2size_T_140; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_142 = {1'h0, _pow2size_T_135} + {1'h0, _pow2size_T_141}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_143 = _pow2size_T_142; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_144 = {1'h0, _pow2size_T_41} + {1'h0, _pow2size_T_42}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_145 = _pow2size_T_144; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_146 = {1'h0, _pow2size_T_43} + {1'h0, _pow2size_T_44}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_147 = _pow2size_T_146; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_148 = {1'h0, _pow2size_T_145} + {1'h0, _pow2size_T_147}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_149 = _pow2size_T_148; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_150 = {1'h0, _pow2size_T_45} + {1'h0, _pow2size_T_46}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_151 = _pow2size_T_150; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_152 = {1'h0, _pow2size_T_47} + {1'h0, _pow2size_T_48}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_153 = _pow2size_T_152; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_154 = {1'h0, _pow2size_T_151} + {1'h0, _pow2size_T_153}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_155 = _pow2size_T_154; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_156 = {1'h0, _pow2size_T_149} + {1'h0, _pow2size_T_155}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_157 = _pow2size_T_156; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_158 = {1'h0, _pow2size_T_143} + {1'h0, _pow2size_T_157}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_159 = _pow2size_T_158; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_160 = {1'h0, _pow2size_T_49} + {1'h0, _pow2size_T_50}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_161 = _pow2size_T_160; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_162 = {1'h0, _pow2size_T_51} + {1'h0, _pow2size_T_52}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_163 = _pow2size_T_162; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_164 = {1'h0, _pow2size_T_161} + {1'h0, _pow2size_T_163}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_165 = _pow2size_T_164; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_166 = {1'h0, _pow2size_T_53} + {1'h0, _pow2size_T_54}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_167 = _pow2size_T_166; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_168 = {1'h0, _pow2size_T_55} + {1'h0, _pow2size_T_56}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_169 = _pow2size_T_168; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_170 = {1'h0, _pow2size_T_167} + {1'h0, _pow2size_T_169}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_171 = _pow2size_T_170; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_172 = {1'h0, _pow2size_T_165} + {1'h0, _pow2size_T_171}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_173 = _pow2size_T_172; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_174 = {1'h0, _pow2size_T_57} + {1'h0, _pow2size_T_58}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_175 = _pow2size_T_174; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_176 = {1'h0, _pow2size_T_59} + {1'h0, _pow2size_T_60}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_177 = _pow2size_T_176; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_178 = {1'h0, _pow2size_T_175} + {1'h0, _pow2size_T_177}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_179 = _pow2size_T_178; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_180 = {1'h0, _pow2size_T_61} + {1'h0, _pow2size_T_62}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_181 = _pow2size_T_180; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_182 = {1'h0, _pow2size_T_64} + {1'h0, _pow2size_T_65}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_183 = _pow2size_T_182; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_184 = {2'h0, _pow2size_T_63} + {1'h0, _pow2size_T_183}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_185 = _pow2size_T_184[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_186 = {1'h0, _pow2size_T_181} + {1'h0, _pow2size_T_185}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_187 = _pow2size_T_186; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_188 = {1'h0, _pow2size_T_179} + {1'h0, _pow2size_T_187}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_189 = _pow2size_T_188; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_190 = {1'h0, _pow2size_T_173} + {1'h0, _pow2size_T_189}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_191 = _pow2size_T_190; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_192 = {1'h0, _pow2size_T_159} + {1'h0, _pow2size_T_191}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_193 = _pow2size_T_192; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_194 = {1'h0, _pow2size_T_129} + {1'h0, _pow2size_T_193}; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_195 = _pow2size_T_194; // @[TSIToTileLink.scala:84:26] wire pow2size = _pow2size_T_195 == 7'h1; // @[TSIToTileLink.scala:84:{26,37}] wire [2:0] _byteAddr_T = addr[2:0]; // @[TSIToTileLink.scala:57:17, :85:36] wire [2:0] byteAddr = pow2size ? _byteAddr_T : 3'h0; // @[TSIToTileLink.scala:84:37, :85:{21,36}] wire [31:0] _put_acquire_T = {beatAddr, 3'h0}; // @[TSIToTileLink.scala:74:22, :88:19] wire [31:0] _put_acquire_legal_T_14 = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [31:0] put_acquire_address = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [63:0] _put_acquire_T_1 = {body_1, body_0}; // @[TSIToTileLink.scala:59:17, :89:10] wire [63:0] put_acquire_data = _put_acquire_T_1; // @[TSIToTileLink.scala:89:10] wire [31:0] _put_acquire_legal_T_4 = {_put_acquire_T[31:14], _put_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_5 = {1'h0, _put_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_6 = _put_acquire_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_7 = _put_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_8 = _put_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_9 = _put_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_69 = _put_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _put_acquire_legal_T_15 = {1'h0, _put_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_16 = _put_acquire_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_17 = _put_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_18 = _put_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_19 = {_put_acquire_T[31:21], _put_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_20 = {1'h0, _put_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_21 = _put_acquire_legal_T_20 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_22 = _put_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_23 = _put_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_24 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_25 = {1'h0, _put_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_26 = _put_acquire_legal_T_25 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_27 = _put_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_28 = _put_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_29 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_30 = {1'h0, _put_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_31 = _put_acquire_legal_T_30 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_32 = _put_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_33 = _put_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:88:19] wire [31:0] _put_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_34 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _put_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_39 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _put_acquire_legal_T_35 = {1'h0, _put_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_36 = _put_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_37 = _put_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_38 = _put_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _put_acquire_legal_T_40 = {1'h0, _put_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_41 = _put_acquire_legal_T_40 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_42 = _put_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_43 = _put_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_44 = {_put_acquire_T[31:29], _put_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_45 = {1'h0, _put_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_46 = _put_acquire_legal_T_45 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_47 = _put_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_48 = _put_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_49 = _put_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_50 = {1'h0, _put_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_51 = _put_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_52 = _put_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_53 = _put_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_54 = _put_acquire_legal_T_18 | _put_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_55 = _put_acquire_legal_T_54 | _put_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_56 = _put_acquire_legal_T_55 | _put_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_57 = _put_acquire_legal_T_56 | _put_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_58 = _put_acquire_legal_T_57 | _put_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_59 = _put_acquire_legal_T_58 | _put_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_60 = _put_acquire_legal_T_59 | _put_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_61 = _put_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [31:0] _put_acquire_legal_T_63 = {_put_acquire_T[31:17], _put_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_64 = {1'h0, _put_acquire_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_65 = _put_acquire_legal_T_64 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_66 = _put_acquire_legal_T_65; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_67 = _put_acquire_legal_T_66 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_70 = _put_acquire_legal_T_69 | _put_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_acquire_legal = _put_acquire_legal_T_70; // @[Parameters.scala:686:26] wire [31:0] _get_acquire_T = {beatAddr, byteAddr}; // @[TSIToTileLink.scala:74:22, :85:21, :92:13] wire [31:0] _get_acquire_legal_T_14 = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] get_acquire_address = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_4 = {_get_acquire_T[31:14], _get_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_5 = {1'h0, _get_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_6 = _get_acquire_legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_7 = _get_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_8 = _get_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_9 = _get_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_62 = _get_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _get_acquire_legal_T_15 = {1'h0, _get_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_16 = _get_acquire_legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_17 = _get_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_18 = _get_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {_get_acquire_T[31:17], _get_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_19; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_24; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_20 = {1'h0, _get_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_21 = _get_acquire_legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_22 = _get_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_23 = _get_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_25 = {1'h0, _get_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_26 = _get_acquire_legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_27 = _get_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_28 = _get_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_29 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_30 = {1'h0, _get_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_31 = _get_acquire_legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_32 = _get_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_33 = _get_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_35 = {1'h0, _get_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_36 = _get_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_37 = _get_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_38 = _get_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_40 = {1'h0, _get_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_41 = _get_acquire_legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_42 = _get_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_43 = _get_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_44 = {_get_acquire_T[31:29], _get_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_45 = {1'h0, _get_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_46 = _get_acquire_legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_47 = _get_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_48 = _get_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_49 = _get_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_50 = {1'h0, _get_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_51 = _get_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_52 = _get_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_53 = _get_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_54 = _get_acquire_legal_T_18 | _get_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_55 = _get_acquire_legal_T_54 | _get_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_56 = _get_acquire_legal_T_55 | _get_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_57 = _get_acquire_legal_T_56 | _get_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_58 = _get_acquire_legal_T_57 | _get_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_59 = _get_acquire_legal_T_58 | _get_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_60 = _get_acquire_legal_T_59 | _get_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_61 = _get_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_acquire_legal = _get_acquire_legal_T_62 | _get_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_acquire_size; // @[Edges.scala:460:17] wire [7:0] get_acquire_mask; // @[Edges.scala:460:17] assign get_acquire_size = {2'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [2:0] _get_acquire_a_mask_sizeOH_T = {1'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [1:0] get_acquire_a_mask_sizeOH_shiftAmount = _get_acquire_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_acquire_a_mask_sizeOH_T_1 = 4'h1 << get_acquire_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_acquire_a_mask_sizeOH_T_2 = _get_acquire_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_acquire_a_mask_sizeOH = {_get_acquire_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_acquire_a_mask_sub_sub_sub_0_1 = &rsize; // @[TSIToTileLink.scala:81:50] wire get_acquire_a_mask_sub_sub_size = get_acquire_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_sub_bit = _get_acquire_T[2]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_sub_1_2 = get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_acquire_a_mask_sub_sub_nbit = ~get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_sub_0_2 = get_acquire_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_sub_acc_T = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_0_1 = get_acquire_a_mask_sub_sub_sub_0_1 | _get_acquire_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_acquire_a_mask_sub_sub_acc_T_1 = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_1_1 = get_acquire_a_mask_sub_sub_sub_0_1 | _get_acquire_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_acquire_a_mask_sub_size = get_acquire_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_bit = _get_acquire_T[1]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_nbit = ~get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_0_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_0_1 = get_acquire_a_mask_sub_sub_0_1 | _get_acquire_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_1_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_1 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_1_1 = get_acquire_a_mask_sub_sub_0_1 | _get_acquire_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_2_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T_2 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_2_1 = get_acquire_a_mask_sub_sub_1_1 | _get_acquire_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_3_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_3 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_3_1 = get_acquire_a_mask_sub_sub_1_1 | _get_acquire_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_size = get_acquire_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_bit = _get_acquire_T[0]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_nbit = ~get_acquire_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_eq = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T = get_acquire_a_mask_size & get_acquire_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc = get_acquire_a_mask_sub_0_1 | _get_acquire_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_1 = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_1 = get_acquire_a_mask_size & get_acquire_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_1 = get_acquire_a_mask_sub_0_1 | _get_acquire_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_2 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_2 = get_acquire_a_mask_size & get_acquire_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_2 = get_acquire_a_mask_sub_1_1 | _get_acquire_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_3 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_3 = get_acquire_a_mask_size & get_acquire_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_3 = get_acquire_a_mask_sub_1_1 | _get_acquire_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_4 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_4 = get_acquire_a_mask_size & get_acquire_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_4 = get_acquire_a_mask_sub_2_1 | _get_acquire_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_5 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_5 = get_acquire_a_mask_size & get_acquire_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_5 = get_acquire_a_mask_sub_2_1 | _get_acquire_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_6 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_6 = get_acquire_a_mask_size & get_acquire_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_6 = get_acquire_a_mask_sub_3_1 | _get_acquire_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_7 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_7 = get_acquire_a_mask_size & get_acquire_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_7 = get_acquire_a_mask_sub_3_1 | _get_acquire_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_acquire_a_mask_lo_lo = {get_acquire_a_mask_acc_1, get_acquire_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_lo_hi = {get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_lo = {get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_acquire_a_mask_hi_lo = {get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_hi_hi = {get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_hi = {get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_acquire_a_mask_T = {get_acquire_a_mask_hi, get_acquire_a_mask_lo}; // @[Misc.scala:222:10] assign get_acquire_mask = _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire _T_28 = state == 4'h7; // @[TSIToTileLink.scala:67:22] wire _nodeOut_a_valid_T; // @[package.scala:16:47] assign _nodeOut_a_valid_T = _T_28; // @[package.scala:16:47] wire _nodeOut_a_bits_T; // @[TSIToTileLink.scala:95:27] assign _nodeOut_a_bits_T = _T_28; // @[TSIToTileLink.scala:95:27] wire _nodeOut_a_valid_T_1 = state == 4'h3; // @[TSIToTileLink.scala:67:22] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign _nodeOut_a_bits_T_1_opcode = _nodeOut_a_bits_T ? 3'h1 : 3'h4; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_size = _nodeOut_a_bits_T ? 4'h3 : get_acquire_size; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_address = _nodeOut_a_bits_T ? put_acquire_address : get_acquire_address; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_mask = _nodeOut_a_bits_T ? put_acquire_mask : get_acquire_mask; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_data = _nodeOut_a_bits_T ? put_acquire_data : 64'h0; // @[TSIToTileLink.scala:95:{20,27}] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] wire _nodeOut_d_ready_T = state == 4'h8; // @[TSIToTileLink.scala:67:22] wire _nodeOut_d_ready_T_1 = state == 4'h4; // @[TSIToTileLink.scala:67:22] assign _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T | _nodeOut_d_ready_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [5:0] _addr_T_1 = {_addr_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _GEN_4 = {63'h0, io_tsi_in_bits_0}; // @[TSIToTileLink.scala:36:7, :103:12] wire [94:0] _addr_T_2 = _GEN_4 << _addr_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _addr_T_3 = {31'h0, addr} | _addr_T_2; // @[TSIToTileLink.scala:57:17, :103:12, :118:18] wire [1:0] _GEN_5 = {1'h0, idx}; // @[TSIToTileLink.scala:61:16, :119:16] wire [1:0] _GEN_6 = _GEN_5 + 2'h1; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T; // @[TSIToTileLink.scala:119:16] assign _idx_T = _GEN_6; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T_2; // @[TSIToTileLink.scala:128:16] assign _idx_T_2 = _GEN_6; // @[TSIToTileLink.scala:119:16, :128:16] wire [1:0] _idx_T_6; // @[TSIToTileLink.scala:154:16] assign _idx_T_6 = _GEN_6; // @[TSIToTileLink.scala:119:16, :154:16] wire [1:0] _idx_T_8; // @[TSIToTileLink.scala:166:18] assign _idx_T_8 = _GEN_6; // @[TSIToTileLink.scala:119:16, :166:18] wire _idx_T_1 = _idx_T[0]; // @[TSIToTileLink.scala:119:16] wire _T_6 = _io_tsi_in_ready_T_2 & io_tsi_in_valid_0; // @[TSIToTileLink.scala:36:7, :126:25] wire [5:0] _len_T_1 = {_len_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _len_T_2 = _GEN_4 << _len_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _len_T_3 = {31'h0, len} | _len_T_2; // @[TSIToTileLink.scala:58:16, :103:12, :127:16] wire _idx_T_3 = _idx_T_2[0]; // @[TSIToTileLink.scala:128:16] wire _GEN_7 = _T_6 & idx; // @[TSIToTileLink.scala:61:16, :126:25, :129:43] wire _idx_T_4 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33] wire _idx_T_5 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33]
Generate the Verilog code corresponding to this FIRRTL code module Tile_66 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_322 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_66( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_322 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_29 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_29 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_29( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_29 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Tile_15 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_271 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_15( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_271 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_cbus : output auto : { coupler_to_prci_ctrl_fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_l2_ctrl_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip cbus_clock_groups_in : { member : { cbus_1 : { clock : Clock, reset : Reset}, cbus_0 : { clock : Clock, reset : Reset}}}, cbus_clock_groups_out : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst cbus_clock_groups of ClockGroupAggregator_cbus inst clockGroup of ClockGroup_3 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_3 inst fixer of TLFIFOFixer_2 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_cbus_in_i1_o1_a26d64s5k1z4u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_cbus_out_i1_o3_a26d64s5k1z4u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a26d64s5k1z4u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_cbus connect atomics.clock, childClock connect atomics.reset, childReset inst wrapped_error_device of ErrorDeviceWrapper connect wrapped_error_device.clock, childClock connect wrapped_error_device.reset, childReset inst coupler_to_l2_ctrl of TLInterconnectCoupler_cbus_to_l2_ctrl connect coupler_to_l2_ctrl.clock, childClock connect coupler_to_l2_ctrl.reset, childReset inst buffer_1 of TLBuffer_a26d64s5k1z4u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bus_named_pbus of TLInterconnectCoupler_cbus_to_bus_named_pbus connect coupler_to_bus_named_pbus.clock, childClock connect coupler_to_bus_named_pbus.reset, childReset inst coupler_to_boom_l1_tracegen of TLInterconnectCoupler_cbus_to_boom_l1_tracegen connect coupler_to_boom_l1_tracegen.clock, childClock connect coupler_to_boom_l1_tracegen.reset, childReset inst coupler_to_boom_l1_tracegen_1 of TLInterconnectCoupler_cbus_to_boom_l1_tracegen_1 connect coupler_to_boom_l1_tracegen_1.clock, childClock connect coupler_to_boom_l1_tracegen_1.reset, childReset inst coupler_to_prci_ctrl of TLInterconnectCoupler_cbus_to_prci_ctrl connect coupler_to_prci_ctrl.clock, childClock connect coupler_to_prci_ctrl.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn connect clockGroup.auto.in, cbus_clock_groups.auto.out_0 connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect wrapped_error_device.auto.buffer_in, out_xbar.auto.anon_out_0 connect coupler_to_l2_ctrl.auto.tl_in, out_xbar.auto.anon_out_1 connect coupler_to_prci_ctrl.auto.tl_in, out_xbar.auto.anon_out_2 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect bus_xingIn, auto.bus_xing_in connect auto.cbus_clock_groups_out, cbus_clock_groups.auto.out_1 connect cbus_clock_groups.auto.in, auto.cbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_l2_ctrl.auto.buffer_out.d, auto.coupler_to_l2_ctrl_buffer_out.d connect auto.coupler_to_l2_ctrl_buffer_out.a.bits, coupler_to_l2_ctrl.auto.buffer_out.a.bits connect auto.coupler_to_l2_ctrl_buffer_out.a.valid, coupler_to_l2_ctrl.auto.buffer_out.a.valid connect coupler_to_l2_ctrl.auto.buffer_out.a.ready, auto.coupler_to_l2_ctrl_buffer_out.a.ready connect coupler_to_prci_ctrl.auto.fixer_anon_out.d, auto.coupler_to_prci_ctrl_fixer_anon_out.d connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.bits, coupler_to_prci_ctrl.auto.fixer_anon_out.a.bits connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.valid, coupler_to_prci_ctrl.auto.fixer_anon_out.a.valid connect coupler_to_prci_ctrl.auto.fixer_anon_out.a.ready, auto.coupler_to_prci_ctrl_fixer_anon_out.a.ready connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset
module PeripheryBus_cbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_1_clock, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_1_reset, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_cbus_clock_groups_out_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_clock_groups_out_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [25:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [4:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [4:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire [4:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire [4:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [25:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [4:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [25:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire cbus_clock_groups_auto_out_0_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_out_0_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [4:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [4:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27] wire [4:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [4:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [25:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_2_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_2_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_2_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_2_a_bits_size; // @[PeripheryBus.scala:57:30] wire [4:0] _out_xbar_auto_anon_out_2_a_bits_source; // @[PeripheryBus.scala:57:30] wire [20:0] _out_xbar_auto_anon_out_2_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_2_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_2_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [4:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [4:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_ready_0 = auto_coupler_to_l2_ctrl_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_valid_0 = auto_coupler_to_l2_ctrl_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_1_clock_0 = auto_cbus_clock_groups_in_member_cbus_1_clock; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_1_reset_0 = auto_cbus_clock_groups_in_member_cbus_1_reset; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_clock_0 = auto_cbus_clock_groups_in_member_cbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_reset_0 = auto_cbus_clock_groups_in_member_cbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire cbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire cbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [25:0] in_xbar__addressC_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] in_xbar__addressC_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] in_xbar__requestCIO_T = 26'h0; // @[Parameters.scala:137:31] wire [25:0] in_xbar__requestBOI_WIRE_bits_address = 26'h0; // @[Bundles.scala:264:74] wire [25:0] in_xbar__requestBOI_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:264:61] wire [25:0] in_xbar__beatsBO_WIRE_bits_address = 26'h0; // @[Bundles.scala:264:74] wire [25:0] in_xbar__beatsBO_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:264:61] wire [25:0] in_xbar__beatsCI_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] in_xbar__beatsCI_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] in_xbar__portsBIO_WIRE_bits_address = 26'h0; // @[Bundles.scala:264:74] wire [25:0] in_xbar__portsBIO_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:264:61] wire [25:0] in_xbar_portsBIO_filtered_0_bits_address = 26'h0; // @[Xbar.scala:352:24] wire [25:0] in_xbar__portsCOI_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] in_xbar__portsCOI_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] in_xbar_portsCOI_filtered_0_bits_address = 26'h0; // @[Xbar.scala:352:24] wire [4:0] in_xbar__addressC_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] in_xbar__addressC_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] in_xbar__requestBOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] in_xbar__requestBOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] in_xbar__requestBOI_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29] wire [4:0] in_xbar_requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] in_xbar__beatsBO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] in_xbar__beatsBO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] in_xbar__beatsCI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] in_xbar__beatsCI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] in_xbar__portsBIO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] in_xbar__portsBIO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] in_xbar_portsBIO_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] in_xbar__portsCOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] in_xbar__portsCOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] in_xbar_portsCOI_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [3:0] in_xbar__addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] in_xbar__addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] in_xbar__requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] in_xbar__requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] in_xbar__beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] in_xbar__beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] in_xbar__beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] in_xbar__beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] in_xbar__portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] in_xbar__portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] in_xbar_portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] in_xbar__portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] in_xbar__portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] in_xbar_portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [8:0] in_xbar_beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] in_xbar_beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] in_xbar_beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] in_xbar_beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [11:0] in_xbar__beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] in_xbar__beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] in_xbar__beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] in_xbar__beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] in_xbar__beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] in_xbar__beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [25:0] fixer__allIDs_FIFOed_T = 26'h3FFFFFF; // @[FIFOFixer.scala:127:48] wire [26:0] fixer__a_notFIFO_T_2 = 27'h0; // @[Parameters.scala:137:46] wire [26:0] fixer__a_notFIFO_T_3 = 27'h0; // @[Parameters.scala:137:46] wire [26:0] in_xbar__requestAIO_T_2 = 27'h0; // @[Parameters.scala:137:46] wire [26:0] in_xbar__requestAIO_T_3 = 27'h0; // @[Parameters.scala:137:46] wire [26:0] in_xbar__requestCIO_T_1 = 27'h0; // @[Parameters.scala:137:41] wire [26:0] in_xbar__requestCIO_T_2 = 27'h0; // @[Parameters.scala:137:46] wire [26:0] in_xbar__requestCIO_T_3 = 27'h0; // @[Parameters.scala:137:46] wire cbus_clock_groups_auto_in_member_cbus_1_clock = auto_cbus_clock_groups_in_member_cbus_1_clock_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_in_member_cbus_1_reset = auto_cbus_clock_groups_in_member_cbus_1_reset_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_in_member_cbus_0_clock = auto_cbus_clock_groups_in_member_cbus_0_clock_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_in_member_cbus_0_reset = auto_cbus_clock_groups_in_member_cbus_0_reset_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_out_1_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_out_1_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_out_member_pbus_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_out_member_pbus_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups_nodeIn_member_cbus_1_clock = cbus_clock_groups_auto_in_member_cbus_1_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeIn_member_cbus_1_reset = cbus_clock_groups_auto_in_member_cbus_1_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeIn_member_cbus_0_clock = cbus_clock_groups_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeIn_member_cbus_0_reset = cbus_clock_groups_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_x1_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] assign auto_cbus_clock_groups_out_member_pbus_0_clock_0 = cbus_clock_groups_auto_out_1_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_x1_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] assign auto_cbus_clock_groups_out_member_pbus_0_reset_0 = cbus_clock_groups_auto_out_1_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_cbus_0_clock = cbus_clock_groups_auto_out_0_member_cbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_cbus_0_reset = cbus_clock_groups_auto_out_0_member_cbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign cbus_clock_groups_x1_nodeOut_member_pbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_x1_nodeOut_member_pbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_nodeOut_member_cbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_nodeOut_member_cbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_auto_out_0_member_cbus_0_clock = cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_auto_out_0_member_cbus_0_reset = cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_auto_out_1_member_pbus_0_clock = cbus_clock_groups_x1_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_auto_out_1_member_pbus_0_reset = cbus_clock_groups_x1_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire clockGroup_nodeIn_member_cbus_0_clock = clockGroup_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_cbus_0_reset = clockGroup_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [25:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [25:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [25:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [25:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [26:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [26:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [26:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 27'h110000; // @[Parameters.scala:137:{41,46}] wire [26:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 27'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_15 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [25:0] fixer__a_id_T_5 = {fixer_anonIn_a_bits_address[25:21], fixer_anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [26:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [26:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 27'h100000; // @[Parameters.scala:137:{41,46}] wire [26:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 27'h0; // @[Parameters.scala:137:{46,59}] wire [25:0] fixer__a_id_T_10 = {fixer_anonIn_a_bits_address[25:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [26:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}] wire [26:0] fixer__a_id_T_12 = fixer__a_id_T_11 & 27'h110000; // @[Parameters.scala:137:{41,46}] wire [26:0] fixer__a_id_T_13 = fixer__a_id_T_12; // @[Parameters.scala:137:46] wire fixer__a_id_T_14 = fixer__a_id_T_13 == 27'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_16 = {2{fixer__a_id_T_9}}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_17 = {fixer__a_id_T_14, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_18 = {1'h0, fixer__a_id_T_15} | fixer__a_id_T_16; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_19 = fixer__a_id_T_18 | fixer__a_id_T_17; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_19; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [25:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [25:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [25:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [31:0] fixer__SourceIdSet_T = 32'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [31:0] fixer__SourceIdClear_T = 32'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [25:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_1_auto_out_a_ready = in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire buffer_1_auto_out_a_valid; // @[Buffer.scala:40:9] wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [4:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [25:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [25:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire buffer_1_auto_out_d_ready; // @[Buffer.scala:40:9] wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire buffer_1_auto_out_d_valid = in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] buffer_1_auto_out_d_bits_opcode = in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [3:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_1_auto_out_d_bits_param = in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [4:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] buffer_1_auto_out_d_bits_size = in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] buffer_1_auto_out_d_bits_source = in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire buffer_1_auto_out_d_bits_sink = in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire buffer_1_auto_out_d_bits_denied = in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] buffer_1_auto_out_d_bits_data = in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire buffer_1_auto_out_d_bits_corrupt = in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [25:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [25:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [4:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [25:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [4:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [25:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [25:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [4:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [4:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [26:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [4:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] in_xbar__beatsAI_decode_T = 27'hFFF << in_xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] in_xbar__beatsDO_decode_T = 27'hFFF << in_xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire buffer_1_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingOut_a_ready = buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_valid = buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_opcode = buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_param = buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeIn_a_bits_size = buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_1_nodeIn_a_bits_source = buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [25:0] buffer_1_nodeIn_a_bits_address = buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeIn_a_bits_mask = buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeIn_a_bits_data = buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_bits_corrupt = buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_d_ready = buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid = buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] bus_xingOut_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] bus_xingOut_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] bus_xingOut_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] bus_xingOut_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_ready = buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_valid = buffer_1_auto_out_a_valid; // @[Xbar.scala:74:9] wire [2:0] buffer_1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] buffer_1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] buffer_1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] buffer_1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Xbar.scala:74:9] wire [25:0] buffer_1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] buffer_1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] buffer_1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[Xbar.scala:74:9] wire buffer_1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire buffer_1_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign in_xbar_auto_anon_in_d_ready = buffer_1_auto_out_d_ready; // @[Xbar.scala:74:9] wire buffer_1_nodeOut_d_valid = buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_1_nodeOut_d_bits_opcode = buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeOut_d_bits_param = buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeOut_d_bits_size = buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_1_nodeOut_d_bits_source = buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_sink = buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_denied = buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeOut_d_bits_data = buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_corrupt = buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_a_ready = buffer_1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_out_a_valid = buffer_1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_opcode = buffer_1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_param = buffer_1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_size = buffer_1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_source = buffer_1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_address = buffer_1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_mask = buffer_1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_data = buffer_1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_corrupt = buffer_1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_out_d_ready = buffer_1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_d_valid = buffer_1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_opcode = buffer_1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_param = buffer_1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_size = buffer_1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_source = buffer_1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_sink = buffer_1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_denied = buffer_1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_data = buffer_1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_corrupt = buffer_1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_ready = buffer_1_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeOut_a_valid = buffer_1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_opcode = buffer_1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_param = buffer_1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_size = buffer_1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_source = buffer_1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_address = buffer_1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_mask = buffer_1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_data = buffer_1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_corrupt = buffer_1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_d_ready = buffer_1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_d_valid = buffer_1_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_opcode = buffer_1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_param = buffer_1_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_size = buffer_1_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_source = buffer_1_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_sink = buffer_1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_denied = buffer_1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_data = buffer_1_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_corrupt = buffer_1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 26'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_cbus_out_i1_o3_a26d64s5k1z4u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_param (fixer_auto_anon_out_d_bits_param), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_sink (fixer_auto_anon_out_d_bits_sink), .auto_anon_in_d_bits_denied (fixer_auto_anon_out_d_bits_denied), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_in_d_bits_corrupt (fixer_auto_anon_out_d_bits_corrupt), .auto_anon_out_2_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_2_a_valid (_out_xbar_auto_anon_out_2_a_valid), .auto_anon_out_2_a_bits_opcode (_out_xbar_auto_anon_out_2_a_bits_opcode), .auto_anon_out_2_a_bits_param (_out_xbar_auto_anon_out_2_a_bits_param), .auto_anon_out_2_a_bits_size (_out_xbar_auto_anon_out_2_a_bits_size), .auto_anon_out_2_a_bits_source (_out_xbar_auto_anon_out_2_a_bits_source), .auto_anon_out_2_a_bits_address (_out_xbar_auto_anon_out_2_a_bits_address), .auto_anon_out_2_a_bits_mask (_out_xbar_auto_anon_out_2_a_bits_mask), .auto_anon_out_2_a_bits_data (_out_xbar_auto_anon_out_2_a_bits_data), .auto_anon_out_2_a_bits_corrupt (_out_xbar_auto_anon_out_2_a_bits_corrupt), .auto_anon_out_2_d_ready (_out_xbar_auto_anon_out_2_d_ready), .auto_anon_out_2_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_2_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a26d64s5k1z4u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_param (fixer_auto_anon_in_d_bits_param), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_sink (fixer_auto_anon_in_d_bits_sink), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_denied (fixer_auto_anon_in_d_bits_denied), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_corrupt (fixer_auto_anon_in_d_bits_corrupt) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_cbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (in_xbar_auto_anon_out_a_ready), .auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (in_xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] ErrorDeviceWrapper wrapped_error_device ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_in_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), .auto_buffer_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_l2_ctrl coupler_to_l2_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (auto_coupler_to_l2_ctrl_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_coupler_to_l2_ctrl_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0), .auto_buffer_out_d_ready (auto_coupler_to_l2_ctrl_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_coupler_to_l2_ctrl_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_prci_ctrl coupler_to_prci_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fixer_anon_out_a_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_a_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0), .auto_fixer_anon_out_a_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0), .auto_fixer_anon_out_a_bits_param (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0), .auto_fixer_anon_out_a_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0), .auto_fixer_anon_out_a_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0), .auto_fixer_anon_out_a_bits_address (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0), .auto_fixer_anon_out_a_bits_mask (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0), .auto_fixer_anon_out_a_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0), .auto_fixer_anon_out_a_bits_corrupt (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0), .auto_fixer_anon_out_d_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0), .auto_fixer_anon_out_d_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_2_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_2_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_2_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_2_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_2_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_2_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_2_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_2_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_2_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_2_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid = auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready = auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_valid = auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode = auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_param = auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_size = auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_source = auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_address = auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask = auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_data = auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt = auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_d_ready = auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_cbus_clock_groups_out_member_pbus_0_clock = auto_cbus_clock_groups_out_member_pbus_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_cbus_clock_groups_out_member_pbus_0_reset = auto_cbus_clock_groups_out_member_pbus_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_149 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_149( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_197 = shr(io.in.a.bits.source, 3) node _T_198 = eq(_T_197, UInt<3>(0h4)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_291 = shr(io.in.a.bits.source, 3) node _T_292 = eq(_T_291, UInt<3>(0h4)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_347 = shr(io.in.a.bits.source, 3) node _T_348 = eq(_T_347, UInt<3>(0h4)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_445 = shr(io.in.a.bits.source, 3) node _T_446 = eq(_T_445, UInt<3>(0h4)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_528 = shr(io.in.a.bits.source, 3) node _T_529 = eq(_T_528, UInt<3>(0h4)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_548 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_549 = and(_T_547, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_556) node _T_558 = and(_T_546, _T_557) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_558, UInt<1>(0h1), "") : assert_26 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(source_ok, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(is_aligned, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_568, UInt<1>(0h1), "") : assert_29 node _T_572 = eq(io.in.a.bits.mask, mask) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_572, UInt<1>(0h1), "") : assert_30 node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_576 : node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_35) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<1>(0h1)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_36) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_593 = shr(io.in.a.bits.source, 2) node _T_594 = eq(_T_593, UInt<2>(0h2)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_37) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_598 = and(_T_596, _T_597) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_599 = shr(io.in.a.bits.source, 2) node _T_600 = eq(_T_599, UInt<2>(0h3)) node _T_601 = leq(UInt<1>(0h0), uncommonBits_38) node _T_602 = and(_T_600, _T_601) node _T_603 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_604 = and(_T_602, _T_603) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_605 = shr(io.in.a.bits.source, 3) node _T_606 = eq(_T_605, UInt<3>(0h4)) node _T_607 = leq(UInt<1>(0h0), uncommonBits_39) node _T_608 = and(_T_606, _T_607) node _T_609 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_614 = or(_T_580, _T_586) node _T_615 = or(_T_614, _T_592) node _T_616 = or(_T_615, _T_598) node _T_617 = or(_T_616, _T_604) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_579, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = and(_T_627, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_635, UInt<1>(0h1), "") : assert_31 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(source_ok, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(is_aligned, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_645, UInt<1>(0h1), "") : assert_34 node _T_649 = not(mask) node _T_650 = and(io.in.a.bits.mask, _T_649) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_651, UInt<1>(0h1), "") : assert_35 node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_655 : node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_40) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h1)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_41) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h2)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_42) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h3)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_43) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_684 = shr(io.in.a.bits.source, 3) node _T_685 = eq(_T_684, UInt<3>(0h4)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_44) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_693 = or(_T_659, _T_665) node _T_694 = or(_T_693, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = and(_T_658, _T_700) node _T_702 = or(UInt<1>(0h0), _T_701) node _T_703 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_704 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _T_706 = or(UInt<1>(0h0), _T_705) node _T_707 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<13>(0h1000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = and(_T_706, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = and(_T_702, _T_713) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_714, UInt<1>(0h1), "") : assert_36 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(source_ok, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(is_aligned, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_724 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_724, UInt<1>(0h1), "") : assert_39 node _T_728 = eq(io.in.a.bits.mask, mask) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_728, UInt<1>(0h1), "") : assert_40 node _T_732 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_732 : node _T_733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<1>(0h0)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_45) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<1>(0h1)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_46) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_749 = shr(io.in.a.bits.source, 2) node _T_750 = eq(_T_749, UInt<2>(0h2)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_47) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_755 = shr(io.in.a.bits.source, 2) node _T_756 = eq(_T_755, UInt<2>(0h3)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_48) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_760 = and(_T_758, _T_759) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_761 = shr(io.in.a.bits.source, 3) node _T_762 = eq(_T_761, UInt<3>(0h4)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_49) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_766 = and(_T_764, _T_765) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_769 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_770 = or(_T_736, _T_742) node _T_771 = or(_T_770, _T_748) node _T_772 = or(_T_771, _T_754) node _T_773 = or(_T_772, _T_760) node _T_774 = or(_T_773, _T_766) node _T_775 = or(_T_774, _T_767) node _T_776 = or(_T_775, _T_768) node _T_777 = or(_T_776, _T_769) node _T_778 = and(_T_735, _T_777) node _T_779 = or(UInt<1>(0h0), _T_778) node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_782 = and(_T_780, _T_781) node _T_783 = or(UInt<1>(0h0), _T_782) node _T_784 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_785 = cvt(_T_784) node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000))) node _T_787 = asSInt(_T_786) node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0))) node _T_789 = and(_T_783, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = and(_T_779, _T_790) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_791, UInt<1>(0h1), "") : assert_41 node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(source_ok, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(is_aligned, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_801 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_801, UInt<1>(0h1), "") : assert_44 node _T_805 = eq(io.in.a.bits.mask, mask) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_805, UInt<1>(0h1), "") : assert_45 node _T_809 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_809 : node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_811 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_812 = and(_T_810, _T_811) node _T_813 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<1>(0h0)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_50) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h1)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_51) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<2>(0h2)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_52) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h3)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_53) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_838 = shr(io.in.a.bits.source, 3) node _T_839 = eq(_T_838, UInt<3>(0h4)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_54) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_813, _T_819) node _T_848 = or(_T_847, _T_825) node _T_849 = or(_T_848, _T_831) node _T_850 = or(_T_849, _T_837) node _T_851 = or(_T_850, _T_843) node _T_852 = or(_T_851, _T_844) node _T_853 = or(_T_852, _T_845) node _T_854 = or(_T_853, _T_846) node _T_855 = and(_T_812, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_858 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_859 = and(_T_857, _T_858) node _T_860 = or(UInt<1>(0h0), _T_859) node _T_861 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<13>(0h1000))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = and(_T_860, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = and(_T_856, _T_867) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_868, UInt<1>(0h1), "") : assert_46 node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(source_ok, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(is_aligned, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_878 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_878, UInt<1>(0h1), "") : assert_49 node _T_882 = eq(io.in.a.bits.mask, mask) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_882, UInt<1>(0h1), "") : assert_50 node _T_886 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_886, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_890 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_890, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 3) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_894 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_894 : node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(source_ok_1, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_898 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_898, UInt<1>(0h1), "") : assert_54 node _T_902 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_902, UInt<1>(0h1), "") : assert_55 node _T_906 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_906, UInt<1>(0h1), "") : assert_56 node _T_910 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_910, UInt<1>(0h1), "") : assert_57 node _T_914 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_914 : node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(source_ok_1, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(sink_ok, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_921 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_921, UInt<1>(0h1), "") : assert_60 node _T_925 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_925, UInt<1>(0h1), "") : assert_61 node _T_929 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_929, UInt<1>(0h1), "") : assert_62 node _T_933 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_933, UInt<1>(0h1), "") : assert_63 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h1), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_938, UInt<1>(0h1), "") : assert_64 node _T_942 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(sink_ok, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_949 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_949, UInt<1>(0h1), "") : assert_67 node _T_953 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_953, UInt<1>(0h1), "") : assert_68 node _T_957 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_957, UInt<1>(0h1), "") : assert_69 node _T_961 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_962 = or(_T_961, io.in.d.bits.corrupt) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_962, UInt<1>(0h1), "") : assert_70 node _T_966 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_967 = or(UInt<1>(0h1), _T_966) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_967, UInt<1>(0h1), "") : assert_71 node _T_971 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(source_ok_1, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_975 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_975, UInt<1>(0h1), "") : assert_73 node _T_979 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(_T_979, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_979, UInt<1>(0h1), "") : assert_74 node _T_983 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_984 = or(UInt<1>(0h1), _T_983) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_984, UInt<1>(0h1), "") : assert_75 node _T_988 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_988 : node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(source_ok_1, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_992 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(_T_992, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_992, UInt<1>(0h1), "") : assert_77 node _T_996 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_997 = or(_T_996, io.in.d.bits.corrupt) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_997, UInt<1>(0h1), "") : assert_78 node _T_1001 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1002 = or(UInt<1>(0h1), _T_1001) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_79 node _T_1006 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(source_ok_1, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_81 node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_82 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(UInt<1>(0h1), _T_1018) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1023 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1027 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1031 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1035 = eq(a_first, UInt<1>(0h0)) node _T_1036 = and(io.in.a.valid, _T_1035) when _T_1036 : node _T_1037 = eq(io.in.a.bits.opcode, opcode) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_87 node _T_1041 = eq(io.in.a.bits.param, param) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_88 node _T_1045 = eq(io.in.a.bits.size, size) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_89 node _T_1049 = eq(io.in.a.bits.source, source) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_90 node _T_1053 = eq(io.in.a.bits.address, address) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_91 node _T_1057 = and(io.in.a.ready, io.in.a.valid) node _T_1058 = and(_T_1057, a_first) when _T_1058 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1059 = eq(d_first, UInt<1>(0h0)) node _T_1060 = and(io.in.d.valid, _T_1059) when _T_1060 : node _T_1061 = eq(io.in.d.bits.opcode, opcode_1) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_92 node _T_1065 = eq(io.in.d.bits.param, param_1) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_93 node _T_1069 = eq(io.in.d.bits.size, size_1) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_94 node _T_1073 = eq(io.in.d.bits.source, source_1) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_95 node _T_1077 = eq(io.in.d.bits.sink, sink) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_96 node _T_1081 = eq(io.in.d.bits.denied, denied) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_97 node _T_1085 = and(io.in.d.ready, io.in.d.valid) node _T_1086 = and(_T_1085, d_first) when _T_1086 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1087 = and(io.in.a.valid, a_first_1) node _T_1088 = and(_T_1087, UInt<1>(0h1)) when _T_1088 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1089 = and(io.in.a.ready, io.in.a.valid) node _T_1090 = and(_T_1089, a_first_1) node _T_1091 = and(_T_1090, UInt<1>(0h1)) when _T_1091 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1092 = dshr(inflight, io.in.a.bits.source) node _T_1093 = bits(_T_1092, 0, 0) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1098 = and(io.in.d.valid, d_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) node _T_1100 = eq(d_release_ack, UInt<1>(0h0)) node _T_1101 = and(_T_1099, _T_1100) when _T_1101 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1102 = and(io.in.d.ready, io.in.d.valid) node _T_1103 = and(_T_1102, d_first_1) node _T_1104 = and(_T_1103, UInt<1>(0h1)) node _T_1105 = eq(d_release_ack, UInt<1>(0h0)) node _T_1106 = and(_T_1104, _T_1105) when _T_1106 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1107 = and(io.in.d.valid, d_first_1) node _T_1108 = and(_T_1107, UInt<1>(0h1)) node _T_1109 = eq(d_release_ack, UInt<1>(0h0)) node _T_1110 = and(_T_1108, _T_1109) when _T_1110 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1111 = dshr(inflight, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1119 = or(_T_1117, _T_1118) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_100 node _T_1123 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_101 else : node _T_1127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1129 = or(_T_1127, _T_1128) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_102 node _T_1133 = eq(io.in.d.bits.size, a_size_lookup) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_103 node _T_1137 = and(io.in.d.valid, d_first_1) node _T_1138 = and(_T_1137, a_first_1) node _T_1139 = and(_T_1138, io.in.a.valid) node _T_1140 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1141 = and(_T_1139, _T_1140) node _T_1142 = eq(d_release_ack, UInt<1>(0h0)) node _T_1143 = and(_T_1141, _T_1142) when _T_1143 : node _T_1144 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1145 = or(_T_1144, io.in.a.ready) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_104 node _T_1149 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1150 = orr(a_set_wo_ready) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = or(_T_1149, _T_1151) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_44 node _T_1156 = orr(inflight) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) node _T_1158 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1159 = or(_T_1157, _T_1158) node _T_1160 = lt(watchdog, plusarg_reader.out) node _T_1161 = or(_T_1159, _T_1160) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1165 = and(io.in.a.ready, io.in.a.valid) node _T_1166 = and(io.in.d.ready, io.in.d.valid) node _T_1167 = or(_T_1165, _T_1166) when _T_1167 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1168 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1169 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1170 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = and(_T_1168, _T_1171) when _T_1172 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1173 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1174 = and(_T_1173, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1175 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1176 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1177 = and(_T_1175, _T_1176) node _T_1178 = and(_T_1174, _T_1177) when _T_1178 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1179 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1180 = bits(_T_1179, 0, 0) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1185 = and(io.in.d.valid, d_first_2) node _T_1186 = and(_T_1185, UInt<1>(0h1)) node _T_1187 = and(_T_1186, d_release_ack_1) when _T_1187 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1188 = and(io.in.d.ready, io.in.d.valid) node _T_1189 = and(_T_1188, d_first_2) node _T_1190 = and(_T_1189, UInt<1>(0h1)) node _T_1191 = and(_T_1190, d_release_ack_1) when _T_1191 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1192 = and(io.in.d.valid, d_first_2) node _T_1193 = and(_T_1192, UInt<1>(0h1)) node _T_1194 = and(_T_1193, d_release_ack_1) when _T_1194 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1195 = dshr(inflight_1, io.in.d.bits.source) node _T_1196 = bits(_T_1195, 0, 0) node _T_1197 = or(_T_1196, same_cycle_resp_1) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1201 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_109 else : node _T_1205 = eq(io.in.d.bits.size, c_size_lookup) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_110 node _T_1209 = and(io.in.d.valid, d_first_2) node _T_1210 = and(_T_1209, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1211 = and(_T_1210, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1212 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1213 = and(_T_1211, _T_1212) node _T_1214 = and(_T_1213, d_release_ack_1) node _T_1215 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1216 = and(_T_1214, _T_1215) when _T_1216 : node _T_1217 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1218 = or(_T_1217, _WIRE_27.ready) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_111 node _T_1222 = orr(c_set_wo_ready) when _T_1222 : node _T_1223 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_45 node _T_1227 = orr(inflight_1) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1230 = or(_T_1228, _T_1229) node _T_1231 = lt(watchdog_1, plusarg_reader_1.out) node _T_1232 = or(_T_1230, _T_1231) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1236 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1237 = and(io.in.d.ready, io.in.d.valid) node _T_1238 = or(_T_1236, _T_1237) when _T_1238 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1165; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1165; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1238 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1238; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1238; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1238; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1091 = _T_1165 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1091 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1091 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1091 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1091 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1137 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1106 = _T_1238 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1106 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1106 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1106 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1191 = _T_1238 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1191 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1191 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1191 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module FPToFP_4 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect in_pipe_v, io.in.valid reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : connect in_pipe_b, io.in.bits wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} connect in.valid, in_pipe_v connect in.bits, in_pipe_b node _signNum_T = bits(in.bits.rm, 1, 1) node _signNum_T_1 = xor(in.bits.in1, in.bits.in2) node _signNum_T_2 = bits(in.bits.rm, 0, 0) node _signNum_T_3 = not(in.bits.in2) node _signNum_T_4 = mux(_signNum_T_2, _signNum_T_3, in.bits.in2) node signNum = mux(_signNum_T, _signNum_T_1, _signNum_T_4) node _fsgnj_T = bits(signNum, 64, 64) node _fsgnj_T_1 = bits(in.bits.in1, 63, 0) node fsgnj = cat(_fsgnj_T, _fsgnj_T_1) wire fsgnjMux : { data : UInt<65>, exc : UInt<5>} connect fsgnjMux.exc, UInt<1>(0h0) connect fsgnjMux.data, fsgnj when in.bits.wflags : node _isnan1_T = bits(in.bits.in1, 63, 61) node isnan1 = andr(_isnan1_T) node _isnan2_T = bits(in.bits.in2, 63, 61) node isnan2 = andr(_isnan2_T) node _isInvalid_T = bits(in.bits.in1, 63, 61) node _isInvalid_T_1 = andr(_isInvalid_T) node _isInvalid_T_2 = bits(in.bits.in1, 51, 51) node _isInvalid_T_3 = eq(_isInvalid_T_2, UInt<1>(0h0)) node _isInvalid_T_4 = and(_isInvalid_T_1, _isInvalid_T_3) node _isInvalid_T_5 = bits(in.bits.in2, 63, 61) node _isInvalid_T_6 = andr(_isInvalid_T_5) node _isInvalid_T_7 = bits(in.bits.in2, 51, 51) node _isInvalid_T_8 = eq(_isInvalid_T_7, UInt<1>(0h0)) node _isInvalid_T_9 = and(_isInvalid_T_6, _isInvalid_T_8) node isInvalid = or(_isInvalid_T_4, _isInvalid_T_9) node isNaNOut = and(isnan1, isnan2) node _isLHS_T = bits(in.bits.rm, 0, 0) node _isLHS_T_1 = neq(_isLHS_T, io.lt) node _isLHS_T_2 = eq(isnan1, UInt<1>(0h0)) node _isLHS_T_3 = and(_isLHS_T_1, _isLHS_T_2) node isLHS = or(isnan2, _isLHS_T_3) node _fsgnjMux_exc_T = shl(isInvalid, 4) connect fsgnjMux.exc, _fsgnjMux_exc_T node _fsgnjMux_data_T = mux(isLHS, in.bits.in1, in.bits.in2) node _fsgnjMux_data_T_1 = mux(isNaNOut, UInt<65>(0he008000000000000), _fsgnjMux_data_T) connect fsgnjMux.data, _fsgnjMux_data_T_1 wire mux : { data : UInt<65>, exc : UInt<5>} connect mux, fsgnjMux node _T = eq(in.bits.typeTagOut, UInt<1>(0h0)) when _T : node _mux_data_T = shr(fsgnjMux.data, 17) node mux_data_sign = bits(fsgnjMux.data, 64, 64) node mux_data_fractIn = bits(fsgnjMux.data, 51, 0) node mux_data_expIn = bits(fsgnjMux.data, 63, 52) node _mux_data_fractOut_T = shl(mux_data_fractIn, 11) node mux_data_fractOut = shr(_mux_data_fractOut_T, 53) node mux_data_expOut_expCode = bits(mux_data_expIn, 11, 9) node _mux_data_expOut_commonCase_T = add(mux_data_expIn, UInt<6>(0h20)) node _mux_data_expOut_commonCase_T_1 = tail(_mux_data_expOut_commonCase_T, 1) node _mux_data_expOut_commonCase_T_2 = sub(_mux_data_expOut_commonCase_T_1, UInt<12>(0h800)) node mux_data_expOut_commonCase = tail(_mux_data_expOut_commonCase_T_2, 1) node _mux_data_expOut_T = eq(mux_data_expOut_expCode, UInt<1>(0h0)) node _mux_data_expOut_T_1 = geq(mux_data_expOut_expCode, UInt<3>(0h6)) node _mux_data_expOut_T_2 = or(_mux_data_expOut_T, _mux_data_expOut_T_1) node _mux_data_expOut_T_3 = bits(mux_data_expOut_commonCase, 2, 0) node _mux_data_expOut_T_4 = cat(mux_data_expOut_expCode, _mux_data_expOut_T_3) node _mux_data_expOut_T_5 = bits(mux_data_expOut_commonCase, 5, 0) node mux_data_expOut = mux(_mux_data_expOut_T_2, _mux_data_expOut_T_4, _mux_data_expOut_T_5) node mux_data_hi = cat(mux_data_sign, mux_data_expOut) node _mux_data_T_1 = cat(mux_data_hi, mux_data_fractOut) node _mux_data_T_2 = cat(_mux_data_T, _mux_data_T_1) connect mux.data, _mux_data_T_2 node _T_1 = eq(in.bits.typeTagOut, UInt<1>(0h1)) when _T_1 : node _mux_data_T_3 = shr(fsgnjMux.data, 33) node mux_data_sign_1 = bits(fsgnjMux.data, 64, 64) node mux_data_fractIn_1 = bits(fsgnjMux.data, 51, 0) node mux_data_expIn_1 = bits(fsgnjMux.data, 63, 52) node _mux_data_fractOut_T_1 = shl(mux_data_fractIn_1, 24) node mux_data_fractOut_1 = shr(_mux_data_fractOut_T_1, 53) node mux_data_expOut_expCode_1 = bits(mux_data_expIn_1, 11, 9) node _mux_data_expOut_commonCase_T_3 = add(mux_data_expIn_1, UInt<9>(0h100)) node _mux_data_expOut_commonCase_T_4 = tail(_mux_data_expOut_commonCase_T_3, 1) node _mux_data_expOut_commonCase_T_5 = sub(_mux_data_expOut_commonCase_T_4, UInt<12>(0h800)) node mux_data_expOut_commonCase_1 = tail(_mux_data_expOut_commonCase_T_5, 1) node _mux_data_expOut_T_6 = eq(mux_data_expOut_expCode_1, UInt<1>(0h0)) node _mux_data_expOut_T_7 = geq(mux_data_expOut_expCode_1, UInt<3>(0h6)) node _mux_data_expOut_T_8 = or(_mux_data_expOut_T_6, _mux_data_expOut_T_7) node _mux_data_expOut_T_9 = bits(mux_data_expOut_commonCase_1, 5, 0) node _mux_data_expOut_T_10 = cat(mux_data_expOut_expCode_1, _mux_data_expOut_T_9) node _mux_data_expOut_T_11 = bits(mux_data_expOut_commonCase_1, 8, 0) node mux_data_expOut_1 = mux(_mux_data_expOut_T_8, _mux_data_expOut_T_10, _mux_data_expOut_T_11) node mux_data_hi_1 = cat(mux_data_sign_1, mux_data_expOut_1) node _mux_data_T_4 = cat(mux_data_hi_1, mux_data_fractOut_1) node _mux_data_T_5 = cat(_mux_data_T_3, _mux_data_T_4) connect mux.data, _mux_data_T_5 node _T_2 = eq(in.bits.ren2, UInt<1>(0h0)) node _T_3 = and(in.bits.wflags, _T_2) when _T_3 : node _widened_T = bits(in.bits.in1, 63, 61) node _widened_T_1 = andr(_widened_T) node widened = mux(_widened_T_1, UInt<65>(0he008000000000000), in.bits.in1) connect fsgnjMux.data, widened node _fsgnjMux_exc_T_1 = bits(in.bits.in1, 63, 61) node _fsgnjMux_exc_T_2 = andr(_fsgnjMux_exc_T_1) node _fsgnjMux_exc_T_3 = bits(in.bits.in1, 51, 51) node _fsgnjMux_exc_T_4 = eq(_fsgnjMux_exc_T_3, UInt<1>(0h0)) node _fsgnjMux_exc_T_5 = and(_fsgnjMux_exc_T_2, _fsgnjMux_exc_T_4) node _fsgnjMux_exc_T_6 = shl(_fsgnjMux_exc_T_5, 4) connect fsgnjMux.exc, _fsgnjMux_exc_T_6 node _T_4 = eq(in.bits.typeTagOut, UInt<1>(0h0)) node _T_5 = lt(in.bits.typeTagOut, in.bits.typeTagIn) node _T_6 = or(UInt<1>(0h1), _T_5) node _T_7 = and(_T_4, _T_6) when _T_7 : inst narrower of RecFNToRecFN_8 connect narrower.io.in, in.bits.in1 connect narrower.io.roundingMode, in.bits.rm connect narrower.io.detectTininess, UInt<1>(0h1) node _mux_data_T_6 = shr(fsgnjMux.data, 17) node _mux_data_T_7 = cat(_mux_data_T_6, narrower.io.out) connect mux.data, _mux_data_T_7 connect mux.exc, narrower.io.exceptionFlags node _T_8 = eq(in.bits.typeTagOut, UInt<1>(0h1)) node _T_9 = lt(in.bits.typeTagOut, in.bits.typeTagIn) node _T_10 = or(UInt<1>(0h0), _T_9) node _T_11 = and(_T_8, _T_10) when _T_11 : inst narrower_1 of RecFNToRecFN_9 connect narrower_1.io.in, in.bits.in1 connect narrower_1.io.roundingMode, in.bits.rm connect narrower_1.io.detectTininess, UInt<1>(0h1) node _narrowed_maskedNaN_T = not(UInt<33>(0h10800000)) node narrowed_maskedNaN = and(narrower_1.io.out, _narrowed_maskedNaN_T) node _narrowed_T = bits(narrower_1.io.out, 31, 29) node _narrowed_T_1 = andr(_narrowed_T) node narrowed = mux(_narrowed_T_1, narrowed_maskedNaN, narrower_1.io.out) node _mux_data_T_8 = shr(fsgnjMux.data, 33) node _mux_data_T_9 = cat(_mux_data_T_8, narrowed) connect mux.data, _mux_data_T_9 connect mux.exc, narrower_1.io.exceptionFlags regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_v, in.valid reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock when in.valid : connect io_out_pipe_b, mux wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} connect io_out_pipe_out.valid, io_out_pipe_v connect io_out_pipe_out.bits, io_out_pipe_b connect io.out, io_out_pipe_out
module FPToFP_4( // @[FPU.scala:573:7] input clock, // @[FPU.scala:573:7] input reset, // @[FPU.scala:573:7] input io_in_valid, // @[FPU.scala:574:14] input io_in_bits_ldst, // @[FPU.scala:574:14] input io_in_bits_wen, // @[FPU.scala:574:14] input io_in_bits_ren1, // @[FPU.scala:574:14] input io_in_bits_ren2, // @[FPU.scala:574:14] input io_in_bits_ren3, // @[FPU.scala:574:14] input io_in_bits_swap12, // @[FPU.scala:574:14] input io_in_bits_swap23, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14] input io_in_bits_fromint, // @[FPU.scala:574:14] input io_in_bits_toint, // @[FPU.scala:574:14] input io_in_bits_fastpipe, // @[FPU.scala:574:14] input io_in_bits_fma, // @[FPU.scala:574:14] input io_in_bits_div, // @[FPU.scala:574:14] input io_in_bits_sqrt, // @[FPU.scala:574:14] input io_in_bits_wflags, // @[FPU.scala:574:14] input io_in_bits_vec, // @[FPU.scala:574:14] input [2:0] io_in_bits_rm, // @[FPU.scala:574:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:574:14] input [1:0] io_in_bits_typ, // @[FPU.scala:574:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:574:14] input [64:0] io_in_bits_in1, // @[FPU.scala:574:14] input [64:0] io_in_bits_in2, // @[FPU.scala:574:14] input [64:0] io_in_bits_in3, // @[FPU.scala:574:14] output [64:0] io_out_bits_data, // @[FPU.scala:574:14] output [4:0] io_out_bits_exc, // @[FPU.scala:574:14] input io_lt // @[FPU.scala:574:14] ); wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30] wire [16:0] _narrower_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:573:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:573:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:573:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:573:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:573:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:573:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:573:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:573:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:573:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:573:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:573:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:573:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:573:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:573:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:573:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:573:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:573:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:573:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:573:7] wire io_lt_0 = io_lt; // @[FPU.scala:573:7] wire [32:0] _narrowed_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:573:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:573:7] wire io_out_valid; // @[FPU.scala:573:7] reg in_pipe_v; // @[Valid.scala:141:24] wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24] reg in_pipe_b_ldst; // @[Valid.scala:142:26] wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wen; // @[Valid.scala:142:26] wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren1; // @[Valid.scala:142:26] wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren2; // @[Valid.scala:142:26] wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren3; // @[Valid.scala:142:26] wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap12; // @[Valid.scala:142:26] wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap23; // @[Valid.scala:142:26] wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fromint; // @[Valid.scala:142:26] wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_toint; // @[Valid.scala:142:26] wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fastpipe; // @[Valid.scala:142:26] wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fma; // @[Valid.scala:142:26] wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_div; // @[Valid.scala:142:26] wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_sqrt; // @[Valid.scala:142:26] wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wflags; // @[Valid.scala:142:26] wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_vec; // @[Valid.scala:142:26] wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26] reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26] wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_fmaCmd; // @[Valid.scala:142:26] wire [1:0] in_bits_fmaCmd = in_pipe_b_fmaCmd; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26] wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_fmt; // @[Valid.scala:142:26] wire [1:0] in_bits_fmt = in_pipe_b_fmt; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26] wire [64:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26] wire [64:0] in_bits_in2 = in_pipe_b_in2; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in3; // @[Valid.scala:142:26] wire [64:0] in_bits_in3 = in_pipe_b_in3; // @[Valid.scala:135:21, :142:26] wire _signNum_T = in_bits_rm[1]; // @[Valid.scala:135:21] wire [64:0] _signNum_T_1 = in_bits_in1 ^ in_bits_in2; // @[Valid.scala:135:21] wire _signNum_T_2 = in_bits_rm[0]; // @[Valid.scala:135:21] wire _isLHS_T = in_bits_rm[0]; // @[Valid.scala:135:21] wire [64:0] _signNum_T_3 = ~in_bits_in2; // @[Valid.scala:135:21] wire [64:0] _signNum_T_4 = _signNum_T_2 ? _signNum_T_3 : in_bits_in2; // @[Valid.scala:135:21] wire [64:0] signNum = _signNum_T ? _signNum_T_1 : _signNum_T_4; // @[FPU.scala:582:{20,31,48,66}] wire _fsgnj_T = signNum[64]; // @[FPU.scala:582:20, :583:26] wire [63:0] _fsgnj_T_1 = in_bits_in1[63:0]; // @[Valid.scala:135:21] wire [64:0] fsgnj = {_fsgnj_T, _fsgnj_T_1}; // @[FPU.scala:583:{18,26,45}] wire [64:0] fsgnjMux_data; // @[FPU.scala:585:22] wire [4:0] fsgnjMux_exc; // @[FPU.scala:585:22] wire [2:0] _isnan1_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _isInvalid_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _widened_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _fsgnjMux_exc_T_1 = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire isnan1 = &_isnan1_T; // @[FPU.scala:249:{25,56}] wire [2:0] _isnan2_T = in_bits_in2[63:61]; // @[Valid.scala:135:21] wire [2:0] _isInvalid_T_5 = in_bits_in2[63:61]; // @[Valid.scala:135:21] wire isnan2 = &_isnan2_T; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_1 = &_isInvalid_T; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_2 = in_bits_in1[51]; // @[Valid.scala:135:21] wire _fsgnjMux_exc_T_3 = in_bits_in1[51]; // @[Valid.scala:135:21] wire _isInvalid_T_3 = ~_isInvalid_T_2; // @[FPU.scala:250:{37,39}] wire _isInvalid_T_4 = _isInvalid_T_1 & _isInvalid_T_3; // @[FPU.scala:249:56, :250:{34,37}] wire _isInvalid_T_6 = &_isInvalid_T_5; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_7 = in_bits_in2[51]; // @[Valid.scala:135:21] wire _isInvalid_T_8 = ~_isInvalid_T_7; // @[FPU.scala:250:{37,39}] wire _isInvalid_T_9 = _isInvalid_T_6 & _isInvalid_T_8; // @[FPU.scala:249:56, :250:{34,37}] wire isInvalid = _isInvalid_T_4 | _isInvalid_T_9; // @[FPU.scala:250:34, :592:49] wire isNaNOut = isnan1 & isnan2; // @[FPU.scala:249:56, :593:27] wire _isLHS_T_1 = _isLHS_T != io_lt_0; // @[FPU.scala:573:7, :594:{37,41}] wire _isLHS_T_2 = ~isnan1; // @[FPU.scala:249:56, :594:54] wire _isLHS_T_3 = _isLHS_T_1 & _isLHS_T_2; // @[FPU.scala:594:{41,51,54}] wire isLHS = isnan2 | _isLHS_T_3; // @[FPU.scala:249:56, :594:{24,51}] wire [4:0] _fsgnjMux_exc_T = {isInvalid, 4'h0}; // @[FPU.scala:592:49, :595:31] wire [64:0] _fsgnjMux_data_T = isLHS ? in_bits_in1 : in_bits_in2; // @[Valid.scala:135:21] wire [64:0] _fsgnjMux_data_T_1 = isNaNOut ? 65'hE008000000000000 : _fsgnjMux_data_T; // @[FPU.scala:593:27, :596:{25,53}] wire [64:0] mux_data; // @[FPU.scala:601:24] wire [4:0] mux_exc; // @[FPU.scala:601:24] wire _T_7 = in_bits_typeTagOut == 2'h0; // @[Valid.scala:135:21] wire [47:0] _mux_data_T = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37] wire [47:0] _mux_data_T_6 = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37, :624:39] wire mux_data_sign = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22] wire mux_data_sign_1 = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22] wire [51:0] mux_data_fractIn = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22] wire [51:0] mux_data_fractIn_1 = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22] wire [11:0] mux_data_expIn = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22] wire [11:0] mux_data_expIn_1 = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22] wire [62:0] _mux_data_fractOut_T = {mux_data_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] mux_data_fractOut = _mux_data_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] mux_data_expOut_expCode = mux_data_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _mux_data_expOut_commonCase_T = {1'h0, mux_data_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _mux_data_expOut_commonCase_T_1 = _mux_data_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _mux_data_expOut_commonCase_T_2 = {1'h0, _mux_data_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] mux_data_expOut_commonCase = _mux_data_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _mux_data_expOut_T = mux_data_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _mux_data_expOut_T_1 = mux_data_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _mux_data_expOut_T_2 = _mux_data_expOut_T | _mux_data_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _mux_data_expOut_T_3 = mux_data_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _mux_data_expOut_T_4 = {mux_data_expOut_expCode, _mux_data_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _mux_data_expOut_T_5 = mux_data_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] mux_data_expOut = _mux_data_expOut_T_2 ? _mux_data_expOut_T_4 : _mux_data_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] mux_data_hi = {mux_data_sign, mux_data_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _mux_data_T_1 = {mux_data_hi, mux_data_fractOut}; // @[FPU.scala:277:38, :283:8] wire [64:0] _mux_data_T_2 = {_mux_data_T, _mux_data_T_1}; // @[FPU.scala:283:8, :604:{22,37}] wire _T_8 = in_bits_typeTagOut == 2'h1; // @[Valid.scala:135:21] wire [31:0] _mux_data_T_3 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37] wire [31:0] _mux_data_T_8 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37, :624:39] wire [75:0] _mux_data_fractOut_T_1 = {mux_data_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] mux_data_fractOut_1 = _mux_data_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] mux_data_expOut_expCode_1 = mux_data_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _mux_data_expOut_commonCase_T_3 = {1'h0, mux_data_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _mux_data_expOut_commonCase_T_4 = _mux_data_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _mux_data_expOut_commonCase_T_5 = {1'h0, _mux_data_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] mux_data_expOut_commonCase_1 = _mux_data_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _mux_data_expOut_T_6 = mux_data_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _mux_data_expOut_T_7 = mux_data_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _mux_data_expOut_T_8 = _mux_data_expOut_T_6 | _mux_data_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _mux_data_expOut_T_9 = mux_data_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _mux_data_expOut_T_10 = {mux_data_expOut_expCode_1, _mux_data_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _mux_data_expOut_T_11 = mux_data_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] mux_data_expOut_1 = _mux_data_expOut_T_8 ? _mux_data_expOut_T_10 : _mux_data_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] mux_data_hi_1 = {mux_data_sign_1, mux_data_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _mux_data_T_4 = {mux_data_hi_1, mux_data_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire [64:0] _mux_data_T_5 = {_mux_data_T_3, _mux_data_T_4}; // @[FPU.scala:283:8, :604:{22,37}] wire _T_3 = in_bits_wflags & ~in_bits_ren2; // @[Valid.scala:135:21] wire _widened_T_1 = &_widened_T; // @[FPU.scala:249:{25,56}] wire [64:0] widened = _widened_T_1 ? 65'hE008000000000000 : in_bits_in1; // @[Valid.scala:135:21] assign fsgnjMux_data = _T_3 ? widened : in_bits_wflags ? _fsgnjMux_data_T_1 : fsgnj; // @[Valid.scala:135:21] wire _fsgnjMux_exc_T_2 = &_fsgnjMux_exc_T_1; // @[FPU.scala:249:{25,56}] wire _fsgnjMux_exc_T_4 = ~_fsgnjMux_exc_T_3; // @[FPU.scala:250:{37,39}] wire _fsgnjMux_exc_T_5 = _fsgnjMux_exc_T_2 & _fsgnjMux_exc_T_4; // @[FPU.scala:249:56, :250:{34,37}] wire [4:0] _fsgnjMux_exc_T_6 = {_fsgnjMux_exc_T_5, 4'h0}; // @[FPU.scala:250:34, :595:31, :613:51] assign fsgnjMux_exc = _T_3 ? _fsgnjMux_exc_T_6 : in_bits_wflags ? _fsgnjMux_exc_T : 5'h0; // @[Valid.scala:135:21] wire [64:0] _mux_data_T_7 = {_mux_data_T_6, _narrower_io_out}; // @[FPU.scala:619:30, :624:{24,39}] wire _T_11 = _T_8 & in_bits_typeTagOut < in_bits_typeTagIn; // @[Valid.scala:135:21] wire [32:0] narrowed_maskedNaN = _narrower_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :619:30] wire [2:0] _narrowed_T = _narrower_1_io_out[31:29]; // @[FPU.scala:249:25, :619:30] wire _narrowed_T_1 = &_narrowed_T; // @[FPU.scala:249:{25,56}] wire [32:0] narrowed = _narrowed_T_1 ? narrowed_maskedNaN : _narrower_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :619:30] wire [64:0] _mux_data_T_9 = {_mux_data_T_8, narrowed}; // @[FPU.scala:414:10, :624:{24,39}] assign mux_data = _T_3 ? (_T_11 ? _mux_data_T_9 : _T_7 ? _mux_data_T_7 : _T_8 ? _mux_data_T_5 : fsgnjMux_data) : _T_8 ? _mux_data_T_5 : _T_7 ? _mux_data_T_2 : fsgnjMux_data; // @[FPU.scala:585:22, :601:24, :603:{18,36}, :604:{16,22}, :608:{24,42}, :618:{76,126}, :624:{18,24}] assign mux_exc = _T_3 ? (_T_11 ? _narrower_1_io_exceptionFlags : _T_7 ? _narrower_io_exceptionFlags : fsgnjMux_exc) : fsgnjMux_exc; // @[FPU.scala:585:22, :601:24, :603:18, :608:{24,42}, :618:{76,126}, :619:30, :625:17] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:573:7] if (reset) begin // @[FPU.scala:573:7] in_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:573:7] in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24] io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24] end if (io_in_valid_0) begin // @[FPU.scala:573:7] in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26] in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26] in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26] in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26] in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26] in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26] in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26] in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26] in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26] in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26] in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26] in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26] in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26] in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26] in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26] in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26] in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26] in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26] in_pipe_b_fmaCmd <= io_in_bits_fmaCmd_0; // @[Valid.scala:142:26] in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26] in_pipe_b_fmt <= io_in_bits_fmt_0; // @[Valid.scala:142:26] in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26] in_pipe_b_in2 <= io_in_bits_in2_0; // @[Valid.scala:142:26] in_pipe_b_in3 <= io_in_bits_in3_0; // @[Valid.scala:142:26] end if (in_valid) begin // @[Valid.scala:135:21] io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26] end always @(posedge) RecFNToRecFN_8 narrower ( // @[FPU.scala:619:30] .io_in (in_bits_in1), // @[Valid.scala:135:21] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_narrower_io_out), .io_exceptionFlags (_narrower_io_exceptionFlags) ); // @[FPU.scala:619:30] RecFNToRecFN_9 narrower_1 ( // @[FPU.scala:619:30] .io_in (in_bits_in1), // @[Valid.scala:135:21] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_narrower_1_io_out), .io_exceptionFlags (_narrower_1_io_exceptionFlags) ); // @[FPU.scala:619:30] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:573:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:573:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_64 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5)) node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4) node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4) node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit) node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2) node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T) node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit) node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2) node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2) node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2) node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2) node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2) node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2) node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2) node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit) node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2) node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8) node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit) node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2) node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9) node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit) node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2) node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10) node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit) node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2) node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11) node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit) node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2) node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12) node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit) node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2) node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13) node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit) node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2) node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14) node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit) node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2) node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_eq_16 = and(mask_sub_8_2, mask_nbit) node _mask_acc_T_16 = and(mask_size, mask_eq_16) node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_8_2, mask_bit) node _mask_acc_T_17 = and(mask_size, mask_eq_17) node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_9_2, mask_nbit) node _mask_acc_T_18 = and(mask_size, mask_eq_18) node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_9_2, mask_bit) node _mask_acc_T_19 = and(mask_size, mask_eq_19) node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_10_2, mask_nbit) node _mask_acc_T_20 = and(mask_size, mask_eq_20) node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_10_2, mask_bit) node _mask_acc_T_21 = and(mask_size, mask_eq_21) node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_11_2, mask_nbit) node _mask_acc_T_22 = and(mask_size, mask_eq_22) node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_11_2, mask_bit) node _mask_acc_T_23 = and(mask_size, mask_eq_23) node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_12_2, mask_nbit) node _mask_acc_T_24 = and(mask_size, mask_eq_24) node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_12_2, mask_bit) node _mask_acc_T_25 = and(mask_size, mask_eq_25) node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_13_2, mask_nbit) node _mask_acc_T_26 = and(mask_size, mask_eq_26) node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_13_2, mask_bit) node _mask_acc_T_27 = and(mask_size, mask_eq_27) node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_14_2, mask_nbit) node _mask_acc_T_28 = and(mask_size, mask_eq_28) node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_14_2, mask_bit) node _mask_acc_T_29 = and(mask_size, mask_eq_29) node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_15_2, mask_nbit) node _mask_acc_T_30 = and(mask_size, mask_eq_30) node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_15_2, mask_bit) node _mask_acc_T_31 = and(mask_size, mask_eq_31) node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31) node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo) node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo) node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16) node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18) node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo) node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20) node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22) node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24) node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26) node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo) node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_128 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<256>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<256>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<256>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<256>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<256>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<256>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<256>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<256>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<256>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<256>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<256>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<256>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_129 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:59:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<256>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59] wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14] wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27] wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25] wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28] wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28] wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_2; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_35 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_35 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_35 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h15)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_9 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_11 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_12 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_13 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_14 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_15 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_16 : connect states[7].g, UInt<3>(0h2) node _T_17 = and(io.router_req.ready, io.router_req.valid) when _T_17 : node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_18, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_22 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_23 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_24 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_25 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_26 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_27 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_28 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_29 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.router_resp.vc_sel.`4` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_30 = and(io.router_req.ready, io.router_req.valid) when _T_30 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_32 = or(_T_31, vcalloc_vals[2]) node _T_33 = or(_T_32, vcalloc_vals[3]) node _T_34 = or(_T_33, vcalloc_vals[4]) node _T_35 = or(_T_34, vcalloc_vals[5]) node _T_36 = or(_T_35, vcalloc_vals[6]) node _T_37 = or(_T_36, vcalloc_vals[7]) when _T_37 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 wire _io_vcalloc_req_bits_WIRE_38 : UInt<1>[8] node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_39 : UInt<1> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE_38[0], _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<1> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_38[1], _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<1> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_38[2], _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<1> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_38[3], _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<1> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_38[4], _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<1> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_38[5], _io_vcalloc_req_bits_WIRE_44 node _io_vcalloc_req_bits_T_578 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_579 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_579) node _io_vcalloc_req_bits_T_587 = or(_io_vcalloc_req_bits_T_586, _io_vcalloc_req_bits_T_580) node _io_vcalloc_req_bits_T_588 = or(_io_vcalloc_req_bits_T_587, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_589 = or(_io_vcalloc_req_bits_T_588, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_589, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_585) wire _io_vcalloc_req_bits_WIRE_45 : UInt<1> connect _io_vcalloc_req_bits_WIRE_45, _io_vcalloc_req_bits_T_592 connect _io_vcalloc_req_bits_WIRE_38[6], _io_vcalloc_req_bits_WIRE_45 node _io_vcalloc_req_bits_T_593 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_594 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_595 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_596 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_597 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_598 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_594) node _io_vcalloc_req_bits_T_602 = or(_io_vcalloc_req_bits_T_601, _io_vcalloc_req_bits_T_595) node _io_vcalloc_req_bits_T_603 = or(_io_vcalloc_req_bits_T_602, _io_vcalloc_req_bits_T_596) node _io_vcalloc_req_bits_T_604 = or(_io_vcalloc_req_bits_T_603, _io_vcalloc_req_bits_T_597) node _io_vcalloc_req_bits_T_605 = or(_io_vcalloc_req_bits_T_604, _io_vcalloc_req_bits_T_598) node _io_vcalloc_req_bits_T_606 = or(_io_vcalloc_req_bits_T_605, _io_vcalloc_req_bits_T_599) node _io_vcalloc_req_bits_T_607 = or(_io_vcalloc_req_bits_T_606, _io_vcalloc_req_bits_T_600) wire _io_vcalloc_req_bits_WIRE_46 : UInt<1> connect _io_vcalloc_req_bits_WIRE_46, _io_vcalloc_req_bits_T_607 connect _io_vcalloc_req_bits_WIRE_38[7], _io_vcalloc_req_bits_WIRE_46 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_38 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_610 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_611 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_612 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_613 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_614 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_615 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_608, _io_vcalloc_req_bits_T_609) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_610) node _io_vcalloc_req_bits_T_618 = or(_io_vcalloc_req_bits_T_617, _io_vcalloc_req_bits_T_611) node _io_vcalloc_req_bits_T_619 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_612) node _io_vcalloc_req_bits_T_620 = or(_io_vcalloc_req_bits_T_619, _io_vcalloc_req_bits_T_613) node _io_vcalloc_req_bits_T_621 = or(_io_vcalloc_req_bits_T_620, _io_vcalloc_req_bits_T_614) node _io_vcalloc_req_bits_T_622 = or(_io_vcalloc_req_bits_T_621, _io_vcalloc_req_bits_T_615) wire _io_vcalloc_req_bits_WIRE_47 : UInt<3> connect _io_vcalloc_req_bits_WIRE_47, _io_vcalloc_req_bits_T_622 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_47 wire _io_vcalloc_req_bits_WIRE_48 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_629 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_630 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_623, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_627) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_628) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_629) node _io_vcalloc_req_bits_T_637 = or(_io_vcalloc_req_bits_T_636, _io_vcalloc_req_bits_T_630) wire _io_vcalloc_req_bits_WIRE_49 : UInt<2> connect _io_vcalloc_req_bits_WIRE_49, _io_vcalloc_req_bits_T_637 connect _io_vcalloc_req_bits_WIRE_48.egress_node_id, _io_vcalloc_req_bits_WIRE_49 node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = or(_io_vcalloc_req_bits_T_638, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_646, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_645) wire _io_vcalloc_req_bits_WIRE_50 : UInt<5> connect _io_vcalloc_req_bits_WIRE_50, _io_vcalloc_req_bits_T_652 connect _io_vcalloc_req_bits_WIRE_48.egress_node, _io_vcalloc_req_bits_WIRE_50 node _io_vcalloc_req_bits_T_653 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_654 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_655 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_654) node _io_vcalloc_req_bits_T_662 = or(_io_vcalloc_req_bits_T_661, _io_vcalloc_req_bits_T_655) node _io_vcalloc_req_bits_T_663 = or(_io_vcalloc_req_bits_T_662, _io_vcalloc_req_bits_T_656) node _io_vcalloc_req_bits_T_664 = or(_io_vcalloc_req_bits_T_663, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_665 = or(_io_vcalloc_req_bits_T_664, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_665, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_660) wire _io_vcalloc_req_bits_WIRE_51 : UInt<2> connect _io_vcalloc_req_bits_WIRE_51, _io_vcalloc_req_bits_T_667 connect _io_vcalloc_req_bits_WIRE_48.ingress_node_id, _io_vcalloc_req_bits_WIRE_51 node _io_vcalloc_req_bits_T_668 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_669 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_670 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_671 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_672 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_673 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_674 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_669) node _io_vcalloc_req_bits_T_677 = or(_io_vcalloc_req_bits_T_676, _io_vcalloc_req_bits_T_670) node _io_vcalloc_req_bits_T_678 = or(_io_vcalloc_req_bits_T_677, _io_vcalloc_req_bits_T_671) node _io_vcalloc_req_bits_T_679 = or(_io_vcalloc_req_bits_T_678, _io_vcalloc_req_bits_T_672) node _io_vcalloc_req_bits_T_680 = or(_io_vcalloc_req_bits_T_679, _io_vcalloc_req_bits_T_673) node _io_vcalloc_req_bits_T_681 = or(_io_vcalloc_req_bits_T_680, _io_vcalloc_req_bits_T_674) node _io_vcalloc_req_bits_T_682 = or(_io_vcalloc_req_bits_T_681, _io_vcalloc_req_bits_T_675) wire _io_vcalloc_req_bits_WIRE_52 : UInt<5> connect _io_vcalloc_req_bits_WIRE_52, _io_vcalloc_req_bits_T_682 connect _io_vcalloc_req_bits_WIRE_48.ingress_node, _io_vcalloc_req_bits_WIRE_52 node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_686 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_687 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_688 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_689 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_690 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_683, _io_vcalloc_req_bits_T_684) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_685) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_686) node _io_vcalloc_req_bits_T_694 = or(_io_vcalloc_req_bits_T_693, _io_vcalloc_req_bits_T_687) node _io_vcalloc_req_bits_T_695 = or(_io_vcalloc_req_bits_T_694, _io_vcalloc_req_bits_T_688) node _io_vcalloc_req_bits_T_696 = or(_io_vcalloc_req_bits_T_695, _io_vcalloc_req_bits_T_689) node _io_vcalloc_req_bits_T_697 = or(_io_vcalloc_req_bits_T_696, _io_vcalloc_req_bits_T_690) wire _io_vcalloc_req_bits_WIRE_53 : UInt<3> connect _io_vcalloc_req_bits_WIRE_53, _io_vcalloc_req_bits_T_697 connect _io_vcalloc_req_bits_WIRE_48.vnet_id, _io_vcalloc_req_bits_WIRE_53 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_48 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].flow, states[0].flow node _T_38 = bits(vcalloc_sel, 0, 0) node _T_39 = and(vcalloc_vals[0], _T_38) node _T_40 = and(_T_39, io.vcalloc_req.ready) when _T_40 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].flow, states[1].flow node _T_41 = bits(vcalloc_sel, 1, 1) node _T_42 = and(vcalloc_vals[1], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].flow, states[2].flow node _T_44 = bits(vcalloc_sel, 2, 2) node _T_45 = and(vcalloc_vals[2], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].vc_sel.`4`, states[3].vc_sel.`4` connect vcalloc_reqs[3].flow, states[3].flow node _T_47 = bits(vcalloc_sel, 3, 3) node _T_48 = and(vcalloc_vals[3], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].vc_sel.`4`, states[4].vc_sel.`4` connect vcalloc_reqs[4].flow, states[4].flow node _T_50 = bits(vcalloc_sel, 4, 4) node _T_51 = and(vcalloc_vals[4], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].vc_sel.`4`, states[5].vc_sel.`4` connect vcalloc_reqs[5].flow, states[5].flow node _T_53 = bits(vcalloc_sel, 5, 5) node _T_54 = and(vcalloc_vals[5], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].vc_sel.`4`, states[6].vc_sel.`4` connect vcalloc_reqs[6].flow, states[6].flow node _T_56 = bits(vcalloc_sel, 6, 6) node _T_57 = and(vcalloc_vals[6], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].vc_sel.`4`, states[7].vc_sel.`4` connect vcalloc_reqs[7].flow, states[7].flow node _T_59 = bits(vcalloc_sel, 7, 7) node _T_60 = and(vcalloc_vals[7], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_62 : node _T_63 = bits(vcalloc_sel, 0, 0) when _T_63 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].g, UInt<3>(0h3) node _T_64 = eq(states[0].g, UInt<3>(0h2)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_64, UInt<1>(0h1), "") : assert_3 node _T_68 = bits(vcalloc_sel, 1, 1) when _T_68 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].g, UInt<3>(0h3) node _T_69 = eq(states[1].g, UInt<3>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_69, UInt<1>(0h1), "") : assert_4 node _T_73 = bits(vcalloc_sel, 2, 2) when _T_73 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].g, UInt<3>(0h3) node _T_74 = eq(states[2].g, UInt<3>(0h2)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = bits(vcalloc_sel, 3, 3) when _T_78 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[3].g, UInt<3>(0h3) node _T_79 = eq(states[3].g, UInt<3>(0h2)) node _T_80 = asUInt(reset) node _T_81 = eq(_T_80, UInt<1>(0h0)) when _T_81 : node _T_82 = eq(_T_79, UInt<1>(0h0)) when _T_82 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_79, UInt<1>(0h1), "") : assert_6 node _T_83 = bits(vcalloc_sel, 4, 4) when _T_83 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[4].g, UInt<3>(0h3) node _T_84 = eq(states[4].g, UInt<3>(0h2)) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_84, UInt<1>(0h1), "") : assert_7 node _T_88 = bits(vcalloc_sel, 5, 5) when _T_88 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[5].g, UInt<3>(0h3) node _T_89 = eq(states[5].g, UInt<3>(0h2)) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_89, UInt<1>(0h1), "") : assert_8 node _T_93 = bits(vcalloc_sel, 6, 6) when _T_93 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[6].g, UInt<3>(0h3) node _T_94 = eq(states[6].g, UInt<3>(0h2)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = bits(vcalloc_sel, 7, 7) when _T_98 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[7].g, UInt<3>(0h3) node _T_99 = eq(states[7].g, UInt<3>(0h2)) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_100 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_lo_4 = cat(states[0].vc_sel.`4`[1], states[0].vc_sel.`4`[0]) node credit_available_lo_hi_4 = cat(states[0].vc_sel.`4`[3], states[0].vc_sel.`4`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[0].vc_sel.`4`[5], states[0].vc_sel.`4`[4]) node credit_available_hi_hi_4 = cat(states[0].vc_sel.`4`[7], states[0].vc_sel.`4`[6]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_5 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_hi_5 = cat(_credit_available_T_4, _credit_available_T_3) node credit_available_hi_5 = cat(credit_available_hi_hi_5, _credit_available_T_2) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_8 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_lo_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_8 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, credit_available_hi_lo_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_9 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_10 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, credit_available_hi_lo_9) node _credit_available_T_10 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_11 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_hi_hi_11 = cat(_credit_available_T_10, _credit_available_T_9) node credit_available_hi_11 = cat(credit_available_hi_hi_11, _credit_available_T_8) node _credit_available_T_11 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_12 = and(_credit_available_T_5, _credit_available_T_11) node credit_available = neq(_credit_available_T_12, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3] connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4] connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6] connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3] connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4] connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5] connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6] connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1] connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3] connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4] connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5] connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6] connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`4`[1], states[0].vc_sel.`4`[1] connect salloc_arb.io.in[0].bits.vc_sel.`4`[2], states[0].vc_sel.`4`[2] connect salloc_arb.io.in[0].bits.vc_sel.`4`[3], states[0].vc_sel.`4`[3] connect salloc_arb.io.in[0].bits.vc_sel.`4`[4], states[0].vc_sel.`4`[4] connect salloc_arb.io.in[0].bits.vc_sel.`4`[5], states[0].vc_sel.`4`[5] connect salloc_arb.io.in[0].bits.vc_sel.`4`[6], states[0].vc_sel.`4`[6] connect salloc_arb.io.in[0].bits.vc_sel.`4`[7], states[0].vc_sel.`4`[7] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail) when _T_104 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_lo_10 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi_10 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi_12 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_12, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_11 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_13 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_13, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_lo_12 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_12 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_14 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_14 = cat(credit_available_hi_hi_14, credit_available_hi_lo_12) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_13 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_13 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_15 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_15, credit_available_hi_lo_13) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_14 = cat(states[1].vc_sel.`4`[1], states[1].vc_sel.`4`[0]) node credit_available_lo_hi_14 = cat(states[1].vc_sel.`4`[3], states[1].vc_sel.`4`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[1].vc_sel.`4`[5], states[1].vc_sel.`4`[4]) node credit_available_hi_hi_16 = cat(states[1].vc_sel.`4`[7], states[1].vc_sel.`4`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_16, credit_available_hi_lo_14) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_17 = cat(_credit_available_T_14, _credit_available_T_13) node credit_available_hi_hi_17 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_17 = cat(credit_available_hi_hi_17, _credit_available_T_15) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_18 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_18, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_16 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_19 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_19 = cat(credit_available_hi_hi_19, credit_available_hi_lo_16) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_17 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_20, credit_available_hi_lo_17) node _credit_available_T_21 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_18 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_18 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_21, credit_available_hi_lo_18) node _credit_available_T_22 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_19 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_19 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_22, credit_available_hi_lo_19) node _credit_available_T_23 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_23 = cat(_credit_available_T_20, _credit_available_T_19) node credit_available_hi_hi_23 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_23 = cat(credit_available_hi_hi_23, _credit_available_T_21) node _credit_available_T_24 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_25 = and(_credit_available_T_18, _credit_available_T_24) node credit_available_1 = neq(_credit_available_T_25, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`4`[1], states[1].vc_sel.`4`[1] connect salloc_arb.io.in[1].bits.vc_sel.`4`[2], states[1].vc_sel.`4`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[3], states[1].vc_sel.`4`[3] connect salloc_arb.io.in[1].bits.vc_sel.`4`[4], states[1].vc_sel.`4`[4] connect salloc_arb.io.in[1].bits.vc_sel.`4`[5], states[1].vc_sel.`4`[5] connect salloc_arb.io.in[1].bits.vc_sel.`4`[6], states[1].vc_sel.`4`[6] connect salloc_arb.io.in[1].bits.vc_sel.`4`[7], states[1].vc_sel.`4`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail) when _T_106 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_20 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_20 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_24 = cat(credit_available_hi_hi_24, credit_available_hi_lo_20) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_21 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_21 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_25, credit_available_hi_lo_21) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_22 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_22 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_26, credit_available_hi_lo_22) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_23 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_23 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_27, credit_available_hi_lo_23) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_24 = cat(states[2].vc_sel.`4`[1], states[2].vc_sel.`4`[0]) node credit_available_lo_hi_24 = cat(states[2].vc_sel.`4`[3], states[2].vc_sel.`4`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[2].vc_sel.`4`[5], states[2].vc_sel.`4`[4]) node credit_available_hi_hi_28 = cat(states[2].vc_sel.`4`[7], states[2].vc_sel.`4`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_28, credit_available_hi_lo_24) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_27, _credit_available_T_26) node credit_available_hi_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node credit_available_hi_29 = cat(credit_available_hi_hi_29, _credit_available_T_28) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node credit_available_lo_lo_25 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_25 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_30, credit_available_hi_lo_25) node _credit_available_T_32 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_26 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_26 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_31, credit_available_hi_lo_26) node _credit_available_T_33 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_27 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_27 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_32 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_32, credit_available_hi_lo_27) node _credit_available_T_34 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_28 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_33 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_33, credit_available_hi_lo_28) node _credit_available_T_35 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_lo_29 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_34 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_34 = cat(credit_available_hi_hi_34, credit_available_hi_lo_29) node _credit_available_T_36 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_35 = cat(_credit_available_T_33, _credit_available_T_32) node credit_available_hi_hi_35 = cat(_credit_available_T_36, _credit_available_T_35) node credit_available_hi_35 = cat(credit_available_hi_hi_35, _credit_available_T_34) node _credit_available_T_37 = cat(credit_available_hi_35, credit_available_lo_35) node _credit_available_T_38 = and(_credit_available_T_31, _credit_available_T_37) node credit_available_2 = neq(_credit_available_T_38, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`4`[1], states[2].vc_sel.`4`[1] connect salloc_arb.io.in[2].bits.vc_sel.`4`[2], states[2].vc_sel.`4`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[3], states[2].vc_sel.`4`[3] connect salloc_arb.io.in[2].bits.vc_sel.`4`[4], states[2].vc_sel.`4`[4] connect salloc_arb.io.in[2].bits.vc_sel.`4`[5], states[2].vc_sel.`4`[5] connect salloc_arb.io.in[2].bits.vc_sel.`4`[6], states[2].vc_sel.`4`[6] connect salloc_arb.io.in[2].bits.vc_sel.`4`[7], states[2].vc_sel.`4`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail) when _T_108 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_30 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_30 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_36 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_36, credit_available_hi_lo_30) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_31 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_31 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_37 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_37, credit_available_hi_lo_31) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_32 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_32 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_38 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_38, credit_available_hi_lo_32) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_lo_33 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_33 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_39 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_39 = cat(credit_available_hi_hi_39, credit_available_hi_lo_33) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node credit_available_lo_lo_34 = cat(states[3].vc_sel.`4`[1], states[3].vc_sel.`4`[0]) node credit_available_lo_hi_34 = cat(states[3].vc_sel.`4`[3], states[3].vc_sel.`4`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[3].vc_sel.`4`[5], states[3].vc_sel.`4`[4]) node credit_available_hi_hi_40 = cat(states[3].vc_sel.`4`[7], states[3].vc_sel.`4`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_40, credit_available_hi_lo_34) node _credit_available_T_43 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_41 = cat(_credit_available_T_40, _credit_available_T_39) node credit_available_hi_hi_41 = cat(_credit_available_T_43, _credit_available_T_42) node credit_available_hi_41 = cat(credit_available_hi_hi_41, _credit_available_T_41) node _credit_available_T_44 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_35 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_35 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_42 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_42, credit_available_hi_lo_35) node _credit_available_T_45 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_36 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_43 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_43, credit_available_hi_lo_36) node _credit_available_T_46 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_lo_37 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_44 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_44 = cat(credit_available_hi_hi_44, credit_available_hi_lo_37) node _credit_available_T_47 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_38 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_45, credit_available_hi_lo_38) node _credit_available_T_48 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_39 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_46, credit_available_hi_lo_39) node _credit_available_T_49 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_47 = cat(_credit_available_T_46, _credit_available_T_45) node credit_available_hi_hi_47 = cat(_credit_available_T_49, _credit_available_T_48) node credit_available_hi_47 = cat(credit_available_hi_hi_47, _credit_available_T_47) node _credit_available_T_50 = cat(credit_available_hi_47, credit_available_lo_47) node _credit_available_T_51 = and(_credit_available_T_44, _credit_available_T_50) node credit_available_3 = neq(_credit_available_T_51, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.vc_sel.`4`[0], states[3].vc_sel.`4`[0] connect salloc_arb.io.in[3].bits.vc_sel.`4`[1], states[3].vc_sel.`4`[1] connect salloc_arb.io.in[3].bits.vc_sel.`4`[2], states[3].vc_sel.`4`[2] connect salloc_arb.io.in[3].bits.vc_sel.`4`[3], states[3].vc_sel.`4`[3] connect salloc_arb.io.in[3].bits.vc_sel.`4`[4], states[3].vc_sel.`4`[4] connect salloc_arb.io.in[3].bits.vc_sel.`4`[5], states[3].vc_sel.`4`[5] connect salloc_arb.io.in[3].bits.vc_sel.`4`[6], states[3].vc_sel.`4`[6] connect salloc_arb.io.in[3].bits.vc_sel.`4`[7], states[3].vc_sel.`4`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail) when _T_110 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_40 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_48, credit_available_hi_lo_40) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_lo_41 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_49 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_49 = cat(credit_available_hi_hi_49, credit_available_hi_lo_41) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node credit_available_lo_lo_42 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_50, credit_available_hi_lo_42) node _credit_available_T_54 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_43 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_51, credit_available_hi_lo_43) node _credit_available_T_55 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_44 = cat(states[4].vc_sel.`4`[1], states[4].vc_sel.`4`[0]) node credit_available_lo_hi_44 = cat(states[4].vc_sel.`4`[3], states[4].vc_sel.`4`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(states[4].vc_sel.`4`[5], states[4].vc_sel.`4`[4]) node credit_available_hi_hi_52 = cat(states[4].vc_sel.`4`[7], states[4].vc_sel.`4`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_52, credit_available_hi_lo_44) node _credit_available_T_56 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_53 = cat(_credit_available_T_53, _credit_available_T_52) node credit_available_hi_hi_53 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_53 = cat(credit_available_hi_hi_53, _credit_available_T_54) node _credit_available_T_57 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_lo_45 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_54 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_54 = cat(credit_available_hi_hi_54, credit_available_hi_lo_45) node _credit_available_T_58 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_46 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_55, credit_available_hi_lo_46) node _credit_available_T_59 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_47 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_56 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_56, credit_available_hi_lo_47) node _credit_available_T_60 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_48 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_48 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_57 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_57, credit_available_hi_lo_48) node _credit_available_T_61 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_49 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_49 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_58 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_58, credit_available_hi_lo_49) node _credit_available_T_62 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_59, _credit_available_T_58) node credit_available_hi_hi_59 = cat(_credit_available_T_62, _credit_available_T_61) node credit_available_hi_59 = cat(credit_available_hi_hi_59, _credit_available_T_60) node _credit_available_T_63 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_64 = and(_credit_available_T_57, _credit_available_T_63) node credit_available_4 = neq(_credit_available_T_64, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.vc_sel.`4`[0], states[4].vc_sel.`4`[0] connect salloc_arb.io.in[4].bits.vc_sel.`4`[1], states[4].vc_sel.`4`[1] connect salloc_arb.io.in[4].bits.vc_sel.`4`[2], states[4].vc_sel.`4`[2] connect salloc_arb.io.in[4].bits.vc_sel.`4`[3], states[4].vc_sel.`4`[3] connect salloc_arb.io.in[4].bits.vc_sel.`4`[4], states[4].vc_sel.`4`[4] connect salloc_arb.io.in[4].bits.vc_sel.`4`[5], states[4].vc_sel.`4`[5] connect salloc_arb.io.in[4].bits.vc_sel.`4`[6], states[4].vc_sel.`4`[6] connect salloc_arb.io.in[4].bits.vc_sel.`4`[7], states[4].vc_sel.`4`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail) when _T_112 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_50 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_50 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_60 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_60, credit_available_hi_lo_50) node _credit_available_T_65 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_51 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_51 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_61 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_61, credit_available_hi_lo_51) node _credit_available_T_66 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_52 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_52 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_62 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_62, credit_available_hi_lo_52) node _credit_available_T_67 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_53 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_53 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_63 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_63, credit_available_hi_lo_53) node _credit_available_T_68 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_lo_54 = cat(states[5].vc_sel.`4`[1], states[5].vc_sel.`4`[0]) node credit_available_lo_hi_54 = cat(states[5].vc_sel.`4`[3], states[5].vc_sel.`4`[2]) node credit_available_lo_64 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(states[5].vc_sel.`4`[5], states[5].vc_sel.`4`[4]) node credit_available_hi_hi_64 = cat(states[5].vc_sel.`4`[7], states[5].vc_sel.`4`[6]) node credit_available_hi_64 = cat(credit_available_hi_hi_64, credit_available_hi_lo_54) node _credit_available_T_69 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_65 = cat(_credit_available_T_66, _credit_available_T_65) node credit_available_hi_hi_65 = cat(_credit_available_T_69, _credit_available_T_68) node credit_available_hi_65 = cat(credit_available_hi_hi_65, _credit_available_T_67) node _credit_available_T_70 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_55 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_66 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_66, credit_available_hi_lo_55) node _credit_available_T_71 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_56 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_56 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56) node credit_available_hi_lo_56 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_67 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_67, credit_available_hi_lo_56) node _credit_available_T_72 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_57 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_57 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57) node credit_available_hi_lo_57 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_68 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_68, credit_available_hi_lo_57) node _credit_available_T_73 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_lo_58 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_58 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_69 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58) node credit_available_hi_lo_58 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_69 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_69 = cat(credit_available_hi_hi_69, credit_available_hi_lo_58) node _credit_available_T_74 = cat(credit_available_hi_69, credit_available_lo_69) node credit_available_lo_lo_59 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_59 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_70 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59) node credit_available_hi_lo_59 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_70 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_70 = cat(credit_available_hi_hi_70, credit_available_hi_lo_59) node _credit_available_T_75 = cat(credit_available_hi_70, credit_available_lo_70) node credit_available_lo_71 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_hi_71 = cat(_credit_available_T_75, _credit_available_T_74) node credit_available_hi_71 = cat(credit_available_hi_hi_71, _credit_available_T_73) node _credit_available_T_76 = cat(credit_available_hi_71, credit_available_lo_71) node _credit_available_T_77 = and(_credit_available_T_70, _credit_available_T_76) node credit_available_5 = neq(_credit_available_T_77, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.vc_sel.`4`[0], states[5].vc_sel.`4`[0] connect salloc_arb.io.in[5].bits.vc_sel.`4`[1], states[5].vc_sel.`4`[1] connect salloc_arb.io.in[5].bits.vc_sel.`4`[2], states[5].vc_sel.`4`[2] connect salloc_arb.io.in[5].bits.vc_sel.`4`[3], states[5].vc_sel.`4`[3] connect salloc_arb.io.in[5].bits.vc_sel.`4`[4], states[5].vc_sel.`4`[4] connect salloc_arb.io.in[5].bits.vc_sel.`4`[5], states[5].vc_sel.`4`[5] connect salloc_arb.io.in[5].bits.vc_sel.`4`[6], states[5].vc_sel.`4`[6] connect salloc_arb.io.in[5].bits.vc_sel.`4`[7], states[5].vc_sel.`4`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail) when _T_114 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_60 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_60 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_72 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60) node credit_available_hi_lo_60 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_72 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_72 = cat(credit_available_hi_hi_72, credit_available_hi_lo_60) node _credit_available_T_78 = cat(credit_available_hi_72, credit_available_lo_72) node credit_available_lo_lo_61 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_61 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_73 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61) node credit_available_hi_lo_61 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_73 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_73 = cat(credit_available_hi_hi_73, credit_available_hi_lo_61) node _credit_available_T_79 = cat(credit_available_hi_73, credit_available_lo_73) node credit_available_lo_lo_62 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_62 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_74 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62) node credit_available_hi_lo_62 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_74 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_74 = cat(credit_available_hi_hi_74, credit_available_hi_lo_62) node _credit_available_T_80 = cat(credit_available_hi_74, credit_available_lo_74) node credit_available_lo_lo_63 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_63 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_75 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63) node credit_available_hi_lo_63 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_75 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_75 = cat(credit_available_hi_hi_75, credit_available_hi_lo_63) node _credit_available_T_81 = cat(credit_available_hi_75, credit_available_lo_75) node credit_available_lo_lo_64 = cat(states[6].vc_sel.`4`[1], states[6].vc_sel.`4`[0]) node credit_available_lo_hi_64 = cat(states[6].vc_sel.`4`[3], states[6].vc_sel.`4`[2]) node credit_available_lo_76 = cat(credit_available_lo_hi_64, credit_available_lo_lo_64) node credit_available_hi_lo_64 = cat(states[6].vc_sel.`4`[5], states[6].vc_sel.`4`[4]) node credit_available_hi_hi_76 = cat(states[6].vc_sel.`4`[7], states[6].vc_sel.`4`[6]) node credit_available_hi_76 = cat(credit_available_hi_hi_76, credit_available_hi_lo_64) node _credit_available_T_82 = cat(credit_available_hi_76, credit_available_lo_76) node credit_available_lo_77 = cat(_credit_available_T_79, _credit_available_T_78) node credit_available_hi_hi_77 = cat(_credit_available_T_82, _credit_available_T_81) node credit_available_hi_77 = cat(credit_available_hi_hi_77, _credit_available_T_80) node _credit_available_T_83 = cat(credit_available_hi_77, credit_available_lo_77) node credit_available_lo_lo_65 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_65 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_78 = cat(credit_available_lo_hi_65, credit_available_lo_lo_65) node credit_available_hi_lo_65 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_78 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_78 = cat(credit_available_hi_hi_78, credit_available_hi_lo_65) node _credit_available_T_84 = cat(credit_available_hi_78, credit_available_lo_78) node credit_available_lo_lo_66 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_66 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_79 = cat(credit_available_lo_hi_66, credit_available_lo_lo_66) node credit_available_hi_lo_66 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_79 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_79 = cat(credit_available_hi_hi_79, credit_available_hi_lo_66) node _credit_available_T_85 = cat(credit_available_hi_79, credit_available_lo_79) node credit_available_lo_lo_67 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_67 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_80 = cat(credit_available_lo_hi_67, credit_available_lo_lo_67) node credit_available_hi_lo_67 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_80 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_80 = cat(credit_available_hi_hi_80, credit_available_hi_lo_67) node _credit_available_T_86 = cat(credit_available_hi_80, credit_available_lo_80) node credit_available_lo_lo_68 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_68 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_81 = cat(credit_available_lo_hi_68, credit_available_lo_lo_68) node credit_available_hi_lo_68 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_81 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_81 = cat(credit_available_hi_hi_81, credit_available_hi_lo_68) node _credit_available_T_87 = cat(credit_available_hi_81, credit_available_lo_81) node credit_available_lo_lo_69 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_69 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_82 = cat(credit_available_lo_hi_69, credit_available_lo_lo_69) node credit_available_hi_lo_69 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_82 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_82 = cat(credit_available_hi_hi_82, credit_available_hi_lo_69) node _credit_available_T_88 = cat(credit_available_hi_82, credit_available_lo_82) node credit_available_lo_83 = cat(_credit_available_T_85, _credit_available_T_84) node credit_available_hi_hi_83 = cat(_credit_available_T_88, _credit_available_T_87) node credit_available_hi_83 = cat(credit_available_hi_hi_83, _credit_available_T_86) node _credit_available_T_89 = cat(credit_available_hi_83, credit_available_lo_83) node _credit_available_T_90 = and(_credit_available_T_83, _credit_available_T_89) node credit_available_6 = neq(_credit_available_T_90, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.vc_sel.`4`[0], states[6].vc_sel.`4`[0] connect salloc_arb.io.in[6].bits.vc_sel.`4`[1], states[6].vc_sel.`4`[1] connect salloc_arb.io.in[6].bits.vc_sel.`4`[2], states[6].vc_sel.`4`[2] connect salloc_arb.io.in[6].bits.vc_sel.`4`[3], states[6].vc_sel.`4`[3] connect salloc_arb.io.in[6].bits.vc_sel.`4`[4], states[6].vc_sel.`4`[4] connect salloc_arb.io.in[6].bits.vc_sel.`4`[5], states[6].vc_sel.`4`[5] connect salloc_arb.io.in[6].bits.vc_sel.`4`[6], states[6].vc_sel.`4`[6] connect salloc_arb.io.in[6].bits.vc_sel.`4`[7], states[6].vc_sel.`4`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail) when _T_116 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_70 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_70 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_84 = cat(credit_available_lo_hi_70, credit_available_lo_lo_70) node credit_available_hi_lo_70 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_84 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_84 = cat(credit_available_hi_hi_84, credit_available_hi_lo_70) node _credit_available_T_91 = cat(credit_available_hi_84, credit_available_lo_84) node credit_available_lo_lo_71 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_71 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_85 = cat(credit_available_lo_hi_71, credit_available_lo_lo_71) node credit_available_hi_lo_71 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_85 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_85 = cat(credit_available_hi_hi_85, credit_available_hi_lo_71) node _credit_available_T_92 = cat(credit_available_hi_85, credit_available_lo_85) node credit_available_lo_lo_72 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_72 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_86 = cat(credit_available_lo_hi_72, credit_available_lo_lo_72) node credit_available_hi_lo_72 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_86 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_86 = cat(credit_available_hi_hi_86, credit_available_hi_lo_72) node _credit_available_T_93 = cat(credit_available_hi_86, credit_available_lo_86) node credit_available_lo_lo_73 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_73 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_87 = cat(credit_available_lo_hi_73, credit_available_lo_lo_73) node credit_available_hi_lo_73 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_87 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_87 = cat(credit_available_hi_hi_87, credit_available_hi_lo_73) node _credit_available_T_94 = cat(credit_available_hi_87, credit_available_lo_87) node credit_available_lo_lo_74 = cat(states[7].vc_sel.`4`[1], states[7].vc_sel.`4`[0]) node credit_available_lo_hi_74 = cat(states[7].vc_sel.`4`[3], states[7].vc_sel.`4`[2]) node credit_available_lo_88 = cat(credit_available_lo_hi_74, credit_available_lo_lo_74) node credit_available_hi_lo_74 = cat(states[7].vc_sel.`4`[5], states[7].vc_sel.`4`[4]) node credit_available_hi_hi_88 = cat(states[7].vc_sel.`4`[7], states[7].vc_sel.`4`[6]) node credit_available_hi_88 = cat(credit_available_hi_hi_88, credit_available_hi_lo_74) node _credit_available_T_95 = cat(credit_available_hi_88, credit_available_lo_88) node credit_available_lo_89 = cat(_credit_available_T_92, _credit_available_T_91) node credit_available_hi_hi_89 = cat(_credit_available_T_95, _credit_available_T_94) node credit_available_hi_89 = cat(credit_available_hi_hi_89, _credit_available_T_93) node _credit_available_T_96 = cat(credit_available_hi_89, credit_available_lo_89) node credit_available_lo_lo_75 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_75 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_90 = cat(credit_available_lo_hi_75, credit_available_lo_lo_75) node credit_available_hi_lo_75 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_90 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_90 = cat(credit_available_hi_hi_90, credit_available_hi_lo_75) node _credit_available_T_97 = cat(credit_available_hi_90, credit_available_lo_90) node credit_available_lo_lo_76 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_76 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_91 = cat(credit_available_lo_hi_76, credit_available_lo_lo_76) node credit_available_hi_lo_76 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_91 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_91 = cat(credit_available_hi_hi_91, credit_available_hi_lo_76) node _credit_available_T_98 = cat(credit_available_hi_91, credit_available_lo_91) node credit_available_lo_lo_77 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_77 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_92 = cat(credit_available_lo_hi_77, credit_available_lo_lo_77) node credit_available_hi_lo_77 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_92 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_92 = cat(credit_available_hi_hi_92, credit_available_hi_lo_77) node _credit_available_T_99 = cat(credit_available_hi_92, credit_available_lo_92) node credit_available_lo_lo_78 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_78 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_93 = cat(credit_available_lo_hi_78, credit_available_lo_lo_78) node credit_available_hi_lo_78 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_93 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_93 = cat(credit_available_hi_hi_93, credit_available_hi_lo_78) node _credit_available_T_100 = cat(credit_available_hi_93, credit_available_lo_93) node credit_available_lo_lo_79 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_79 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_94 = cat(credit_available_lo_hi_79, credit_available_lo_lo_79) node credit_available_hi_lo_79 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_94 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_94 = cat(credit_available_hi_hi_94, credit_available_hi_lo_79) node _credit_available_T_101 = cat(credit_available_hi_94, credit_available_lo_94) node credit_available_lo_95 = cat(_credit_available_T_98, _credit_available_T_97) node credit_available_hi_hi_95 = cat(_credit_available_T_101, _credit_available_T_100) node credit_available_hi_95 = cat(credit_available_hi_hi_95, _credit_available_T_99) node _credit_available_T_102 = cat(credit_available_hi_95, credit_available_lo_95) node _credit_available_T_103 = and(_credit_available_T_96, _credit_available_T_102) node credit_available_7 = neq(_credit_available_T_103, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.vc_sel.`4`[0], states[7].vc_sel.`4`[0] connect salloc_arb.io.in[7].bits.vc_sel.`4`[1], states[7].vc_sel.`4`[1] connect salloc_arb.io.in[7].bits.vc_sel.`4`[2], states[7].vc_sel.`4`[2] connect salloc_arb.io.in[7].bits.vc_sel.`4`[3], states[7].vc_sel.`4`[3] connect salloc_arb.io.in[7].bits.vc_sel.`4`[4], states[7].vc_sel.`4`[4] connect salloc_arb.io.in[7].bits.vc_sel.`4`[5], states[7].vc_sel.`4`[5] connect salloc_arb.io.in[7].bits.vc_sel.`4`[6], states[7].vc_sel.`4`[6] connect salloc_arb.io.in[7].bits.vc_sel.`4`[7], states[7].vc_sel.`4`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail) when _T_118 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 wire _vc_sel_WIRE_36 : UInt<1>[8] node _vc_sel_T_488 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_495 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_496 = or(_vc_sel_T_488, _vc_sel_T_489) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_490) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_491) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_492) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_493) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_494) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_495) wire _vc_sel_WIRE_37 : UInt<1> connect _vc_sel_WIRE_37, _vc_sel_T_502 connect _vc_sel_WIRE_36[0], _vc_sel_WIRE_37 node _vc_sel_T_503 = mux(_vc_sel_T, states[0].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_504 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_511 = or(_vc_sel_T_503, _vc_sel_T_504) node _vc_sel_T_512 = or(_vc_sel_T_511, _vc_sel_T_505) node _vc_sel_T_513 = or(_vc_sel_T_512, _vc_sel_T_506) node _vc_sel_T_514 = or(_vc_sel_T_513, _vc_sel_T_507) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_508) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_509) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_510) wire _vc_sel_WIRE_38 : UInt<1> connect _vc_sel_WIRE_38, _vc_sel_T_517 connect _vc_sel_WIRE_36[1], _vc_sel_WIRE_38 node _vc_sel_T_518 = mux(_vc_sel_T, states[0].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_519 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_520 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_521 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_522 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_523 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_526 = or(_vc_sel_T_518, _vc_sel_T_519) node _vc_sel_T_527 = or(_vc_sel_T_526, _vc_sel_T_520) node _vc_sel_T_528 = or(_vc_sel_T_527, _vc_sel_T_521) node _vc_sel_T_529 = or(_vc_sel_T_528, _vc_sel_T_522) node _vc_sel_T_530 = or(_vc_sel_T_529, _vc_sel_T_523) node _vc_sel_T_531 = or(_vc_sel_T_530, _vc_sel_T_524) node _vc_sel_T_532 = or(_vc_sel_T_531, _vc_sel_T_525) wire _vc_sel_WIRE_39 : UInt<1> connect _vc_sel_WIRE_39, _vc_sel_T_532 connect _vc_sel_WIRE_36[2], _vc_sel_WIRE_39 node _vc_sel_T_533 = mux(_vc_sel_T, states[0].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_534 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_535 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_536 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_537 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_538 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_539 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_540 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_541 = or(_vc_sel_T_533, _vc_sel_T_534) node _vc_sel_T_542 = or(_vc_sel_T_541, _vc_sel_T_535) node _vc_sel_T_543 = or(_vc_sel_T_542, _vc_sel_T_536) node _vc_sel_T_544 = or(_vc_sel_T_543, _vc_sel_T_537) node _vc_sel_T_545 = or(_vc_sel_T_544, _vc_sel_T_538) node _vc_sel_T_546 = or(_vc_sel_T_545, _vc_sel_T_539) node _vc_sel_T_547 = or(_vc_sel_T_546, _vc_sel_T_540) wire _vc_sel_WIRE_40 : UInt<1> connect _vc_sel_WIRE_40, _vc_sel_T_547 connect _vc_sel_WIRE_36[3], _vc_sel_WIRE_40 node _vc_sel_T_548 = mux(_vc_sel_T, states[0].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_552 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_553 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_554 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_555 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_556 = or(_vc_sel_T_548, _vc_sel_T_549) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_550) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_551) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_552) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_553) node _vc_sel_T_561 = or(_vc_sel_T_560, _vc_sel_T_554) node _vc_sel_T_562 = or(_vc_sel_T_561, _vc_sel_T_555) wire _vc_sel_WIRE_41 : UInt<1> connect _vc_sel_WIRE_41, _vc_sel_T_562 connect _vc_sel_WIRE_36[4], _vc_sel_WIRE_41 node _vc_sel_T_563 = mux(_vc_sel_T, states[0].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_563, _vc_sel_T_564) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_565) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_566) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_567) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_568) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_569) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_570) wire _vc_sel_WIRE_42 : UInt<1> connect _vc_sel_WIRE_42, _vc_sel_T_577 connect _vc_sel_WIRE_36[5], _vc_sel_WIRE_42 node _vc_sel_T_578 = mux(_vc_sel_T, states[0].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_579 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_580 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_581 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_582 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_583 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_584 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_585 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_586 = or(_vc_sel_T_578, _vc_sel_T_579) node _vc_sel_T_587 = or(_vc_sel_T_586, _vc_sel_T_580) node _vc_sel_T_588 = or(_vc_sel_T_587, _vc_sel_T_581) node _vc_sel_T_589 = or(_vc_sel_T_588, _vc_sel_T_582) node _vc_sel_T_590 = or(_vc_sel_T_589, _vc_sel_T_583) node _vc_sel_T_591 = or(_vc_sel_T_590, _vc_sel_T_584) node _vc_sel_T_592 = or(_vc_sel_T_591, _vc_sel_T_585) wire _vc_sel_WIRE_43 : UInt<1> connect _vc_sel_WIRE_43, _vc_sel_T_592 connect _vc_sel_WIRE_36[6], _vc_sel_WIRE_43 node _vc_sel_T_593 = mux(_vc_sel_T, states[0].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_594 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_595 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_596 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_597 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_598 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_599 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_600 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_601 = or(_vc_sel_T_593, _vc_sel_T_594) node _vc_sel_T_602 = or(_vc_sel_T_601, _vc_sel_T_595) node _vc_sel_T_603 = or(_vc_sel_T_602, _vc_sel_T_596) node _vc_sel_T_604 = or(_vc_sel_T_603, _vc_sel_T_597) node _vc_sel_T_605 = or(_vc_sel_T_604, _vc_sel_T_598) node _vc_sel_T_606 = or(_vc_sel_T_605, _vc_sel_T_599) node _vc_sel_T_607 = or(_vc_sel_T_606, _vc_sel_T_600) wire _vc_sel_WIRE_44 : UInt<1> connect _vc_sel_WIRE_44, _vc_sel_T_607 connect _vc_sel_WIRE_36[7], _vc_sel_WIRE_44 connect vc_sel.`4`, _vc_sel_WIRE_36 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node _channel_oh_T_24 = or(vc_sel.`4`[0], vc_sel.`4`[1]) node _channel_oh_T_25 = or(_channel_oh_T_24, vc_sel.`4`[2]) node _channel_oh_T_26 = or(_channel_oh_T_25, vc_sel.`4`[3]) node _channel_oh_T_27 = or(_channel_oh_T_26, vc_sel.`4`[4]) node _channel_oh_T_28 = or(_channel_oh_T_27, vc_sel.`4`[5]) node _channel_oh_T_29 = or(_channel_oh_T_28, vc_sel.`4`[6]) node channel_oh_4 = or(_channel_oh_T_29, vc_sel.`4`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node virt_channel_lo_lo_4 = cat(vc_sel.`4`[1], vc_sel.`4`[0]) node virt_channel_lo_hi_4 = cat(vc_sel.`4`[3], vc_sel.`4`[2]) node virt_channel_lo_12 = cat(virt_channel_lo_hi_4, virt_channel_lo_lo_4) node virt_channel_hi_lo_4 = cat(vc_sel.`4`[5], vc_sel.`4`[4]) node virt_channel_hi_hi_4 = cat(vc_sel.`4`[7], vc_sel.`4`[6]) node virt_channel_hi_12 = cat(virt_channel_hi_hi_4, virt_channel_hi_lo_4) node _virt_channel_T_32 = cat(virt_channel_hi_12, virt_channel_lo_12) node virt_channel_hi_13 = bits(_virt_channel_T_32, 7, 4) node virt_channel_lo_13 = bits(_virt_channel_T_32, 3, 0) node _virt_channel_T_33 = orr(virt_channel_hi_13) node _virt_channel_T_34 = or(virt_channel_hi_13, virt_channel_lo_13) node virt_channel_hi_14 = bits(_virt_channel_T_34, 3, 2) node virt_channel_lo_14 = bits(_virt_channel_T_34, 1, 0) node _virt_channel_T_35 = orr(virt_channel_hi_14) node _virt_channel_T_36 = or(virt_channel_hi_14, virt_channel_lo_14) node _virt_channel_T_37 = bits(_virt_channel_T_36, 1, 1) node _virt_channel_T_38 = cat(_virt_channel_T_35, _virt_channel_T_37) node _virt_channel_T_39 = cat(_virt_channel_T_33, _virt_channel_T_38) node _virt_channel_T_40 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_41 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_42 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_43 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_44 = mux(channel_oh_4, _virt_channel_T_39, UInt<1>(0h0)) node _virt_channel_T_45 = or(_virt_channel_T_40, _virt_channel_T_41) node _virt_channel_T_46 = or(_virt_channel_T_45, _virt_channel_T_42) node _virt_channel_T_47 = or(_virt_channel_T_46, _virt_channel_T_43) node _virt_channel_T_48 = or(_virt_channel_T_47, _virt_channel_T_44) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_48 node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_119 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[3], UInt<1>(0h0) connect states[0].vc_sel.`1`[4], UInt<1>(0h0) connect states[0].vc_sel.`1`[5], UInt<1>(0h0) connect states[0].vc_sel.`1`[6], UInt<1>(0h0) connect states[0].vc_sel.`1`[7], UInt<1>(0h0) connect states[0].vc_sel.`2`[0], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[3], UInt<1>(0h0) connect states[0].vc_sel.`2`[4], UInt<1>(0h0) connect states[0].vc_sel.`2`[5], UInt<1>(0h0) connect states[0].vc_sel.`2`[6], UInt<1>(0h0) connect states[0].vc_sel.`2`[7], UInt<1>(0h0) connect states[0].vc_sel.`3`[0], UInt<1>(0h0) connect states[0].vc_sel.`3`[1], UInt<1>(0h0) connect states[0].vc_sel.`3`[2], UInt<1>(0h0) connect states[0].vc_sel.`3`[3], UInt<1>(0h0) connect states[0].vc_sel.`3`[4], UInt<1>(0h0) connect states[0].vc_sel.`3`[5], UInt<1>(0h0) connect states[0].vc_sel.`3`[6], UInt<1>(0h0) connect states[0].vc_sel.`3`[7], UInt<1>(0h0) connect states[0].vc_sel.`4`[1], UInt<1>(0h0) connect states[0].vc_sel.`4`[2], UInt<1>(0h0) connect states[0].vc_sel.`4`[3], UInt<1>(0h0) connect states[0].vc_sel.`4`[4], UInt<1>(0h0) connect states[0].vc_sel.`4`[5], UInt<1>(0h0) connect states[0].vc_sel.`4`[6], UInt<1>(0h0) connect states[0].vc_sel.`4`[7], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[5], UInt<1>(0h0) connect states[1].vc_sel.`2`[6], UInt<1>(0h0) connect states[1].vc_sel.`2`[7], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[3], UInt<1>(0h0) connect states[1].vc_sel.`3`[4], UInt<1>(0h0) connect states[1].vc_sel.`3`[5], UInt<1>(0h0) connect states[1].vc_sel.`3`[6], UInt<1>(0h0) connect states[1].vc_sel.`3`[7], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[3], UInt<1>(0h0) connect states[2].vc_sel.`3`[4], UInt<1>(0h0) connect states[2].vc_sel.`3`[5], UInt<1>(0h0) connect states[2].vc_sel.`3`[6], UInt<1>(0h0) connect states[2].vc_sel.`3`[7], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[1], UInt<1>(0h0) connect states[3].vc_sel.`3`[2], UInt<1>(0h0) connect states[3].vc_sel.`3`[3], UInt<1>(0h0) connect states[3].vc_sel.`3`[4], UInt<1>(0h0) connect states[3].vc_sel.`3`[5], UInt<1>(0h0) connect states[3].vc_sel.`3`[6], UInt<1>(0h0) connect states[3].vc_sel.`3`[7], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[1], UInt<1>(0h0) connect states[4].vc_sel.`3`[2], UInt<1>(0h0) connect states[4].vc_sel.`3`[3], UInt<1>(0h0) connect states[4].vc_sel.`3`[4], UInt<1>(0h0) connect states[4].vc_sel.`3`[5], UInt<1>(0h0) connect states[4].vc_sel.`3`[6], UInt<1>(0h0) connect states[4].vc_sel.`3`[7], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[1], UInt<1>(0h0) connect states[5].vc_sel.`3`[2], UInt<1>(0h0) connect states[5].vc_sel.`3`[3], UInt<1>(0h0) connect states[5].vc_sel.`3`[4], UInt<1>(0h0) connect states[5].vc_sel.`3`[5], UInt<1>(0h0) connect states[5].vc_sel.`3`[6], UInt<1>(0h0) connect states[5].vc_sel.`3`[7], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[1], UInt<1>(0h0) connect states[6].vc_sel.`3`[2], UInt<1>(0h0) connect states[6].vc_sel.`3`[3], UInt<1>(0h0) connect states[6].vc_sel.`3`[4], UInt<1>(0h0) connect states[6].vc_sel.`3`[5], UInt<1>(0h0) connect states[6].vc_sel.`3`[6], UInt<1>(0h0) connect states[6].vc_sel.`3`[7], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[1], UInt<1>(0h0) connect states[7].vc_sel.`3`[2], UInt<1>(0h0) connect states[7].vc_sel.`3`[3], UInt<1>(0h0) connect states[7].vc_sel.`3`[4], UInt<1>(0h0) connect states[7].vc_sel.`3`[5], UInt<1>(0h0) connect states[7].vc_sel.`3`[6], UInt<1>(0h0) connect states[7].vc_sel.`3`[7], UInt<1>(0h0) node _T_120 = asUInt(reset) when _T_120 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)
module InputUnit_35( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_1, // @[InputUnit.scala:170:14] input io_out_credit_available_4_2, // @[InputUnit.scala:170:14] input io_out_credit_available_4_3, // @[InputUnit.scala:170:14] input io_out_credit_available_4_4, // @[InputUnit.scala:170:14] input io_out_credit_available_4_5, // @[InputUnit.scala:170:14] input io_out_credit_available_4_6, // @[InputUnit.scala:170:14] input io_out_credit_available_4_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_35 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_35( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BTBBranchPredictorBank : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask node _s0_pc_T = not(io.f0_pc) node _s0_pc_T_1 = or(_s0_pc_T, UInt<3>(0h7)) node s0_pc = not(_s0_pc_T_1) reg s1_pc : UInt, clock connect s1_pc, s0_pc reg s2_pc : UInt, clock connect s2_pc, s1_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid node _s1_update_bits_pc_T = not(io.update.bits.pc) node _s1_update_bits_pc_T_1 = or(_s1_update_bits_pc_T, UInt<3>(0h7)) node _s1_update_bits_pc_T_2 = not(_s1_update_bits_pc_T_1) connect s1_update.bits.pc, _s1_update_bits_pc_T_2 reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire s1_meta : { write_way : UInt<1>} reg f3_meta_REG : { write_way : UInt<1>}, clock connect f3_meta_REG, s1_meta reg f3_meta : { write_way : UInt<1>}, clock connect f3_meta, f3_meta_REG connect io.f3_meta, f3_meta.write_way regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) wire s1_req_rmeta : { is_br : UInt<1>, tag : UInt<30>}[4][2] wire s1_req_rbtb : { offset : SInt<13>, extended : UInt<1>}[4][2] wire s1_req_rebtb : UInt<40> node s1_req_tag = shr(s1_idx, 7) wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4] wire s1_is_br : UInt<1>[4] wire s1_is_jal : UInt<1>[4] node _s1_hit_ohs_T = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_1 = eq(s1_req_rmeta[0][0].tag, _s1_hit_ohs_T) node _s1_hit_ohs_T_2 = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_3 = eq(s1_req_rmeta[1][0].tag, _s1_hit_ohs_T_2) wire _s1_hit_ohs_WIRE : UInt<1>[2] connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1 connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3 node _s1_hit_ohs_T_4 = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_5 = eq(s1_req_rmeta[0][1].tag, _s1_hit_ohs_T_4) node _s1_hit_ohs_T_6 = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_7 = eq(s1_req_rmeta[1][1].tag, _s1_hit_ohs_T_6) wire _s1_hit_ohs_WIRE_1 : UInt<1>[2] connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_5 connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_7 node _s1_hit_ohs_T_8 = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_9 = eq(s1_req_rmeta[0][2].tag, _s1_hit_ohs_T_8) node _s1_hit_ohs_T_10 = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_11 = eq(s1_req_rmeta[1][2].tag, _s1_hit_ohs_T_10) wire _s1_hit_ohs_WIRE_2 : UInt<1>[2] connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_9 connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_11 node _s1_hit_ohs_T_12 = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_13 = eq(s1_req_rmeta[0][3].tag, _s1_hit_ohs_T_12) node _s1_hit_ohs_T_14 = bits(s1_req_tag, 29, 0) node _s1_hit_ohs_T_15 = eq(s1_req_rmeta[1][3].tag, _s1_hit_ohs_T_14) wire _s1_hit_ohs_WIRE_3 : UInt<1>[2] connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_13 connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_15 wire s1_hit_ohs : UInt<1>[2][4] connect s1_hit_ohs[0], _s1_hit_ohs_WIRE connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1 connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2 connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3 node s1_hits_0 = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1]) node s1_hits_1 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1]) node s1_hits_2 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1]) node s1_hits_3 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1]) node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), UInt<1>(0h1)) node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), UInt<1>(0h1)) wire s1_targs : UInt<40>[4][2] wire entry_btb : { offset : SInt<13>, extended : UInt<1>} connect entry_btb, s1_req_rbtb[0][0] node _s1_targs_0_0_T = asSInt(s1_pc) node _s1_targs_0_0_T_1 = add(_s1_targs_0_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_0_0_T_2 = tail(_s1_targs_0_0_T_1, 1) node _s1_targs_0_0_T_3 = asSInt(_s1_targs_0_0_T_2) node _s1_targs_0_0_T_4 = add(_s1_targs_0_0_T_3, entry_btb.offset) node _s1_targs_0_0_T_5 = tail(_s1_targs_0_0_T_4, 1) node _s1_targs_0_0_T_6 = asSInt(_s1_targs_0_0_T_5) node _s1_targs_0_0_T_7 = asUInt(_s1_targs_0_0_T_6) node _s1_targs_0_0_T_8 = mux(entry_btb.extended, s1_req_rebtb, _s1_targs_0_0_T_7) connect s1_targs[0][0], _s1_targs_0_0_T_8 wire entry_btb_1 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_1, s1_req_rbtb[1][0] node _s1_targs_1_0_T = asSInt(s1_pc) node _s1_targs_1_0_T_1 = add(_s1_targs_1_0_T, asSInt(UInt<1>(0h0))) node _s1_targs_1_0_T_2 = tail(_s1_targs_1_0_T_1, 1) node _s1_targs_1_0_T_3 = asSInt(_s1_targs_1_0_T_2) node _s1_targs_1_0_T_4 = add(_s1_targs_1_0_T_3, entry_btb_1.offset) node _s1_targs_1_0_T_5 = tail(_s1_targs_1_0_T_4, 1) node _s1_targs_1_0_T_6 = asSInt(_s1_targs_1_0_T_5) node _s1_targs_1_0_T_7 = asUInt(_s1_targs_1_0_T_6) node _s1_targs_1_0_T_8 = mux(entry_btb_1.extended, s1_req_rebtb, _s1_targs_1_0_T_7) connect s1_targs[1][0], _s1_targs_1_0_T_8 node _s1_resp_0_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_0_valid_T_1 = and(_s1_resp_0_valid_T, s1_valid) node _s1_resp_0_valid_T_2 = and(_s1_resp_0_valid_T_1, s1_hits_0) connect s1_resp[0].valid, _s1_resp_0_valid_T_2 connect s1_resp[0].bits, s1_targs[s1_hit_ways_0][0] node _s1_is_br_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_0_T_1 = and(_s1_is_br_0_T, s1_resp[0].valid) node _s1_is_br_0_T_2 = and(_s1_is_br_0_T_1, s1_req_rmeta[s1_hit_ways_0][0].is_br) connect s1_is_br[0], _s1_is_br_0_T_2 node _s1_is_jal_0_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_0_T_1 = and(_s1_is_jal_0_T, s1_resp[0].valid) node _s1_is_jal_0_T_2 = eq(s1_req_rmeta[s1_hit_ways_0][0].is_br, UInt<1>(0h0)) node _s1_is_jal_0_T_3 = and(_s1_is_jal_0_T_1, _s1_is_jal_0_T_2) connect s1_is_jal[0], _s1_is_jal_0_T_3 connect io.resp.f1[0], io.resp_in[0].f1[0] connect io.resp.f2[0], io.resp_in[0].f2[0] connect io.resp.f3[0], io.resp_in[0].f3[0] reg REG : UInt<1>, clock connect REG, s1_hits_0 when REG : reg io_resp_f2_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_0_predicted_pc_REG, s1_resp[0] connect io.resp.f2[0].predicted_pc, io_resp_f2_0_predicted_pc_REG reg io_resp_f2_0_is_br_REG : UInt<1>, clock connect io_resp_f2_0_is_br_REG, s1_is_br[0] connect io.resp.f2[0].is_br, io_resp_f2_0_is_br_REG reg io_resp_f2_0_is_jal_REG : UInt<1>, clock connect io_resp_f2_0_is_jal_REG, s1_is_jal[0] connect io.resp.f2[0].is_jal, io_resp_f2_0_is_jal_REG reg REG_1 : UInt<1>, clock connect REG_1, s1_is_jal[0] when REG_1 : connect io.resp.f2[0].taken, UInt<1>(0h1) reg REG_2 : UInt<1>, clock connect REG_2, s1_hits_0 reg REG_3 : UInt<1>, clock connect REG_3, REG_2 when REG_3 : reg io_resp_f3_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_0_predicted_pc_REG.bits, io.resp.f2[0].predicted_pc.bits connect io_resp_f3_0_predicted_pc_REG.valid, io.resp.f2[0].predicted_pc.valid connect io.resp.f3[0].predicted_pc, io_resp_f3_0_predicted_pc_REG reg io_resp_f3_0_is_br_REG : UInt<1>, clock connect io_resp_f3_0_is_br_REG, io.resp.f2[0].is_br connect io.resp.f3[0].is_br, io_resp_f3_0_is_br_REG reg io_resp_f3_0_is_jal_REG : UInt<1>, clock connect io_resp_f3_0_is_jal_REG, io.resp.f2[0].is_jal connect io.resp.f3[0].is_jal, io_resp_f3_0_is_jal_REG reg REG_4 : UInt<1>, clock connect REG_4, s1_is_jal[0] reg REG_5 : UInt<1>, clock connect REG_5, REG_4 when REG_5 : connect io.resp.f3[0].taken, UInt<1>(0h1) wire entry_btb_2 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_2, s1_req_rbtb[0][1] node _s1_targs_0_1_T = asSInt(s1_pc) node _s1_targs_0_1_T_1 = add(_s1_targs_0_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_0_1_T_2 = tail(_s1_targs_0_1_T_1, 1) node _s1_targs_0_1_T_3 = asSInt(_s1_targs_0_1_T_2) node _s1_targs_0_1_T_4 = add(_s1_targs_0_1_T_3, entry_btb_2.offset) node _s1_targs_0_1_T_5 = tail(_s1_targs_0_1_T_4, 1) node _s1_targs_0_1_T_6 = asSInt(_s1_targs_0_1_T_5) node _s1_targs_0_1_T_7 = asUInt(_s1_targs_0_1_T_6) node _s1_targs_0_1_T_8 = mux(entry_btb_2.extended, s1_req_rebtb, _s1_targs_0_1_T_7) connect s1_targs[0][1], _s1_targs_0_1_T_8 wire entry_btb_3 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_3, s1_req_rbtb[1][1] node _s1_targs_1_1_T = asSInt(s1_pc) node _s1_targs_1_1_T_1 = add(_s1_targs_1_1_T, asSInt(UInt<3>(0h2))) node _s1_targs_1_1_T_2 = tail(_s1_targs_1_1_T_1, 1) node _s1_targs_1_1_T_3 = asSInt(_s1_targs_1_1_T_2) node _s1_targs_1_1_T_4 = add(_s1_targs_1_1_T_3, entry_btb_3.offset) node _s1_targs_1_1_T_5 = tail(_s1_targs_1_1_T_4, 1) node _s1_targs_1_1_T_6 = asSInt(_s1_targs_1_1_T_5) node _s1_targs_1_1_T_7 = asUInt(_s1_targs_1_1_T_6) node _s1_targs_1_1_T_8 = mux(entry_btb_3.extended, s1_req_rebtb, _s1_targs_1_1_T_7) connect s1_targs[1][1], _s1_targs_1_1_T_8 node _s1_resp_1_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_1_valid_T_1 = and(_s1_resp_1_valid_T, s1_valid) node _s1_resp_1_valid_T_2 = and(_s1_resp_1_valid_T_1, s1_hits_1) connect s1_resp[1].valid, _s1_resp_1_valid_T_2 connect s1_resp[1].bits, s1_targs[s1_hit_ways_1][1] node _s1_is_br_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_1_T_1 = and(_s1_is_br_1_T, s1_resp[1].valid) node _s1_is_br_1_T_2 = and(_s1_is_br_1_T_1, s1_req_rmeta[s1_hit_ways_1][1].is_br) connect s1_is_br[1], _s1_is_br_1_T_2 node _s1_is_jal_1_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_1_T_1 = and(_s1_is_jal_1_T, s1_resp[1].valid) node _s1_is_jal_1_T_2 = eq(s1_req_rmeta[s1_hit_ways_1][1].is_br, UInt<1>(0h0)) node _s1_is_jal_1_T_3 = and(_s1_is_jal_1_T_1, _s1_is_jal_1_T_2) connect s1_is_jal[1], _s1_is_jal_1_T_3 connect io.resp.f1[1], io.resp_in[0].f1[1] connect io.resp.f2[1], io.resp_in[0].f2[1] connect io.resp.f3[1], io.resp_in[0].f3[1] reg REG_6 : UInt<1>, clock connect REG_6, s1_hits_1 when REG_6 : reg io_resp_f2_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_1_predicted_pc_REG, s1_resp[1] connect io.resp.f2[1].predicted_pc, io_resp_f2_1_predicted_pc_REG reg io_resp_f2_1_is_br_REG : UInt<1>, clock connect io_resp_f2_1_is_br_REG, s1_is_br[1] connect io.resp.f2[1].is_br, io_resp_f2_1_is_br_REG reg io_resp_f2_1_is_jal_REG : UInt<1>, clock connect io_resp_f2_1_is_jal_REG, s1_is_jal[1] connect io.resp.f2[1].is_jal, io_resp_f2_1_is_jal_REG reg REG_7 : UInt<1>, clock connect REG_7, s1_is_jal[1] when REG_7 : connect io.resp.f2[1].taken, UInt<1>(0h1) reg REG_8 : UInt<1>, clock connect REG_8, s1_hits_1 reg REG_9 : UInt<1>, clock connect REG_9, REG_8 when REG_9 : reg io_resp_f3_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_1_predicted_pc_REG.bits, io.resp.f2[1].predicted_pc.bits connect io_resp_f3_1_predicted_pc_REG.valid, io.resp.f2[1].predicted_pc.valid connect io.resp.f3[1].predicted_pc, io_resp_f3_1_predicted_pc_REG reg io_resp_f3_1_is_br_REG : UInt<1>, clock connect io_resp_f3_1_is_br_REG, io.resp.f2[1].is_br connect io.resp.f3[1].is_br, io_resp_f3_1_is_br_REG reg io_resp_f3_1_is_jal_REG : UInt<1>, clock connect io_resp_f3_1_is_jal_REG, io.resp.f2[1].is_jal connect io.resp.f3[1].is_jal, io_resp_f3_1_is_jal_REG reg REG_10 : UInt<1>, clock connect REG_10, s1_is_jal[1] reg REG_11 : UInt<1>, clock connect REG_11, REG_10 when REG_11 : connect io.resp.f3[1].taken, UInt<1>(0h1) wire entry_btb_4 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_4, s1_req_rbtb[0][2] node _s1_targs_0_2_T = asSInt(s1_pc) node _s1_targs_0_2_T_1 = add(_s1_targs_0_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_0_2_T_2 = tail(_s1_targs_0_2_T_1, 1) node _s1_targs_0_2_T_3 = asSInt(_s1_targs_0_2_T_2) node _s1_targs_0_2_T_4 = add(_s1_targs_0_2_T_3, entry_btb_4.offset) node _s1_targs_0_2_T_5 = tail(_s1_targs_0_2_T_4, 1) node _s1_targs_0_2_T_6 = asSInt(_s1_targs_0_2_T_5) node _s1_targs_0_2_T_7 = asUInt(_s1_targs_0_2_T_6) node _s1_targs_0_2_T_8 = mux(entry_btb_4.extended, s1_req_rebtb, _s1_targs_0_2_T_7) connect s1_targs[0][2], _s1_targs_0_2_T_8 wire entry_btb_5 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_5, s1_req_rbtb[1][2] node _s1_targs_1_2_T = asSInt(s1_pc) node _s1_targs_1_2_T_1 = add(_s1_targs_1_2_T, asSInt(UInt<4>(0h4))) node _s1_targs_1_2_T_2 = tail(_s1_targs_1_2_T_1, 1) node _s1_targs_1_2_T_3 = asSInt(_s1_targs_1_2_T_2) node _s1_targs_1_2_T_4 = add(_s1_targs_1_2_T_3, entry_btb_5.offset) node _s1_targs_1_2_T_5 = tail(_s1_targs_1_2_T_4, 1) node _s1_targs_1_2_T_6 = asSInt(_s1_targs_1_2_T_5) node _s1_targs_1_2_T_7 = asUInt(_s1_targs_1_2_T_6) node _s1_targs_1_2_T_8 = mux(entry_btb_5.extended, s1_req_rebtb, _s1_targs_1_2_T_7) connect s1_targs[1][2], _s1_targs_1_2_T_8 node _s1_resp_2_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_2_valid_T_1 = and(_s1_resp_2_valid_T, s1_valid) node _s1_resp_2_valid_T_2 = and(_s1_resp_2_valid_T_1, s1_hits_2) connect s1_resp[2].valid, _s1_resp_2_valid_T_2 connect s1_resp[2].bits, s1_targs[s1_hit_ways_2][2] node _s1_is_br_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_2_T_1 = and(_s1_is_br_2_T, s1_resp[2].valid) node _s1_is_br_2_T_2 = and(_s1_is_br_2_T_1, s1_req_rmeta[s1_hit_ways_2][2].is_br) connect s1_is_br[2], _s1_is_br_2_T_2 node _s1_is_jal_2_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_2_T_1 = and(_s1_is_jal_2_T, s1_resp[2].valid) node _s1_is_jal_2_T_2 = eq(s1_req_rmeta[s1_hit_ways_2][2].is_br, UInt<1>(0h0)) node _s1_is_jal_2_T_3 = and(_s1_is_jal_2_T_1, _s1_is_jal_2_T_2) connect s1_is_jal[2], _s1_is_jal_2_T_3 connect io.resp.f1[2], io.resp_in[0].f1[2] connect io.resp.f2[2], io.resp_in[0].f2[2] connect io.resp.f3[2], io.resp_in[0].f3[2] reg REG_12 : UInt<1>, clock connect REG_12, s1_hits_2 when REG_12 : reg io_resp_f2_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_2_predicted_pc_REG, s1_resp[2] connect io.resp.f2[2].predicted_pc, io_resp_f2_2_predicted_pc_REG reg io_resp_f2_2_is_br_REG : UInt<1>, clock connect io_resp_f2_2_is_br_REG, s1_is_br[2] connect io.resp.f2[2].is_br, io_resp_f2_2_is_br_REG reg io_resp_f2_2_is_jal_REG : UInt<1>, clock connect io_resp_f2_2_is_jal_REG, s1_is_jal[2] connect io.resp.f2[2].is_jal, io_resp_f2_2_is_jal_REG reg REG_13 : UInt<1>, clock connect REG_13, s1_is_jal[2] when REG_13 : connect io.resp.f2[2].taken, UInt<1>(0h1) reg REG_14 : UInt<1>, clock connect REG_14, s1_hits_2 reg REG_15 : UInt<1>, clock connect REG_15, REG_14 when REG_15 : reg io_resp_f3_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_2_predicted_pc_REG.bits, io.resp.f2[2].predicted_pc.bits connect io_resp_f3_2_predicted_pc_REG.valid, io.resp.f2[2].predicted_pc.valid connect io.resp.f3[2].predicted_pc, io_resp_f3_2_predicted_pc_REG reg io_resp_f3_2_is_br_REG : UInt<1>, clock connect io_resp_f3_2_is_br_REG, io.resp.f2[2].is_br connect io.resp.f3[2].is_br, io_resp_f3_2_is_br_REG reg io_resp_f3_2_is_jal_REG : UInt<1>, clock connect io_resp_f3_2_is_jal_REG, io.resp.f2[2].is_jal connect io.resp.f3[2].is_jal, io_resp_f3_2_is_jal_REG reg REG_16 : UInt<1>, clock connect REG_16, s1_is_jal[2] reg REG_17 : UInt<1>, clock connect REG_17, REG_16 when REG_17 : connect io.resp.f3[2].taken, UInt<1>(0h1) wire entry_btb_6 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_6, s1_req_rbtb[0][3] node _s1_targs_0_3_T = asSInt(s1_pc) node _s1_targs_0_3_T_1 = add(_s1_targs_0_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_0_3_T_2 = tail(_s1_targs_0_3_T_1, 1) node _s1_targs_0_3_T_3 = asSInt(_s1_targs_0_3_T_2) node _s1_targs_0_3_T_4 = add(_s1_targs_0_3_T_3, entry_btb_6.offset) node _s1_targs_0_3_T_5 = tail(_s1_targs_0_3_T_4, 1) node _s1_targs_0_3_T_6 = asSInt(_s1_targs_0_3_T_5) node _s1_targs_0_3_T_7 = asUInt(_s1_targs_0_3_T_6) node _s1_targs_0_3_T_8 = mux(entry_btb_6.extended, s1_req_rebtb, _s1_targs_0_3_T_7) connect s1_targs[0][3], _s1_targs_0_3_T_8 wire entry_btb_7 : { offset : SInt<13>, extended : UInt<1>} connect entry_btb_7, s1_req_rbtb[1][3] node _s1_targs_1_3_T = asSInt(s1_pc) node _s1_targs_1_3_T_1 = add(_s1_targs_1_3_T, asSInt(UInt<4>(0h6))) node _s1_targs_1_3_T_2 = tail(_s1_targs_1_3_T_1, 1) node _s1_targs_1_3_T_3 = asSInt(_s1_targs_1_3_T_2) node _s1_targs_1_3_T_4 = add(_s1_targs_1_3_T_3, entry_btb_7.offset) node _s1_targs_1_3_T_5 = tail(_s1_targs_1_3_T_4, 1) node _s1_targs_1_3_T_6 = asSInt(_s1_targs_1_3_T_5) node _s1_targs_1_3_T_7 = asUInt(_s1_targs_1_3_T_6) node _s1_targs_1_3_T_8 = mux(entry_btb_7.extended, s1_req_rebtb, _s1_targs_1_3_T_7) connect s1_targs[1][3], _s1_targs_1_3_T_8 node _s1_resp_3_valid_T = eq(doing_reset, UInt<1>(0h0)) node _s1_resp_3_valid_T_1 = and(_s1_resp_3_valid_T, s1_valid) node _s1_resp_3_valid_T_2 = and(_s1_resp_3_valid_T_1, s1_hits_3) connect s1_resp[3].valid, _s1_resp_3_valid_T_2 connect s1_resp[3].bits, s1_targs[s1_hit_ways_3][3] node _s1_is_br_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_br_3_T_1 = and(_s1_is_br_3_T, s1_resp[3].valid) node _s1_is_br_3_T_2 = and(_s1_is_br_3_T_1, s1_req_rmeta[s1_hit_ways_3][3].is_br) connect s1_is_br[3], _s1_is_br_3_T_2 node _s1_is_jal_3_T = eq(doing_reset, UInt<1>(0h0)) node _s1_is_jal_3_T_1 = and(_s1_is_jal_3_T, s1_resp[3].valid) node _s1_is_jal_3_T_2 = eq(s1_req_rmeta[s1_hit_ways_3][3].is_br, UInt<1>(0h0)) node _s1_is_jal_3_T_3 = and(_s1_is_jal_3_T_1, _s1_is_jal_3_T_2) connect s1_is_jal[3], _s1_is_jal_3_T_3 connect io.resp.f1[3], io.resp_in[0].f1[3] connect io.resp.f2[3], io.resp_in[0].f2[3] connect io.resp.f3[3], io.resp_in[0].f3[3] reg REG_18 : UInt<1>, clock connect REG_18, s1_hits_3 when REG_18 : reg io_resp_f2_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f2_3_predicted_pc_REG, s1_resp[3] connect io.resp.f2[3].predicted_pc, io_resp_f2_3_predicted_pc_REG reg io_resp_f2_3_is_br_REG : UInt<1>, clock connect io_resp_f2_3_is_br_REG, s1_is_br[3] connect io.resp.f2[3].is_br, io_resp_f2_3_is_br_REG reg io_resp_f2_3_is_jal_REG : UInt<1>, clock connect io_resp_f2_3_is_jal_REG, s1_is_jal[3] connect io.resp.f2[3].is_jal, io_resp_f2_3_is_jal_REG reg REG_19 : UInt<1>, clock connect REG_19, s1_is_jal[3] when REG_19 : connect io.resp.f2[3].taken, UInt<1>(0h1) reg REG_20 : UInt<1>, clock connect REG_20, s1_hits_3 reg REG_21 : UInt<1>, clock connect REG_21, REG_20 when REG_21 : reg io_resp_f3_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock connect io_resp_f3_3_predicted_pc_REG.bits, io.resp.f2[3].predicted_pc.bits connect io_resp_f3_3_predicted_pc_REG.valid, io.resp.f2[3].predicted_pc.valid connect io.resp.f3[3].predicted_pc, io_resp_f3_3_predicted_pc_REG reg io_resp_f3_3_is_br_REG : UInt<1>, clock connect io_resp_f3_3_is_br_REG, io.resp.f2[3].is_br connect io.resp.f3[3].is_br, io_resp_f3_3_is_br_REG reg io_resp_f3_3_is_jal_REG : UInt<1>, clock connect io_resp_f3_3_is_jal_REG, io.resp.f2[3].is_jal connect io.resp.f3[3].is_jal, io_resp_f3_3_is_jal_REG reg REG_22 : UInt<1>, clock connect REG_22, s1_is_jal[3] reg REG_23 : UInt<1>, clock connect REG_23, REG_22 when REG_23 : connect io.resp.f3[3].taken, UInt<1>(0h1) wire _alloc_way_r_metas_WIRE : UInt<30>[4] connect _alloc_way_r_metas_WIRE[0], s1_req_rmeta[0][0].tag connect _alloc_way_r_metas_WIRE[1], s1_req_rmeta[0][1].tag connect _alloc_way_r_metas_WIRE[2], s1_req_rmeta[0][2].tag connect _alloc_way_r_metas_WIRE[3], s1_req_rmeta[0][3].tag wire _alloc_way_r_metas_WIRE_1 : UInt<30>[4] connect _alloc_way_r_metas_WIRE_1[0], s1_req_rmeta[1][0].tag connect _alloc_way_r_metas_WIRE_1[1], s1_req_rmeta[1][1].tag connect _alloc_way_r_metas_WIRE_1[2], s1_req_rmeta[1][2].tag connect _alloc_way_r_metas_WIRE_1[3], s1_req_rmeta[1][3].tag wire _alloc_way_r_metas_WIRE_2 : UInt<30>[4][2] connect _alloc_way_r_metas_WIRE_2[0], _alloc_way_r_metas_WIRE connect _alloc_way_r_metas_WIRE_2[1], _alloc_way_r_metas_WIRE_1 node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_2[0][1], _alloc_way_r_metas_WIRE_2[0][0]) node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_2[0][3], _alloc_way_r_metas_WIRE_2[0][2]) node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo) node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_2[1][1], _alloc_way_r_metas_WIRE_2[1][0]) node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_2[1][3], _alloc_way_r_metas_WIRE_2[1][2]) node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1) node _alloc_way_r_metas_T_2 = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T) node _alloc_way_r_metas_T_3 = bits(s1_req_tag, 29, 0) node alloc_way_r_metas = cat(_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3) node alloc_way_chunks_0 = bits(alloc_way_r_metas, 0, 0) node alloc_way_chunks_1 = bits(alloc_way_r_metas, 1, 1) node alloc_way_chunks_2 = bits(alloc_way_r_metas, 2, 2) node alloc_way_chunks_3 = bits(alloc_way_r_metas, 3, 3) node alloc_way_chunks_4 = bits(alloc_way_r_metas, 4, 4) node alloc_way_chunks_5 = bits(alloc_way_r_metas, 5, 5) node alloc_way_chunks_6 = bits(alloc_way_r_metas, 6, 6) node alloc_way_chunks_7 = bits(alloc_way_r_metas, 7, 7) node alloc_way_chunks_8 = bits(alloc_way_r_metas, 8, 8) node alloc_way_chunks_9 = bits(alloc_way_r_metas, 9, 9) node alloc_way_chunks_10 = bits(alloc_way_r_metas, 10, 10) node alloc_way_chunks_11 = bits(alloc_way_r_metas, 11, 11) node alloc_way_chunks_12 = bits(alloc_way_r_metas, 12, 12) node alloc_way_chunks_13 = bits(alloc_way_r_metas, 13, 13) node alloc_way_chunks_14 = bits(alloc_way_r_metas, 14, 14) node alloc_way_chunks_15 = bits(alloc_way_r_metas, 15, 15) node alloc_way_chunks_16 = bits(alloc_way_r_metas, 16, 16) node alloc_way_chunks_17 = bits(alloc_way_r_metas, 17, 17) node alloc_way_chunks_18 = bits(alloc_way_r_metas, 18, 18) node alloc_way_chunks_19 = bits(alloc_way_r_metas, 19, 19) node alloc_way_chunks_20 = bits(alloc_way_r_metas, 20, 20) node alloc_way_chunks_21 = bits(alloc_way_r_metas, 21, 21) node alloc_way_chunks_22 = bits(alloc_way_r_metas, 22, 22) node alloc_way_chunks_23 = bits(alloc_way_r_metas, 23, 23) node alloc_way_chunks_24 = bits(alloc_way_r_metas, 24, 24) node alloc_way_chunks_25 = bits(alloc_way_r_metas, 25, 25) node alloc_way_chunks_26 = bits(alloc_way_r_metas, 26, 26) node alloc_way_chunks_27 = bits(alloc_way_r_metas, 27, 27) node alloc_way_chunks_28 = bits(alloc_way_r_metas, 28, 28) node alloc_way_chunks_29 = bits(alloc_way_r_metas, 29, 29) node alloc_way_chunks_30 = bits(alloc_way_r_metas, 30, 30) node alloc_way_chunks_31 = bits(alloc_way_r_metas, 31, 31) node alloc_way_chunks_32 = bits(alloc_way_r_metas, 32, 32) node alloc_way_chunks_33 = bits(alloc_way_r_metas, 33, 33) node alloc_way_chunks_34 = bits(alloc_way_r_metas, 34, 34) node alloc_way_chunks_35 = bits(alloc_way_r_metas, 35, 35) node alloc_way_chunks_36 = bits(alloc_way_r_metas, 36, 36) node alloc_way_chunks_37 = bits(alloc_way_r_metas, 37, 37) node alloc_way_chunks_38 = bits(alloc_way_r_metas, 38, 38) node alloc_way_chunks_39 = bits(alloc_way_r_metas, 39, 39) node alloc_way_chunks_40 = bits(alloc_way_r_metas, 40, 40) node alloc_way_chunks_41 = bits(alloc_way_r_metas, 41, 41) node alloc_way_chunks_42 = bits(alloc_way_r_metas, 42, 42) node alloc_way_chunks_43 = bits(alloc_way_r_metas, 43, 43) node alloc_way_chunks_44 = bits(alloc_way_r_metas, 44, 44) node alloc_way_chunks_45 = bits(alloc_way_r_metas, 45, 45) node alloc_way_chunks_46 = bits(alloc_way_r_metas, 46, 46) node alloc_way_chunks_47 = bits(alloc_way_r_metas, 47, 47) node alloc_way_chunks_48 = bits(alloc_way_r_metas, 48, 48) node alloc_way_chunks_49 = bits(alloc_way_r_metas, 49, 49) node alloc_way_chunks_50 = bits(alloc_way_r_metas, 50, 50) node alloc_way_chunks_51 = bits(alloc_way_r_metas, 51, 51) node alloc_way_chunks_52 = bits(alloc_way_r_metas, 52, 52) node alloc_way_chunks_53 = bits(alloc_way_r_metas, 53, 53) node alloc_way_chunks_54 = bits(alloc_way_r_metas, 54, 54) node alloc_way_chunks_55 = bits(alloc_way_r_metas, 55, 55) node alloc_way_chunks_56 = bits(alloc_way_r_metas, 56, 56) node alloc_way_chunks_57 = bits(alloc_way_r_metas, 57, 57) node alloc_way_chunks_58 = bits(alloc_way_r_metas, 58, 58) node alloc_way_chunks_59 = bits(alloc_way_r_metas, 59, 59) node alloc_way_chunks_60 = bits(alloc_way_r_metas, 60, 60) node alloc_way_chunks_61 = bits(alloc_way_r_metas, 61, 61) node alloc_way_chunks_62 = bits(alloc_way_r_metas, 62, 62) node alloc_way_chunks_63 = bits(alloc_way_r_metas, 63, 63) node alloc_way_chunks_64 = bits(alloc_way_r_metas, 64, 64) node alloc_way_chunks_65 = bits(alloc_way_r_metas, 65, 65) node alloc_way_chunks_66 = bits(alloc_way_r_metas, 66, 66) node alloc_way_chunks_67 = bits(alloc_way_r_metas, 67, 67) node alloc_way_chunks_68 = bits(alloc_way_r_metas, 68, 68) node alloc_way_chunks_69 = bits(alloc_way_r_metas, 69, 69) node alloc_way_chunks_70 = bits(alloc_way_r_metas, 70, 70) node alloc_way_chunks_71 = bits(alloc_way_r_metas, 71, 71) node alloc_way_chunks_72 = bits(alloc_way_r_metas, 72, 72) node alloc_way_chunks_73 = bits(alloc_way_r_metas, 73, 73) node alloc_way_chunks_74 = bits(alloc_way_r_metas, 74, 74) node alloc_way_chunks_75 = bits(alloc_way_r_metas, 75, 75) node alloc_way_chunks_76 = bits(alloc_way_r_metas, 76, 76) node alloc_way_chunks_77 = bits(alloc_way_r_metas, 77, 77) node alloc_way_chunks_78 = bits(alloc_way_r_metas, 78, 78) node alloc_way_chunks_79 = bits(alloc_way_r_metas, 79, 79) node alloc_way_chunks_80 = bits(alloc_way_r_metas, 80, 80) node alloc_way_chunks_81 = bits(alloc_way_r_metas, 81, 81) node alloc_way_chunks_82 = bits(alloc_way_r_metas, 82, 82) node alloc_way_chunks_83 = bits(alloc_way_r_metas, 83, 83) node alloc_way_chunks_84 = bits(alloc_way_r_metas, 84, 84) node alloc_way_chunks_85 = bits(alloc_way_r_metas, 85, 85) node alloc_way_chunks_86 = bits(alloc_way_r_metas, 86, 86) node alloc_way_chunks_87 = bits(alloc_way_r_metas, 87, 87) node alloc_way_chunks_88 = bits(alloc_way_r_metas, 88, 88) node alloc_way_chunks_89 = bits(alloc_way_r_metas, 89, 89) node alloc_way_chunks_90 = bits(alloc_way_r_metas, 90, 90) node alloc_way_chunks_91 = bits(alloc_way_r_metas, 91, 91) node alloc_way_chunks_92 = bits(alloc_way_r_metas, 92, 92) node alloc_way_chunks_93 = bits(alloc_way_r_metas, 93, 93) node alloc_way_chunks_94 = bits(alloc_way_r_metas, 94, 94) node alloc_way_chunks_95 = bits(alloc_way_r_metas, 95, 95) node alloc_way_chunks_96 = bits(alloc_way_r_metas, 96, 96) node alloc_way_chunks_97 = bits(alloc_way_r_metas, 97, 97) node alloc_way_chunks_98 = bits(alloc_way_r_metas, 98, 98) node alloc_way_chunks_99 = bits(alloc_way_r_metas, 99, 99) node alloc_way_chunks_100 = bits(alloc_way_r_metas, 100, 100) node alloc_way_chunks_101 = bits(alloc_way_r_metas, 101, 101) node alloc_way_chunks_102 = bits(alloc_way_r_metas, 102, 102) node alloc_way_chunks_103 = bits(alloc_way_r_metas, 103, 103) node alloc_way_chunks_104 = bits(alloc_way_r_metas, 104, 104) node alloc_way_chunks_105 = bits(alloc_way_r_metas, 105, 105) node alloc_way_chunks_106 = bits(alloc_way_r_metas, 106, 106) node alloc_way_chunks_107 = bits(alloc_way_r_metas, 107, 107) node alloc_way_chunks_108 = bits(alloc_way_r_metas, 108, 108) node alloc_way_chunks_109 = bits(alloc_way_r_metas, 109, 109) node alloc_way_chunks_110 = bits(alloc_way_r_metas, 110, 110) node alloc_way_chunks_111 = bits(alloc_way_r_metas, 111, 111) node alloc_way_chunks_112 = bits(alloc_way_r_metas, 112, 112) node alloc_way_chunks_113 = bits(alloc_way_r_metas, 113, 113) node alloc_way_chunks_114 = bits(alloc_way_r_metas, 114, 114) node alloc_way_chunks_115 = bits(alloc_way_r_metas, 115, 115) node alloc_way_chunks_116 = bits(alloc_way_r_metas, 116, 116) node alloc_way_chunks_117 = bits(alloc_way_r_metas, 117, 117) node alloc_way_chunks_118 = bits(alloc_way_r_metas, 118, 118) node alloc_way_chunks_119 = bits(alloc_way_r_metas, 119, 119) node alloc_way_chunks_120 = bits(alloc_way_r_metas, 120, 120) node alloc_way_chunks_121 = bits(alloc_way_r_metas, 121, 121) node alloc_way_chunks_122 = bits(alloc_way_r_metas, 122, 122) node alloc_way_chunks_123 = bits(alloc_way_r_metas, 123, 123) node alloc_way_chunks_124 = bits(alloc_way_r_metas, 124, 124) node alloc_way_chunks_125 = bits(alloc_way_r_metas, 125, 125) node alloc_way_chunks_126 = bits(alloc_way_r_metas, 126, 126) node alloc_way_chunks_127 = bits(alloc_way_r_metas, 127, 127) node alloc_way_chunks_128 = bits(alloc_way_r_metas, 128, 128) node alloc_way_chunks_129 = bits(alloc_way_r_metas, 129, 129) node alloc_way_chunks_130 = bits(alloc_way_r_metas, 130, 130) node alloc_way_chunks_131 = bits(alloc_way_r_metas, 131, 131) node alloc_way_chunks_132 = bits(alloc_way_r_metas, 132, 132) node alloc_way_chunks_133 = bits(alloc_way_r_metas, 133, 133) node alloc_way_chunks_134 = bits(alloc_way_r_metas, 134, 134) node alloc_way_chunks_135 = bits(alloc_way_r_metas, 135, 135) node alloc_way_chunks_136 = bits(alloc_way_r_metas, 136, 136) node alloc_way_chunks_137 = bits(alloc_way_r_metas, 137, 137) node alloc_way_chunks_138 = bits(alloc_way_r_metas, 138, 138) node alloc_way_chunks_139 = bits(alloc_way_r_metas, 139, 139) node alloc_way_chunks_140 = bits(alloc_way_r_metas, 140, 140) node alloc_way_chunks_141 = bits(alloc_way_r_metas, 141, 141) node alloc_way_chunks_142 = bits(alloc_way_r_metas, 142, 142) node alloc_way_chunks_143 = bits(alloc_way_r_metas, 143, 143) node alloc_way_chunks_144 = bits(alloc_way_r_metas, 144, 144) node alloc_way_chunks_145 = bits(alloc_way_r_metas, 145, 145) node alloc_way_chunks_146 = bits(alloc_way_r_metas, 146, 146) node alloc_way_chunks_147 = bits(alloc_way_r_metas, 147, 147) node alloc_way_chunks_148 = bits(alloc_way_r_metas, 148, 148) node alloc_way_chunks_149 = bits(alloc_way_r_metas, 149, 149) node alloc_way_chunks_150 = bits(alloc_way_r_metas, 150, 150) node alloc_way_chunks_151 = bits(alloc_way_r_metas, 151, 151) node alloc_way_chunks_152 = bits(alloc_way_r_metas, 152, 152) node alloc_way_chunks_153 = bits(alloc_way_r_metas, 153, 153) node alloc_way_chunks_154 = bits(alloc_way_r_metas, 154, 154) node alloc_way_chunks_155 = bits(alloc_way_r_metas, 155, 155) node alloc_way_chunks_156 = bits(alloc_way_r_metas, 156, 156) node alloc_way_chunks_157 = bits(alloc_way_r_metas, 157, 157) node alloc_way_chunks_158 = bits(alloc_way_r_metas, 158, 158) node alloc_way_chunks_159 = bits(alloc_way_r_metas, 159, 159) node alloc_way_chunks_160 = bits(alloc_way_r_metas, 160, 160) node alloc_way_chunks_161 = bits(alloc_way_r_metas, 161, 161) node alloc_way_chunks_162 = bits(alloc_way_r_metas, 162, 162) node alloc_way_chunks_163 = bits(alloc_way_r_metas, 163, 163) node alloc_way_chunks_164 = bits(alloc_way_r_metas, 164, 164) node alloc_way_chunks_165 = bits(alloc_way_r_metas, 165, 165) node alloc_way_chunks_166 = bits(alloc_way_r_metas, 166, 166) node alloc_way_chunks_167 = bits(alloc_way_r_metas, 167, 167) node alloc_way_chunks_168 = bits(alloc_way_r_metas, 168, 168) node alloc_way_chunks_169 = bits(alloc_way_r_metas, 169, 169) node alloc_way_chunks_170 = bits(alloc_way_r_metas, 170, 170) node alloc_way_chunks_171 = bits(alloc_way_r_metas, 171, 171) node alloc_way_chunks_172 = bits(alloc_way_r_metas, 172, 172) node alloc_way_chunks_173 = bits(alloc_way_r_metas, 173, 173) node alloc_way_chunks_174 = bits(alloc_way_r_metas, 174, 174) node alloc_way_chunks_175 = bits(alloc_way_r_metas, 175, 175) node alloc_way_chunks_176 = bits(alloc_way_r_metas, 176, 176) node alloc_way_chunks_177 = bits(alloc_way_r_metas, 177, 177) node alloc_way_chunks_178 = bits(alloc_way_r_metas, 178, 178) node alloc_way_chunks_179 = bits(alloc_way_r_metas, 179, 179) node alloc_way_chunks_180 = bits(alloc_way_r_metas, 180, 180) node alloc_way_chunks_181 = bits(alloc_way_r_metas, 181, 181) node alloc_way_chunks_182 = bits(alloc_way_r_metas, 182, 182) node alloc_way_chunks_183 = bits(alloc_way_r_metas, 183, 183) node alloc_way_chunks_184 = bits(alloc_way_r_metas, 184, 184) node alloc_way_chunks_185 = bits(alloc_way_r_metas, 185, 185) node alloc_way_chunks_186 = bits(alloc_way_r_metas, 186, 186) node alloc_way_chunks_187 = bits(alloc_way_r_metas, 187, 187) node alloc_way_chunks_188 = bits(alloc_way_r_metas, 188, 188) node alloc_way_chunks_189 = bits(alloc_way_r_metas, 189, 189) node alloc_way_chunks_190 = bits(alloc_way_r_metas, 190, 190) node alloc_way_chunks_191 = bits(alloc_way_r_metas, 191, 191) node alloc_way_chunks_192 = bits(alloc_way_r_metas, 192, 192) node alloc_way_chunks_193 = bits(alloc_way_r_metas, 193, 193) node alloc_way_chunks_194 = bits(alloc_way_r_metas, 194, 194) node alloc_way_chunks_195 = bits(alloc_way_r_metas, 195, 195) node alloc_way_chunks_196 = bits(alloc_way_r_metas, 196, 196) node alloc_way_chunks_197 = bits(alloc_way_r_metas, 197, 197) node alloc_way_chunks_198 = bits(alloc_way_r_metas, 198, 198) node alloc_way_chunks_199 = bits(alloc_way_r_metas, 199, 199) node alloc_way_chunks_200 = bits(alloc_way_r_metas, 200, 200) node alloc_way_chunks_201 = bits(alloc_way_r_metas, 201, 201) node alloc_way_chunks_202 = bits(alloc_way_r_metas, 202, 202) node alloc_way_chunks_203 = bits(alloc_way_r_metas, 203, 203) node alloc_way_chunks_204 = bits(alloc_way_r_metas, 204, 204) node alloc_way_chunks_205 = bits(alloc_way_r_metas, 205, 205) node alloc_way_chunks_206 = bits(alloc_way_r_metas, 206, 206) node alloc_way_chunks_207 = bits(alloc_way_r_metas, 207, 207) node alloc_way_chunks_208 = bits(alloc_way_r_metas, 208, 208) node alloc_way_chunks_209 = bits(alloc_way_r_metas, 209, 209) node alloc_way_chunks_210 = bits(alloc_way_r_metas, 210, 210) node alloc_way_chunks_211 = bits(alloc_way_r_metas, 211, 211) node alloc_way_chunks_212 = bits(alloc_way_r_metas, 212, 212) node alloc_way_chunks_213 = bits(alloc_way_r_metas, 213, 213) node alloc_way_chunks_214 = bits(alloc_way_r_metas, 214, 214) node alloc_way_chunks_215 = bits(alloc_way_r_metas, 215, 215) node alloc_way_chunks_216 = bits(alloc_way_r_metas, 216, 216) node alloc_way_chunks_217 = bits(alloc_way_r_metas, 217, 217) node alloc_way_chunks_218 = bits(alloc_way_r_metas, 218, 218) node alloc_way_chunks_219 = bits(alloc_way_r_metas, 219, 219) node alloc_way_chunks_220 = bits(alloc_way_r_metas, 220, 220) node alloc_way_chunks_221 = bits(alloc_way_r_metas, 221, 221) node alloc_way_chunks_222 = bits(alloc_way_r_metas, 222, 222) node alloc_way_chunks_223 = bits(alloc_way_r_metas, 223, 223) node alloc_way_chunks_224 = bits(alloc_way_r_metas, 224, 224) node alloc_way_chunks_225 = bits(alloc_way_r_metas, 225, 225) node alloc_way_chunks_226 = bits(alloc_way_r_metas, 226, 226) node alloc_way_chunks_227 = bits(alloc_way_r_metas, 227, 227) node alloc_way_chunks_228 = bits(alloc_way_r_metas, 228, 228) node alloc_way_chunks_229 = bits(alloc_way_r_metas, 229, 229) node alloc_way_chunks_230 = bits(alloc_way_r_metas, 230, 230) node alloc_way_chunks_231 = bits(alloc_way_r_metas, 231, 231) node alloc_way_chunks_232 = bits(alloc_way_r_metas, 232, 232) node alloc_way_chunks_233 = bits(alloc_way_r_metas, 233, 233) node alloc_way_chunks_234 = bits(alloc_way_r_metas, 234, 234) node alloc_way_chunks_235 = bits(alloc_way_r_metas, 235, 235) node alloc_way_chunks_236 = bits(alloc_way_r_metas, 236, 236) node alloc_way_chunks_237 = bits(alloc_way_r_metas, 237, 237) node alloc_way_chunks_238 = bits(alloc_way_r_metas, 238, 238) node alloc_way_chunks_239 = bits(alloc_way_r_metas, 239, 239) node alloc_way_chunks_240 = bits(alloc_way_r_metas, 240, 240) node alloc_way_chunks_241 = bits(alloc_way_r_metas, 241, 241) node alloc_way_chunks_242 = bits(alloc_way_r_metas, 242, 242) node alloc_way_chunks_243 = bits(alloc_way_r_metas, 243, 243) node alloc_way_chunks_244 = bits(alloc_way_r_metas, 244, 244) node alloc_way_chunks_245 = bits(alloc_way_r_metas, 245, 245) node alloc_way_chunks_246 = bits(alloc_way_r_metas, 246, 246) node alloc_way_chunks_247 = bits(alloc_way_r_metas, 247, 247) node alloc_way_chunks_248 = bits(alloc_way_r_metas, 248, 248) node alloc_way_chunks_249 = bits(alloc_way_r_metas, 249, 249) node alloc_way_chunks_250 = bits(alloc_way_r_metas, 250, 250) node alloc_way_chunks_251 = bits(alloc_way_r_metas, 251, 251) node alloc_way_chunks_252 = bits(alloc_way_r_metas, 252, 252) node alloc_way_chunks_253 = bits(alloc_way_r_metas, 253, 253) node alloc_way_chunks_254 = bits(alloc_way_r_metas, 254, 254) node alloc_way_chunks_255 = bits(alloc_way_r_metas, 255, 255) node alloc_way_chunks_256 = bits(alloc_way_r_metas, 256, 256) node alloc_way_chunks_257 = bits(alloc_way_r_metas, 257, 257) node alloc_way_chunks_258 = bits(alloc_way_r_metas, 258, 258) node alloc_way_chunks_259 = bits(alloc_way_r_metas, 259, 259) node alloc_way_chunks_260 = bits(alloc_way_r_metas, 260, 260) node alloc_way_chunks_261 = bits(alloc_way_r_metas, 261, 261) node alloc_way_chunks_262 = bits(alloc_way_r_metas, 262, 262) node alloc_way_chunks_263 = bits(alloc_way_r_metas, 263, 263) node alloc_way_chunks_264 = bits(alloc_way_r_metas, 264, 264) node alloc_way_chunks_265 = bits(alloc_way_r_metas, 265, 265) node alloc_way_chunks_266 = bits(alloc_way_r_metas, 266, 266) node alloc_way_chunks_267 = bits(alloc_way_r_metas, 267, 267) node alloc_way_chunks_268 = bits(alloc_way_r_metas, 268, 268) node alloc_way_chunks_269 = bits(alloc_way_r_metas, 269, 269) node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1) node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2) node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3) node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4) node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5) node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6) node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7) node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8) node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9) node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10) node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11) node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12) node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13) node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14) node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15) node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16) node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17) node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18) node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19) node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20) node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21) node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22) node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23) node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24) node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25) node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26) node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27) node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28) node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29) node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30) node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31) node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32) node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33) node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34) node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35) node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36) node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37) node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38) node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39) node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40) node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41) node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42) node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43) node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44) node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45) node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46) node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47) node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48) node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49) node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50) node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51) node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52) node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53) node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54) node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55) node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56) node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57) node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58) node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59) node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60) node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61) node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62) node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63) node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64) node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65) node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66) node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67) node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68) node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69) node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70) node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71) node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72) node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73) node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74) node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75) node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76) node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77) node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78) node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79) node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80) node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81) node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82) node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83) node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84) node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85) node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86) node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87) node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88) node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89) node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90) node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91) node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92) node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93) node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94) node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95) node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96) node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97) node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98) node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99) node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100) node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101) node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102) node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103) node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104) node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105) node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106) node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107) node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108) node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109) node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110) node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111) node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112) node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113) node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114) node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115) node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116) node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117) node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118) node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119) node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120) node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121) node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122) node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123) node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124) node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125) node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126) node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127) node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128) node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129) node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130) node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131) node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132) node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133) node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134) node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135) node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136) node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137) node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138) node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139) node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140) node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141) node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142) node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143) node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144) node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145) node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146) node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147) node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148) node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149) node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150) node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151) node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152) node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153) node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154) node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155) node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156) node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157) node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158) node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159) node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160) node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161) node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162) node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163) node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164) node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165) node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166) node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167) node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168) node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169) node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170) node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171) node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172) node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173) node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174) node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175) node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176) node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177) node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178) node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179) node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180) node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181) node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182) node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183) node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184) node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185) node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186) node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187) node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188) node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189) node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190) node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191) node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192) node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193) node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194) node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195) node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196) node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197) node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198) node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199) node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200) node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201) node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202) node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203) node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204) node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205) node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206) node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207) node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208) node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209) node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210) node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211) node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212) node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213) node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214) node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215) node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216) node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217) node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218) node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219) node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220) node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221) node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222) node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223) node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224) node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225) node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226) node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227) node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228) node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229) node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230) node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231) node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232) node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233) node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234) node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235) node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236) node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237) node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238) node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239) node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240) node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241) node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242) node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243) node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244) node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245) node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246) node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247) node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248) node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249) node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250) node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251) node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252) node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253) node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254) node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255) node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256) node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257) node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258) node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259) node _alloc_way_T_259 = xor(_alloc_way_T_258, alloc_way_chunks_260) node _alloc_way_T_260 = xor(_alloc_way_T_259, alloc_way_chunks_261) node _alloc_way_T_261 = xor(_alloc_way_T_260, alloc_way_chunks_262) node _alloc_way_T_262 = xor(_alloc_way_T_261, alloc_way_chunks_263) node _alloc_way_T_263 = xor(_alloc_way_T_262, alloc_way_chunks_264) node _alloc_way_T_264 = xor(_alloc_way_T_263, alloc_way_chunks_265) node _alloc_way_T_265 = xor(_alloc_way_T_264, alloc_way_chunks_266) node _alloc_way_T_266 = xor(_alloc_way_T_265, alloc_way_chunks_267) node _alloc_way_T_267 = xor(_alloc_way_T_266, alloc_way_chunks_268) node alloc_way = xor(_alloc_way_T_267, alloc_way_chunks_269) node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1) node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2) node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3) node _s1_meta_write_way_T_3 = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0]) node _s1_meta_write_way_T_4 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0]) node _s1_meta_write_way_T_5 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0]) node _s1_meta_write_way_T_6 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0]) node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4) node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5) node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6) node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0) node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1) node _s1_meta_write_way_T_12 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), UInt<1>(0h1)) node _s1_meta_write_way_T_13 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_12, alloc_way) connect s1_meta.write_way, _s1_meta_write_way_T_13 wire s1_update_meta : { write_way : UInt<1>} wire _s1_update_meta_WIRE : UInt<1> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 0, 0) connect s1_update_meta.write_way, _s1_update_meta_T node _max_offset_value_T = not(UInt<12>(0h0)) node _max_offset_value_T_1 = cat(UInt<1>(0h0), _max_offset_value_T) node max_offset_value = asSInt(_max_offset_value_T_1) node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0)) node min_offset_value = asSInt(_min_offset_value_T) node _new_offset_value_T = asSInt(s1_update.bits.target) node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1) node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1) node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1) node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3) node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4) node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1) node new_offset_value = asSInt(_new_offset_value_T_6) node _offset_is_extended_T = gt(new_offset_value, max_offset_value) node _offset_is_extended_T_1 = lt(new_offset_value, min_offset_value) node offset_is_extended = or(_offset_is_extended_T, _offset_is_extended_T_1) wire s1_update_wbtb_data : { offset : SInt<13>, extended : UInt<1>} connect s1_update_wbtb_data.extended, offset_is_extended connect s1_update_wbtb_data.offset, new_offset_value node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid) node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken) node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4) node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0)) node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6) node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8) node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask) node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2) node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0)) node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4) node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_7 = mux(s1_update.valid, UInt<4>(0hf), UInt<4>(0h0)) node _s1_update_wmeta_mask_T_8 = and(_s1_update_wmeta_mask_T_7, s1_update.bits.btb_mispredicts) node _s1_update_wmeta_mask_T_9 = or(_s1_update_wmeta_mask_T_6, _s1_update_wmeta_mask_T_8) node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_9) wire s1_update_wmeta_data : { is_br : UInt<1>, tag : UInt<30>}[4] node _s1_update_wmeta_data_0_tag_T = bits(s1_update.bits.btb_mispredicts, 0, 0) node _s1_update_wmeta_data_0_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_0_tag_T_2 = mux(_s1_update_wmeta_data_0_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_0_tag_T_1) connect s1_update_wmeta_data[0].tag, _s1_update_wmeta_data_0_tag_T_2 node _s1_update_wmeta_data_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0) connect s1_update_wmeta_data[0].is_br, _s1_update_wmeta_data_0_is_br_T node _s1_update_wmeta_data_1_tag_T = bits(s1_update.bits.btb_mispredicts, 1, 1) node _s1_update_wmeta_data_1_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_1_tag_T_2 = mux(_s1_update_wmeta_data_1_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_1_tag_T_1) connect s1_update_wmeta_data[1].tag, _s1_update_wmeta_data_1_tag_T_2 node _s1_update_wmeta_data_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1) connect s1_update_wmeta_data[1].is_br, _s1_update_wmeta_data_1_is_br_T node _s1_update_wmeta_data_2_tag_T = bits(s1_update.bits.btb_mispredicts, 2, 2) node _s1_update_wmeta_data_2_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_2_tag_T_2 = mux(_s1_update_wmeta_data_2_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_2_tag_T_1) connect s1_update_wmeta_data[2].tag, _s1_update_wmeta_data_2_tag_T_2 node _s1_update_wmeta_data_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2) connect s1_update_wmeta_data[2].is_br, _s1_update_wmeta_data_2_is_br_T node _s1_update_wmeta_data_3_tag_T = bits(s1_update.bits.btb_mispredicts, 3, 3) node _s1_update_wmeta_data_3_tag_T_1 = shr(s1_update_idx, 7) node _s1_update_wmeta_data_3_tag_T_2 = mux(_s1_update_wmeta_data_3_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_3_tag_T_1) connect s1_update_wmeta_data[3].tag, _s1_update_wmeta_data_3_tag_T_2 node _s1_update_wmeta_data_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3) connect s1_update_wmeta_data[3].is_br, _s1_update_wmeta_data_3_is_br_T smem btb_meta_way_0 : UInt<31>[4] [128] smem btb_data_way_0 : UInt<14>[4] [128] wire _WIRE : UInt<37> invalidate _WIRE when io.f0_valid : connect _WIRE, s0_idx node _T_1 = bits(_WIRE, 6, 0) read mport MPORT = btb_meta_way_0[_T_1], clock wire _WIRE_1 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_2 : UInt<31> connect _WIRE_2, MPORT[0] node _T_2 = bits(_WIRE_2, 29, 0) connect _WIRE_1.tag, _T_2 node _T_3 = bits(_WIRE_2, 30, 30) connect _WIRE_1.is_br, _T_3 wire _WIRE_3 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_4 : UInt<31> connect _WIRE_4, MPORT[1] node _T_4 = bits(_WIRE_4, 29, 0) connect _WIRE_3.tag, _T_4 node _T_5 = bits(_WIRE_4, 30, 30) connect _WIRE_3.is_br, _T_5 wire _WIRE_5 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_6 : UInt<31> connect _WIRE_6, MPORT[2] node _T_6 = bits(_WIRE_6, 29, 0) connect _WIRE_5.tag, _T_6 node _T_7 = bits(_WIRE_6, 30, 30) connect _WIRE_5.is_br, _T_7 wire _WIRE_7 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_8 : UInt<31> connect _WIRE_8, MPORT[3] node _T_8 = bits(_WIRE_8, 29, 0) connect _WIRE_7.tag, _T_8 node _T_9 = bits(_WIRE_8, 30, 30) connect _WIRE_7.is_br, _T_9 wire _WIRE_9 : { is_br : UInt<1>, tag : UInt<30>}[4] connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].is_br, _WIRE_1.is_br connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].is_br, _WIRE_3.is_br connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].is_br, _WIRE_5.is_br connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].is_br, _WIRE_7.is_br connect s1_req_rmeta[0], _WIRE_9 wire _WIRE_10 : UInt<37> invalidate _WIRE_10 when io.f0_valid : connect _WIRE_10, s0_idx node _T_10 = bits(_WIRE_10, 6, 0) read mport MPORT_1 = btb_data_way_0[_T_10], clock wire _WIRE_11 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_12 : UInt<14> connect _WIRE_12, MPORT_1[0] node _T_11 = bits(_WIRE_12, 0, 0) connect _WIRE_11.extended, _T_11 node _T_12 = bits(_WIRE_12, 13, 1) node _T_13 = asSInt(_T_12) connect _WIRE_11.offset, _T_13 wire _WIRE_13 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_14 : UInt<14> connect _WIRE_14, MPORT_1[1] node _T_14 = bits(_WIRE_14, 0, 0) connect _WIRE_13.extended, _T_14 node _T_15 = bits(_WIRE_14, 13, 1) node _T_16 = asSInt(_T_15) connect _WIRE_13.offset, _T_16 wire _WIRE_15 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_16 : UInt<14> connect _WIRE_16, MPORT_1[2] node _T_17 = bits(_WIRE_16, 0, 0) connect _WIRE_15.extended, _T_17 node _T_18 = bits(_WIRE_16, 13, 1) node _T_19 = asSInt(_T_18) connect _WIRE_15.offset, _T_19 wire _WIRE_17 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_18 : UInt<14> connect _WIRE_18, MPORT_1[3] node _T_20 = bits(_WIRE_18, 0, 0) connect _WIRE_17.extended, _T_20 node _T_21 = bits(_WIRE_18, 13, 1) node _T_22 = asSInt(_T_21) connect _WIRE_17.offset, _T_22 wire _WIRE_19 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_19[0].extended, _WIRE_11.extended connect _WIRE_19[0].offset, _WIRE_11.offset connect _WIRE_19[1].extended, _WIRE_13.extended connect _WIRE_19[1].offset, _WIRE_13.offset connect _WIRE_19[2].extended, _WIRE_15.extended connect _WIRE_19[2].offset, _WIRE_15.offset connect _WIRE_19[3].extended, _WIRE_17.extended connect _WIRE_19[3].offset, _WIRE_17.offset connect s1_req_rbtb[0], _WIRE_19 node _T_23 = eq(s1_update_meta.write_way, UInt<1>(0h0)) node _T_24 = or(doing_reset, _T_23) node _T_25 = or(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_20 : UInt<14>[4] connect _WIRE_20[0], UInt<14>(0h0) connect _WIRE_20[1], UInt<14>(0h0) connect _WIRE_20[2], UInt<14>(0h0) connect _WIRE_20[3], UInt<14>(0h0) node _T_27 = asUInt(s1_update_wbtb_data.offset) node _T_28 = cat(_T_27, s1_update_wbtb_data.extended) node _T_29 = asUInt(s1_update_wbtb_data.offset) node _T_30 = cat(_T_29, s1_update_wbtb_data.extended) node _T_31 = asUInt(s1_update_wbtb_data.offset) node _T_32 = cat(_T_31, s1_update_wbtb_data.extended) node _T_33 = asUInt(s1_update_wbtb_data.offset) node _T_34 = cat(_T_33, s1_update_wbtb_data.extended) wire _WIRE_21 : UInt<14>[4] connect _WIRE_21[0], _T_28 connect _WIRE_21[1], _T_30 connect _WIRE_21[2], _T_32 connect _WIRE_21[3], _T_34 node _T_35 = mux(doing_reset, _WIRE_20, _WIRE_21) node _T_36 = not(UInt<4>(0h0)) node _T_37 = mux(doing_reset, _T_36, s1_update_wbtb_mask) node _T_38 = bits(_T_37, 0, 0) node _T_39 = bits(_T_37, 1, 1) node _T_40 = bits(_T_37, 2, 2) node _T_41 = bits(_T_37, 3, 3) node _T_42 = or(_T_26, UInt<7>(0h0)) node _T_43 = bits(_T_42, 6, 0) write mport MPORT_2 = btb_data_way_0[_T_43], clock when _T_38 : connect MPORT_2[0], _T_35[0] when _T_39 : connect MPORT_2[1], _T_35[1] when _T_40 : connect MPORT_2[2], _T_35[2] when _T_41 : connect MPORT_2[3], _T_35[3] node _T_44 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_22 : UInt<31>[4] connect _WIRE_22[0], UInt<31>(0h0) connect _WIRE_22[1], UInt<31>(0h0) connect _WIRE_22[2], UInt<31>(0h0) connect _WIRE_22[3], UInt<31>(0h0) node _T_45 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_46 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_47 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_48 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_23 : UInt<31>[4] connect _WIRE_23[0], _T_45 connect _WIRE_23[1], _T_46 connect _WIRE_23[2], _T_47 connect _WIRE_23[3], _T_48 node _T_49 = mux(doing_reset, _WIRE_22, _WIRE_23) node _T_50 = not(UInt<4>(0h0)) node _T_51 = mux(doing_reset, _T_50, s1_update_wmeta_mask) node _T_52 = bits(_T_51, 0, 0) node _T_53 = bits(_T_51, 1, 1) node _T_54 = bits(_T_51, 2, 2) node _T_55 = bits(_T_51, 3, 3) node _T_56 = or(_T_44, UInt<7>(0h0)) node _T_57 = bits(_T_56, 6, 0) write mport MPORT_3 = btb_meta_way_0[_T_57], clock when _T_52 : connect MPORT_3[0], _T_49[0] when _T_53 : connect MPORT_3[1], _T_49[1] when _T_54 : connect MPORT_3[2], _T_49[2] when _T_55 : connect MPORT_3[3], _T_49[3] smem btb_meta_way_1 : UInt<31>[4] [128] smem btb_data_way_1 : UInt<14>[4] [128] wire _WIRE_24 : UInt<37> invalidate _WIRE_24 when io.f0_valid : connect _WIRE_24, s0_idx node _T_58 = bits(_WIRE_24, 6, 0) read mport MPORT_4 = btb_meta_way_1[_T_58], clock wire _WIRE_25 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_26 : UInt<31> connect _WIRE_26, MPORT_4[0] node _T_59 = bits(_WIRE_26, 29, 0) connect _WIRE_25.tag, _T_59 node _T_60 = bits(_WIRE_26, 30, 30) connect _WIRE_25.is_br, _T_60 wire _WIRE_27 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_28 : UInt<31> connect _WIRE_28, MPORT_4[1] node _T_61 = bits(_WIRE_28, 29, 0) connect _WIRE_27.tag, _T_61 node _T_62 = bits(_WIRE_28, 30, 30) connect _WIRE_27.is_br, _T_62 wire _WIRE_29 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_30 : UInt<31> connect _WIRE_30, MPORT_4[2] node _T_63 = bits(_WIRE_30, 29, 0) connect _WIRE_29.tag, _T_63 node _T_64 = bits(_WIRE_30, 30, 30) connect _WIRE_29.is_br, _T_64 wire _WIRE_31 : { is_br : UInt<1>, tag : UInt<30>} wire _WIRE_32 : UInt<31> connect _WIRE_32, MPORT_4[3] node _T_65 = bits(_WIRE_32, 29, 0) connect _WIRE_31.tag, _T_65 node _T_66 = bits(_WIRE_32, 30, 30) connect _WIRE_31.is_br, _T_66 wire _WIRE_33 : { is_br : UInt<1>, tag : UInt<30>}[4] connect _WIRE_33[0].tag, _WIRE_25.tag connect _WIRE_33[0].is_br, _WIRE_25.is_br connect _WIRE_33[1].tag, _WIRE_27.tag connect _WIRE_33[1].is_br, _WIRE_27.is_br connect _WIRE_33[2].tag, _WIRE_29.tag connect _WIRE_33[2].is_br, _WIRE_29.is_br connect _WIRE_33[3].tag, _WIRE_31.tag connect _WIRE_33[3].is_br, _WIRE_31.is_br connect s1_req_rmeta[1], _WIRE_33 wire _WIRE_34 : UInt<37> invalidate _WIRE_34 when io.f0_valid : connect _WIRE_34, s0_idx node _T_67 = bits(_WIRE_34, 6, 0) read mport MPORT_5 = btb_data_way_1[_T_67], clock wire _WIRE_35 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_36 : UInt<14> connect _WIRE_36, MPORT_5[0] node _T_68 = bits(_WIRE_36, 0, 0) connect _WIRE_35.extended, _T_68 node _T_69 = bits(_WIRE_36, 13, 1) node _T_70 = asSInt(_T_69) connect _WIRE_35.offset, _T_70 wire _WIRE_37 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_38 : UInt<14> connect _WIRE_38, MPORT_5[1] node _T_71 = bits(_WIRE_38, 0, 0) connect _WIRE_37.extended, _T_71 node _T_72 = bits(_WIRE_38, 13, 1) node _T_73 = asSInt(_T_72) connect _WIRE_37.offset, _T_73 wire _WIRE_39 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_40 : UInt<14> connect _WIRE_40, MPORT_5[2] node _T_74 = bits(_WIRE_40, 0, 0) connect _WIRE_39.extended, _T_74 node _T_75 = bits(_WIRE_40, 13, 1) node _T_76 = asSInt(_T_75) connect _WIRE_39.offset, _T_76 wire _WIRE_41 : { offset : SInt<13>, extended : UInt<1>} wire _WIRE_42 : UInt<14> connect _WIRE_42, MPORT_5[3] node _T_77 = bits(_WIRE_42, 0, 0) connect _WIRE_41.extended, _T_77 node _T_78 = bits(_WIRE_42, 13, 1) node _T_79 = asSInt(_T_78) connect _WIRE_41.offset, _T_79 wire _WIRE_43 : { offset : SInt<13>, extended : UInt<1>}[4] connect _WIRE_43[0].extended, _WIRE_35.extended connect _WIRE_43[0].offset, _WIRE_35.offset connect _WIRE_43[1].extended, _WIRE_37.extended connect _WIRE_43[1].offset, _WIRE_37.offset connect _WIRE_43[2].extended, _WIRE_39.extended connect _WIRE_43[2].offset, _WIRE_39.offset connect _WIRE_43[3].extended, _WIRE_41.extended connect _WIRE_43[3].offset, _WIRE_41.offset connect s1_req_rbtb[1], _WIRE_43 node _T_80 = eq(s1_update_meta.write_way, UInt<1>(0h1)) node _T_81 = or(doing_reset, _T_80) node _T_82 = or(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_44 : UInt<14>[4] connect _WIRE_44[0], UInt<14>(0h0) connect _WIRE_44[1], UInt<14>(0h0) connect _WIRE_44[2], UInt<14>(0h0) connect _WIRE_44[3], UInt<14>(0h0) node _T_84 = asUInt(s1_update_wbtb_data.offset) node _T_85 = cat(_T_84, s1_update_wbtb_data.extended) node _T_86 = asUInt(s1_update_wbtb_data.offset) node _T_87 = cat(_T_86, s1_update_wbtb_data.extended) node _T_88 = asUInt(s1_update_wbtb_data.offset) node _T_89 = cat(_T_88, s1_update_wbtb_data.extended) node _T_90 = asUInt(s1_update_wbtb_data.offset) node _T_91 = cat(_T_90, s1_update_wbtb_data.extended) wire _WIRE_45 : UInt<14>[4] connect _WIRE_45[0], _T_85 connect _WIRE_45[1], _T_87 connect _WIRE_45[2], _T_89 connect _WIRE_45[3], _T_91 node _T_92 = mux(doing_reset, _WIRE_44, _WIRE_45) node _T_93 = not(UInt<4>(0h0)) node _T_94 = mux(doing_reset, _T_93, s1_update_wbtb_mask) node _T_95 = bits(_T_94, 0, 0) node _T_96 = bits(_T_94, 1, 1) node _T_97 = bits(_T_94, 2, 2) node _T_98 = bits(_T_94, 3, 3) node _T_99 = or(_T_83, UInt<7>(0h0)) node _T_100 = bits(_T_99, 6, 0) write mport MPORT_6 = btb_data_way_1[_T_100], clock when _T_95 : connect MPORT_6[0], _T_92[0] when _T_96 : connect MPORT_6[1], _T_92[1] when _T_97 : connect MPORT_6[2], _T_92[2] when _T_98 : connect MPORT_6[3], _T_92[3] node _T_101 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE_46 : UInt<31>[4] connect _WIRE_46[0], UInt<31>(0h0) connect _WIRE_46[1], UInt<31>(0h0) connect _WIRE_46[2], UInt<31>(0h0) connect _WIRE_46[3], UInt<31>(0h0) node _T_102 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag) node _T_103 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag) node _T_104 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag) node _T_105 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag) wire _WIRE_47 : UInt<31>[4] connect _WIRE_47[0], _T_102 connect _WIRE_47[1], _T_103 connect _WIRE_47[2], _T_104 connect _WIRE_47[3], _T_105 node _T_106 = mux(doing_reset, _WIRE_46, _WIRE_47) node _T_107 = not(UInt<4>(0h0)) node _T_108 = mux(doing_reset, _T_107, s1_update_wmeta_mask) node _T_109 = bits(_T_108, 0, 0) node _T_110 = bits(_T_108, 1, 1) node _T_111 = bits(_T_108, 2, 2) node _T_112 = bits(_T_108, 3, 3) node _T_113 = or(_T_101, UInt<7>(0h0)) node _T_114 = bits(_T_113, 6, 0) write mport MPORT_7 = btb_meta_way_1[_T_114], clock when _T_109 : connect MPORT_7[0], _T_106[0] when _T_110 : connect MPORT_7[1], _T_106[1] when _T_111 : connect MPORT_7[2], _T_106[2] when _T_112 : connect MPORT_7[3], _T_106[3] smem btb_ebtb : UInt<40> [128] wire _s1_req_rebtb_WIRE : UInt<37> invalidate _s1_req_rebtb_WIRE when io.f0_valid : connect _s1_req_rebtb_WIRE, s0_idx node _s1_req_rebtb_T = bits(_s1_req_rebtb_WIRE, 6, 0) read mport s1_req_rebtb_MPORT = btb_ebtb[_s1_req_rebtb_T], clock connect s1_req_rebtb, s1_req_rebtb_MPORT node _T_115 = neq(s1_update_wbtb_mask, UInt<1>(0h0)) node _T_116 = and(_T_115, offset_is_extended) when _T_116 : node _T_117 = or(s1_update_idx, UInt<7>(0h0)) node _T_118 = bits(_T_117, 6, 0) write mport MPORT_8 = btb_ebtb[_T_118], clock connect MPORT_8, s1_update.bits.target
module BTBBranchPredictorBank( // @[btb.scala:24:7] input clock, // @[btb.scala:24:7] input reset, // @[btb.scala:24:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [30:0] btb_meta_way_1_MPORT_7_data_3; // @[btb.scala:207:14] wire [30:0] btb_meta_way_1_MPORT_7_data_2; // @[btb.scala:207:14] wire [30:0] btb_meta_way_1_MPORT_7_data_1; // @[btb.scala:207:14] wire [30:0] btb_meta_way_1_MPORT_7_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_1_MPORT_6_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_1_MPORT_6_data_0; // @[btb.scala:201:14] wire [30:0] btb_meta_way_0_MPORT_3_data_3; // @[btb.scala:207:14] wire [30:0] btb_meta_way_0_MPORT_3_data_2; // @[btb.scala:207:14] wire [30:0] btb_meta_way_0_MPORT_3_data_1; // @[btb.scala:207:14] wire [30:0] btb_meta_way_0_MPORT_3_data_0; // @[btb.scala:207:14] wire [13:0] btb_data_way_0_MPORT_2_data_3; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_2; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_1; // @[btb.scala:201:14] wire [13:0] btb_data_way_0_MPORT_2_data_0; // @[btb.scala:201:14] wire _s1_update_meta_WIRE; // @[btb.scala:139:55] wire s1_req_rbtb_1_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_1_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_1_0_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_3_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_3_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_2_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_2_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_1_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_1_offset; // @[btb.scala:71:26] wire s1_req_rbtb_0_0_extended; // @[btb.scala:71:26] wire [12:0] s1_req_rbtb_0_0_offset; // @[btb.scala:71:26] wire [29:0] s1_req_rmeta_1_3_tag; // @[btb.scala:70:26] wire [29:0] s1_req_rmeta_1_2_tag; // @[btb.scala:70:26] wire [29:0] s1_req_rmeta_1_1_tag; // @[btb.scala:70:26] wire [29:0] s1_req_rmeta_1_0_tag; // @[btb.scala:70:26] wire [29:0] s1_req_rmeta_0_3_tag; // @[btb.scala:70:26] wire [29:0] s1_req_rmeta_0_2_tag; // @[btb.scala:70:26] wire [29:0] s1_req_rmeta_0_1_tag; // @[btb.scala:70:26] wire [29:0] s1_req_rmeta_0_0_tag; // @[btb.scala:70:26] wire [55:0] _btb_data_way_1_R0_data; // @[btb.scala:192:29] wire [123:0] _btb_meta_way_1_R0_data; // @[btb.scala:191:29] wire [55:0] _btb_data_way_0_R0_data; // @[btb.scala:192:29] wire [123:0] _btb_meta_way_0_R0_data; // @[btb.scala:191:29] wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:24:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:24:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:24:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:24:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:24:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:24:7] wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:24:7] wire io_update_valid_0 = io_update_valid; // @[btb.scala:24:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:24:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:24:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:24:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:24:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:24:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:24:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:24:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:24:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:24:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:24:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:24:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:24:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:24:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:24:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:24:7] wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:141:35] wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:141:{29,59}] wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:141:59] wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:142:{29,59}] wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:142:59] wire io_f1_lhist = 1'h0; // @[btb.scala:24:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_0_taken_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_1_taken_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_2_taken_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f2_3_taken_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_0_taken_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_1_taken_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_2_taken_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] wire io_resp_f3_3_taken_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_br_0; // @[btb.scala:24:7] wire io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] wire [119:0] io_f3_meta_0; // @[btb.scala:24:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:149:35] wire [36:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:149:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] wire [39:0] _s0_pc_T = ~io_f0_pc_0; // @[frontend.scala:147:33] wire [39:0] _s0_pc_T_1 = {_s0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] s0_pc = ~_s0_pc_T_1; // @[frontend.scala:147:{31,39}] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_0_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_1_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_2_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_0_3_T = s1_pc; // @[predictor.scala:178:22] wire [39:0] _s1_targs_1_3_T = s1_pc; // @[predictor.scala:178:22] reg [39:0] s2_pc; // @[predictor.scala:179:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:149:35] reg s1_update_valid; // @[predictor.scala:185:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:185:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:185:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:185:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:185:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:185:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:185:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:185:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:185:30] reg s1_update_bits_lhist; // @[predictor.scala:185:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:185:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:185:30] wire [39:0] _s1_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _s1_update_bits_pc_T_1 = {_s1_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _s1_update_bits_pc_T_2 = ~_s1_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] reg [36:0] s1_update_idx; // @[predictor.scala:187:30] reg s1_update_valid_0; // @[predictor.scala:188:32] wire _s1_meta_write_way_T_13; // @[btb.scala:134:27] wire s1_meta_write_way; // @[btb.scala:53:21] reg f3_meta_REG_write_way; // @[btb.scala:54:32] reg f3_meta_write_way; // @[btb.scala:54:24] assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:24:7, :54:24, :57:14] reg doing_reset; // @[btb.scala:61:28] reg [6:0] reset_idx; // @[btb.scala:62:28] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:61:28, :62:28, :63:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:63:26] wire [29:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:70:26, :124:62] wire [29:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:70:26, :124:62] wire [29:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:70:26, :124:62] wire [29:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:70:26, :124:62] wire [29:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:70:26, :124:62] wire [29:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:70:26, :124:62] wire [29:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_0_is_br; // @[btb.scala:70:26] wire [29:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:70:26, :124:62] wire s1_req_rmeta_0_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_0_3_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_0_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_1_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_2_is_br; // @[btb.scala:70:26] wire s1_req_rmeta_1_3_is_br; // @[btb.scala:70:26] wire [12:0] entry_btb_offset = s1_req_rbtb_0_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_extended = s1_req_rbtb_0_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_2_offset = s1_req_rbtb_0_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_2_extended = s1_req_rbtb_0_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_4_offset = s1_req_rbtb_0_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_4_extended = s1_req_rbtb_0_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_6_offset = s1_req_rbtb_0_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_6_extended = s1_req_rbtb_0_3_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_1_offset = s1_req_rbtb_1_0_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_1_extended = s1_req_rbtb_1_0_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_3_offset = s1_req_rbtb_1_1_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_3_extended = s1_req_rbtb_1_1_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_5_offset = s1_req_rbtb_1_2_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_5_extended = s1_req_rbtb_1_2_extended; // @[btb.scala:71:26, :90:31] wire [12:0] entry_btb_7_offset = s1_req_rbtb_1_3_offset; // @[btb.scala:71:26, :90:31] wire entry_btb_7_extended = s1_req_rbtb_1_3_extended; // @[btb.scala:71:26, :90:31] wire [39:0] s1_req_rebtb; // @[btb.scala:72:26] wire [29:0] s1_req_tag = s1_idx[36:7]; // @[predictor.scala:163:29] wire [29:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:74:29, :82:44] wire [29:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:74:29, :124:98] wire _s1_resp_0_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_1_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_2_valid_T_2; // @[btb.scala:97:50] wire _s1_resp_3_valid_T_2; // @[btb.scala:97:50] wire s1_resp_0_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_0_bits; // @[btb.scala:76:23] wire s1_resp_1_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_1_bits; // @[btb.scala:76:23] wire s1_resp_2_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_2_bits; // @[btb.scala:76:23] wire s1_resp_3_valid; // @[btb.scala:76:23] wire [39:0] s1_resp_3_bits; // @[btb.scala:76:23] wire _s1_is_br_0_T_2; // @[btb.scala:99:54] wire _s1_is_br_1_T_2; // @[btb.scala:99:54] wire _s1_is_br_2_T_2; // @[btb.scala:99:54] wire _s1_is_br_3_T_2; // @[btb.scala:99:54] wire s1_is_br_0; // @[btb.scala:77:23] wire s1_is_br_1; // @[btb.scala:77:23] wire s1_is_br_2; // @[btb.scala:77:23] wire s1_is_br_3; // @[btb.scala:77:23] wire _s1_is_jal_0_T_3; // @[btb.scala:100:54] wire _s1_is_jal_1_T_3; // @[btb.scala:100:54] wire _s1_is_jal_2_T_3; // @[btb.scala:100:54] wire _s1_is_jal_3_T_3; // @[btb.scala:100:54] wire s1_is_jal_0; // @[btb.scala:78:23] wire s1_is_jal_1; // @[btb.scala:78:23] wire s1_is_jal_2; // @[btb.scala:78:23] wire s1_is_jal_3; // @[btb.scala:78:23] wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:80:27, :81:12] wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:81:12, :82:30] wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:70:26, :82:{30,44}] wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:81:12, :82:30] wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:80:27, :81:12] wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:80:27, :81:12] wire s1_hits_0 = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[btb.scala:80:27, :85:55] wire s1_hits_1 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[btb.scala:80:27, :85:55] wire s1_hits_2 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[btb.scala:80:27, :85:55] wire s1_hits_3 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[btb.scala:80:27, :85:55] wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70] wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70] wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70] wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70] wire [39:0] _s1_targs_0_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_0_3_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_0_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_1_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_2_T_8; // @[btb.scala:91:28] wire [39:0] _s1_targs_1_3_T_8; // @[btb.scala:91:28] wire [39:0] s1_targs_0_0; // @[btb.scala:87:25] wire [39:0] s1_targs_0_1; // @[btb.scala:87:25] wire [39:0] s1_targs_0_2; // @[btb.scala:87:25] wire [39:0] s1_targs_0_3; // @[btb.scala:87:25] wire [39:0] s1_targs_1_0; // @[btb.scala:87:25] wire [39:0] s1_targs_1_1; // @[btb.scala:87:25] wire [39:0] s1_targs_1_2; // @[btb.scala:87:25] wire [39:0] s1_targs_1_3; // @[btb.scala:87:25] wire [40:0] _s1_targs_0_0_T_1 = {_s1_targs_0_0_T[39], _s1_targs_0_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_0_T_2 = _s1_targs_0_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_0_T_3 = _s1_targs_0_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_0_T_4 = {_s1_targs_0_0_T_3[39], _s1_targs_0_0_T_3} + {{28{entry_btb_offset[12]}}, entry_btb_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_0_T_5 = _s1_targs_0_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_6 = _s1_targs_0_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_0_T_7 = _s1_targs_0_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_0_T_8 = entry_btb_extended ? s1_req_rebtb : _s1_targs_0_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_0 = _s1_targs_0_0_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_0_T_1 = {_s1_targs_1_0_T[39], _s1_targs_1_0_T}; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_0_T_2 = _s1_targs_1_0_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_0_T_3 = _s1_targs_1_0_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_0_T_4 = {_s1_targs_1_0_T_3[39], _s1_targs_1_0_T_3} + {{28{entry_btb_1_offset[12]}}, entry_btb_1_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_0_T_5 = _s1_targs_1_0_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_6 = _s1_targs_1_0_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_0_T_7 = _s1_targs_1_0_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_0_T_8 = entry_btb_1_extended ? s1_req_rebtb : _s1_targs_1_0_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_0 = _s1_targs_1_0_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_0_bits = s1_hit_ways_0 ? s1_targs_1_0 : s1_targs_0_0; // @[Mux.scala:50:70] wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70] assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN; // @[btb.scala:99:{34,54}] assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_0_T_2 = ~_GEN; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:78:23, :100:54] reg REG; // @[btb.scala:105:18] reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_0_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_0_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_1; // @[btb.scala:109:20] assign io_resp_f2_0_taken_0 = REG & REG_1 | io_resp_in_0_f2_0_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_2; // @[btb.scala:113:26] reg REG_3; // @[btb.scala:113:18] reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_0_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_0_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_4; // @[btb.scala:117:28] reg REG_5; // @[btb.scala:117:20] assign io_resp_f3_0_taken_0 = REG_3 & REG_5 | io_resp_in_0_f3_0_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_1_T_1 = {_s1_targs_0_1_T[39], _s1_targs_0_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_1_T_2 = _s1_targs_0_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_1_T_3 = _s1_targs_0_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_1_T_4 = {_s1_targs_0_1_T_3[39], _s1_targs_0_1_T_3} + {{28{entry_btb_2_offset[12]}}, entry_btb_2_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_1_T_5 = _s1_targs_0_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_6 = _s1_targs_0_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_1_T_7 = _s1_targs_0_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_1_T_8 = entry_btb_2_extended ? s1_req_rebtb : _s1_targs_0_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_1 = _s1_targs_0_1_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_1_T_1 = {_s1_targs_1_1_T[39], _s1_targs_1_1_T} + 41'h2; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_1_T_2 = _s1_targs_1_1_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_1_T_3 = _s1_targs_1_1_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_1_T_4 = {_s1_targs_1_1_T_3[39], _s1_targs_1_1_T_3} + {{28{entry_btb_3_offset[12]}}, entry_btb_3_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_1_T_5 = _s1_targs_1_1_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_6 = _s1_targs_1_1_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_1_T_7 = _s1_targs_1_1_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_1_T_8 = entry_btb_3_extended ? s1_req_rebtb : _s1_targs_1_1_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_1 = _s1_targs_1_1_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_1_bits = s1_hit_ways_1 ? s1_targs_1_1 : s1_targs_0_1; // @[Mux.scala:50:70] wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_0 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70] assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_0; // @[btb.scala:99:{34,54}] assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_1_T_2 = ~_GEN_0; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:78:23, :100:54] reg REG_6; // @[btb.scala:105:18] reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_1_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_1_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_7; // @[btb.scala:109:20] assign io_resp_f2_1_taken_0 = REG_6 & REG_7 | io_resp_in_0_f2_1_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_8; // @[btb.scala:113:26] reg REG_9; // @[btb.scala:113:18] reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_1_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_1_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_10; // @[btb.scala:117:28] reg REG_11; // @[btb.scala:117:20] assign io_resp_f3_1_taken_0 = REG_9 & REG_11 | io_resp_in_0_f3_1_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_2_T_1 = {_s1_targs_0_2_T[39], _s1_targs_0_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_2_T_2 = _s1_targs_0_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_2_T_3 = _s1_targs_0_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_2_T_4 = {_s1_targs_0_2_T_3[39], _s1_targs_0_2_T_3} + {{28{entry_btb_4_offset[12]}}, entry_btb_4_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_2_T_5 = _s1_targs_0_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_6 = _s1_targs_0_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_2_T_7 = _s1_targs_0_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_2_T_8 = entry_btb_4_extended ? s1_req_rebtb : _s1_targs_0_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_2 = _s1_targs_0_2_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_2_T_1 = {_s1_targs_1_2_T[39], _s1_targs_1_2_T} + 41'h4; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_2_T_2 = _s1_targs_1_2_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_2_T_3 = _s1_targs_1_2_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_2_T_4 = {_s1_targs_1_2_T_3[39], _s1_targs_1_2_T_3} + {{28{entry_btb_5_offset[12]}}, entry_btb_5_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_2_T_5 = _s1_targs_1_2_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_6 = _s1_targs_1_2_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_2_T_7 = _s1_targs_1_2_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_2_T_8 = entry_btb_5_extended ? s1_req_rebtb : _s1_targs_1_2_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_2 = _s1_targs_1_2_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_2_bits = s1_hit_ways_2 ? s1_targs_1_2 : s1_targs_0_2; // @[Mux.scala:50:70] wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_1 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70] assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_1; // @[btb.scala:99:{34,54}] assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_2_T_2 = ~_GEN_1; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:78:23, :100:54] reg REG_12; // @[btb.scala:105:18] reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_2_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_2_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_13; // @[btb.scala:109:20] assign io_resp_f2_2_taken_0 = REG_12 & REG_13 | io_resp_in_0_f2_2_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_14; // @[btb.scala:113:26] reg REG_15; // @[btb.scala:113:18] reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_2_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_2_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_16; // @[btb.scala:117:28] reg REG_17; // @[btb.scala:117:20] assign io_resp_f3_2_taken_0 = REG_15 & REG_17 | io_resp_in_0_f3_2_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [40:0] _s1_targs_0_3_T_1 = {_s1_targs_0_3_T[39], _s1_targs_0_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_0_3_T_2 = _s1_targs_0_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_0_3_T_3 = _s1_targs_0_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_0_3_T_4 = {_s1_targs_0_3_T_3[39], _s1_targs_0_3_T_3} + {{28{entry_btb_6_offset[12]}}, entry_btb_6_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_0_3_T_5 = _s1_targs_0_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_6 = _s1_targs_0_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_0_3_T_7 = _s1_targs_0_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_0_3_T_8 = entry_btb_6_extended ? s1_req_rebtb : _s1_targs_0_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_0_3 = _s1_targs_0_3_T_8; // @[btb.scala:87:25, :91:28] wire [40:0] _s1_targs_1_3_T_1 = {_s1_targs_1_3_T[39], _s1_targs_1_3_T} + 41'h6; // @[btb.scala:93:{16,23}] wire [39:0] _s1_targs_1_3_T_2 = _s1_targs_1_3_T_1[39:0]; // @[btb.scala:93:23] wire [39:0] _s1_targs_1_3_T_3 = _s1_targs_1_3_T_2; // @[btb.scala:93:23] wire [40:0] _s1_targs_1_3_T_4 = {_s1_targs_1_3_T_3[39], _s1_targs_1_3_T_3} + {{28{entry_btb_7_offset[12]}}, entry_btb_7_offset}; // @[btb.scala:90:31, :93:{23,36}] wire [39:0] _s1_targs_1_3_T_5 = _s1_targs_1_3_T_4[39:0]; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_6 = _s1_targs_1_3_T_5; // @[btb.scala:93:36] wire [39:0] _s1_targs_1_3_T_7 = _s1_targs_1_3_T_6; // @[btb.scala:93:{36,56}] assign _s1_targs_1_3_T_8 = entry_btb_7_extended ? s1_req_rebtb : _s1_targs_1_3_T_7; // @[btb.scala:72:26, :90:31, :91:28, :93:56] assign s1_targs_1_3 = _s1_targs_1_3_T_8; // @[btb.scala:87:25, :91:28] wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:61:28, :97:25] wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25] assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:85:55, :97:{38,50}] assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:76:23, :97:50] assign s1_resp_3_bits = s1_hit_ways_3 ? s1_targs_1_3 : s1_targs_0_3; // @[Mux.scala:50:70] wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :99:21] wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :99:{21,34}] wire _GEN_2 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70] assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_2; // @[btb.scala:99:{34,54}] assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:77:23, :99:54] wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:61:28, :97:25, :100:21] wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:76:23, :100:{21,34}] wire _s1_is_jal_3_T_2 = ~_GEN_2; // @[btb.scala:99:54, :100:57] assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:100:{34,54,57}] assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:78:23, :100:54] reg REG_18; // @[btb.scala:105:18] reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:106:44] reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:106:44] assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :106:{34,44}] reg io_resp_f2_3_is_br_REG; // @[btb.scala:107:44] assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :107:{34,44}] reg io_resp_f2_3_is_jal_REG; // @[btb.scala:108:44] assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :108:{34,44}] reg REG_19; // @[btb.scala:109:20] assign io_resp_f2_3_taken_0 = REG_18 & REG_19 | io_resp_in_0_f2_3_taken_0; // @[btb.scala:24:7, :103:19, :105:{18,32}, :109:{20,36}, :110:34] reg REG_20; // @[btb.scala:113:26] reg REG_21; // @[btb.scala:113:18] reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:114:44] reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:114:44] assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :114:{34,44}] reg io_resp_f3_3_is_br_REG; // @[btb.scala:115:44] assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :115:{34,44}] reg io_resp_f3_3_is_jal_REG; // @[btb.scala:116:44] assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :116:{34,44}] reg REG_22; // @[btb.scala:117:28] reg REG_23; // @[btb.scala:117:20] assign io_resp_f3_3_taken_0 = REG_21 & REG_23 | io_resp_in_0_f3_3_taken_0; // @[btb.scala:24:7, :104:19, :113:{18,41}, :117:{20,45}, :118:34] wire [29:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:124:{30,62}] wire [29:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:124:{30,62}] wire [29:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:124:{30,62}] wire [29:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:124:{30,62}] wire [29:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:124:{30,62}] wire [29:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:124:{30,62}] wire [29:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:124:{30,62}] wire [29:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:124:{30,62}] wire [59:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:124:{30,80}] wire [59:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:124:{30,80}] wire [119:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:124:80] wire [59:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:124:{30,80}] wire [59:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:124:{30,80}] wire [119:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:124:80] wire [239:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:124:80] wire [269:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:124:{22,80,98}] wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_261 = alloc_way_r_metas[261]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_262 = alloc_way_r_metas[262]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_263 = alloc_way_r_metas[263]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_264 = alloc_way_r_metas[264]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_265 = alloc_way_r_metas[265]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_266 = alloc_way_r_metas[266]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_267 = alloc_way_r_metas[267]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_268 = alloc_way_r_metas[268]; // @[btb.scala:124:22, :128:14] wire alloc_way_chunks_269 = alloc_way_r_metas[269]; // @[btb.scala:124:22, :128:14] wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_259 = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_260 = _alloc_way_T_259 ^ alloc_way_chunks_261; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_261 = _alloc_way_T_260 ^ alloc_way_chunks_262; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_262 = _alloc_way_T_261 ^ alloc_way_chunks_263; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_263 = _alloc_way_T_262 ^ alloc_way_chunks_264; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_264 = _alloc_way_T_263 ^ alloc_way_chunks_265; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_265 = _alloc_way_T_264 ^ alloc_way_chunks_266; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_266 = _alloc_way_T_265 ^ alloc_way_chunks_267; // @[btb.scala:128:14, :130:20] wire _alloc_way_T_267 = _alloc_way_T_266 ^ alloc_way_chunks_268; // @[btb.scala:128:14, :130:20] wire alloc_way = _alloc_way_T_267 ^ alloc_way_chunks_269; // @[btb.scala:128:14, :130:20] wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[btb.scala:85:55, :134:44] wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[btb.scala:85:55, :134:44] wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:80:27, :135:38] wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[btb.scala:135:{38,54}] wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[btb.scala:135:{38,54}] wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45] wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45] assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70] assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:53:21, :134:27] wire _s1_update_meta_T; // @[btb.scala:139:55] wire s1_update_meta_write_way; // @[btb.scala:139:55] assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:139:55] assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:185:30] assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:139:55] wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:185:30] wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:185:30] wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:144:24] wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:144:{24,62}] wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:143:{49,56}, :144:62] wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:143:56] wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:143:56] wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:143:56, :145:46] wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:143:56, :146:46] wire offset_is_extended = _offset_is_extended_T | _offset_is_extended_T_1; // @[btb.scala:145:{46,65}, :146:46] wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:145:65, :149:34] wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:149:34] assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:143:56, :149:34, :151:32] wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:185:30] wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:185:30] wire _GEN_3 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :185:30] wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49] assign _s1_update_wbtb_mask_T_3 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49] assign _s1_update_wmeta_mask_T_1 = _GEN_3; // @[predictor.scala:96:49] wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}] wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26] wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:153:{9,97}] wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35] wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:185:30] wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :185:30] wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}] wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}] wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :185:30] wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:156:{10,38}] wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30] wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 | _s1_update_wmeta_mask_T_8; // @[btb.scala:156:{10,74}, :157:40] wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:155:{52,78}, :156:74] wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:164:62] wire [29:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:164:62] wire [29:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:164:62] wire [29:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:163:43] wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:164:62] wire [29:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:163:43] wire s1_update_wmeta_data_0_is_br; // @[btb.scala:160:34] wire [29:0] s1_update_wmeta_data_0_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_1_is_br; // @[btb.scala:160:34] wire [29:0] s1_update_wmeta_data_1_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_2_is_br; // @[btb.scala:160:34] wire [29:0] s1_update_wmeta_data_2_tag; // @[btb.scala:160:34] wire s1_update_wmeta_data_3_is_br; // @[btb.scala:160:34] wire [29:0] s1_update_wmeta_data_3_tag; // @[btb.scala:160:34] wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:185:30] wire [29:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[36:7]; // @[predictor.scala:187:30] wire [29:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[36:7]; // @[predictor.scala:187:30] wire [29:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[36:7]; // @[predictor.scala:187:30] wire [29:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[36:7]; // @[predictor.scala:187:30] assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 30'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 30'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 30'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:160:34, :164:62] wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:185:30] assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 30'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:163:{43,74,98}] assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:160:34, :163:43] assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:185:30] assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:160:34, :164:62] assign s1_req_rmeta_0_0_tag = _btb_meta_way_0_R0_data[29:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_0_is_br = _btb_meta_way_0_R0_data[30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_tag = _btb_meta_way_0_R0_data[60:31]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_1_is_br = _btb_meta_way_0_R0_data[61]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_tag = _btb_meta_way_0_R0_data[91:62]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_2_is_br = _btb_meta_way_0_R0_data[92]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_tag = _btb_meta_way_0_R0_data[122:93]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_0_3_is_br = _btb_meta_way_0_R0_data[123]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_0_0_extended = _btb_data_way_0_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_0_offset = _btb_data_way_0_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_extended = _btb_data_way_0_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_1_offset = _btb_data_way_0_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_extended = _btb_data_way_0_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_2_offset = _btb_data_way_0_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_extended = _btb_data_way_0_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_0_3_offset = _btb_data_way_0_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_0_MPORT_2_en = doing_reset | ~s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:{25,53}] wire [6:0] _T_56 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_0_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_0_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_0_MPORT_3_data_0 = doing_reset ? 31'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_1 = doing_reset ? 31'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_2 = doing_reset ? 31'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_0_MPORT_3_data_3 = doing_reset ? 31'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign s1_req_rmeta_1_0_tag = _btb_meta_way_1_R0_data[29:0]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_0_is_br = _btb_meta_way_1_R0_data[30]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_tag = _btb_meta_way_1_R0_data[60:31]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_1_is_br = _btb_meta_way_1_R0_data[61]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_tag = _btb_meta_way_1_R0_data[91:62]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_2_is_br = _btb_meta_way_1_R0_data[92]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_tag = _btb_meta_way_1_R0_data[122:93]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rmeta_1_3_is_br = _btb_meta_way_1_R0_data[123]; // @[btb.scala:70:26, :191:29, :195:76] assign s1_req_rbtb_1_0_extended = _btb_data_way_1_R0_data[0]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_0_offset = _btb_data_way_1_R0_data[13:1]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_extended = _btb_data_way_1_R0_data[14]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_1_offset = _btb_data_way_1_R0_data[27:15]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_extended = _btb_data_way_1_R0_data[28]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_2_offset = _btb_data_way_1_R0_data[41:29]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_extended = _btb_data_way_1_R0_data[42]; // @[btb.scala:71:26, :192:29, :196:75] assign s1_req_rbtb_1_3_offset = _btb_data_way_1_R0_data[55:43]; // @[btb.scala:71:26, :192:29, :196:75] wire btb_data_way_1_MPORT_6_en = doing_reset | s1_update_meta_write_way; // @[btb.scala:61:28, :139:55, :198:25] wire [6:0] _T_113 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:187:30] assign btb_data_way_1_MPORT_6_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_data_way_1_MPORT_6_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:61:28, :149:34, :201:14, :202:78] assign btb_meta_way_1_MPORT_7_data_0 = doing_reset ? 31'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_1 = doing_reset ? 31'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_2 = doing_reset ? 31'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] assign btb_meta_way_1_MPORT_7_data_3 = doing_reset ? 31'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:61:28, :160:34, :207:14, :208:63] wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:215:30] always @(posedge clock) begin // @[btb.scala:24:7] s1_idx <= s0_idx; // @[frontend.scala:149:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= s0_pc; // @[frontend.scala:147:31] s2_pc <= s1_pc; // @[predictor.scala:178:22, :179:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:185:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:185:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:185:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:185:30] s1_update_bits_pc <= _s1_update_bits_pc_T_2; // @[frontend.scala:147:31] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:185:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:185:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:185:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:185:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:185:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:185:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:185:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:185:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:185:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:149:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:188:32] f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:53:21, :54:32] f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:54:{24,32}] REG <= s1_hits_0; // @[btb.scala:85:55, :105:18] io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:77:23, :107:44] io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:78:23, :108:44] REG_1 <= s1_is_jal_0; // @[btb.scala:78:23, :109:20] REG_2 <= s1_hits_0; // @[btb.scala:85:55, :113:26] REG_3 <= REG_2; // @[btb.scala:113:{18,26}] io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:24:7, :116:44] REG_4 <= s1_is_jal_0; // @[btb.scala:78:23, :117:28] REG_5 <= REG_4; // @[btb.scala:117:{20,28}] REG_6 <= s1_hits_1; // @[btb.scala:85:55, :105:18] io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:77:23, :107:44] io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:78:23, :108:44] REG_7 <= s1_is_jal_1; // @[btb.scala:78:23, :109:20] REG_8 <= s1_hits_1; // @[btb.scala:85:55, :113:26] REG_9 <= REG_8; // @[btb.scala:113:{18,26}] io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:24:7, :116:44] REG_10 <= s1_is_jal_1; // @[btb.scala:78:23, :117:28] REG_11 <= REG_10; // @[btb.scala:117:{20,28}] REG_12 <= s1_hits_2; // @[btb.scala:85:55, :105:18] io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:77:23, :107:44] io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:78:23, :108:44] REG_13 <= s1_is_jal_2; // @[btb.scala:78:23, :109:20] REG_14 <= s1_hits_2; // @[btb.scala:85:55, :113:26] REG_15 <= REG_14; // @[btb.scala:113:{18,26}] io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:24:7, :116:44] REG_16 <= s1_is_jal_2; // @[btb.scala:78:23, :117:28] REG_17 <= REG_16; // @[btb.scala:117:{20,28}] REG_18 <= s1_hits_3; // @[btb.scala:85:55, :105:18] io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:76:23, :106:44] io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:76:23, :106:44] io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:77:23, :107:44] io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:78:23, :108:44] REG_19 <= s1_is_jal_3; // @[btb.scala:78:23, :109:20] REG_20 <= s1_hits_3; // @[btb.scala:85:55, :113:26] REG_21 <= REG_20; // @[btb.scala:113:{18,26}] io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7, :114:44] io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:24:7, :115:44] io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:24:7, :116:44] REG_22 <= s1_is_jal_3; // @[btb.scala:78:23, :117:28] REG_23 <= REG_22; // @[btb.scala:117:{20,28}] if (reset) begin // @[btb.scala:24:7] doing_reset <= 1'h1; // @[btb.scala:61:28] reset_idx <= 7'h0; // @[btb.scala:62:28] end else begin // @[btb.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:61:28, :62:28, :64:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[btb.scala:62:28, :63:26] end always @(posedge) btb_meta_way_0 btb_meta_way_0 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_0_MPORT_3_data_3, btb_meta_way_0_MPORT_3_data_2, btb_meta_way_0_MPORT_3_data_1, btb_meta_way_0_MPORT_3_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_0 btb_data_way_0 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_0_R0_data), .W0_addr (_T_56), // @[btb.scala:200:14] .W0_en (btb_data_way_0_MPORT_2_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_0_MPORT_2_data_3, btb_data_way_0_MPORT_2_data_2, btb_data_way_0_MPORT_2_data_1, btb_data_way_0_MPORT_2_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_meta_way_1 btb_meta_way_1 ( // @[btb.scala:191:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_meta_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_meta_way_1_MPORT_7_data_3, btb_meta_way_1_MPORT_7_data_2, btb_meta_way_1_MPORT_7_data_1, btb_meta_way_1_MPORT_7_data_0}), // @[btb.scala:191:29, :207:14] .W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:61:28, :155:78, :209:14] ); // @[btb.scala:191:29] btb_data_way_1 btb_data_way_1 ( // @[btb.scala:192:29] .R0_addr (s0_idx[6:0]), // @[frontend.scala:149:35] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (_btb_data_way_1_R0_data), .W0_addr (_T_113), // @[btb.scala:200:14] .W0_en (btb_data_way_1_MPORT_6_en), // @[btb.scala:198:25] .W0_clk (clock), .W0_data ({btb_data_way_1_MPORT_6_data_3, btb_data_way_1_MPORT_6_data_2, btb_data_way_1_MPORT_6_data_1, btb_data_way_1_MPORT_6_data_0}), // @[btb.scala:192:29, :201:14] .W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:61:28, :152:58, :203:14] ); // @[btb.scala:192:29] btb_ebtb btb_ebtb ( // @[btb.scala:213:27] .R0_addr (_s1_req_rebtb_T), // @[btb.scala:215:30] .R0_en (io_f0_valid_0), // @[btb.scala:24:7] .R0_clk (clock), .R0_data (s1_req_rebtb), .W0_addr (s1_update_idx[6:0]), // @[predictor.scala:187:30] .W0_en ((|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:145:65, :152:58, :216:{31,39}] .W0_clk (clock), .W0_data (s1_update_bits_target) // @[predictor.scala:185:30] ); // @[btb.scala:213:27] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:24:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:24:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:24:7] assign io_f3_meta = io_f3_meta_0; // @[btb.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_125 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_125( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_21 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_21( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_1 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], chosen_oh : UInt<3>[1]} regreset lock_0 : UInt<3>, clock, reset, UInt<3>(0h0) node unassigned_hi = cat(io.in[2].valid, io.in[1].valid) node _unassigned_T = cat(unassigned_hi, io.in[0].valid) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire choices : UInt<3>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = mux(_sel_T_8, UInt<6>(0h20), UInt<6>(0h0)) node _sel_T_10 = mux(_sel_T_7, UInt<6>(0h10), _sel_T_9) node _sel_T_11 = mux(_sel_T_6, UInt<6>(0h8), _sel_T_10) node _sel_T_12 = mux(_sel_T_5, UInt<6>(0h4), _sel_T_11) node _sel_T_13 = mux(_sel_T_4, UInt<6>(0h2), _sel_T_12) node sel = mux(_sel_T_3, UInt<6>(0h1), _sel_T_13) node _choices_0_T = shr(sel, 3) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = mux(_T_4, UInt<3>(0h4), UInt<3>(0h0)) node _T_6 = mux(_T_3, UInt<3>(0h2), _T_5) node _T_7 = mux(_T_2, UInt<3>(0h1), _T_6) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) node in_tails_hi = cat(io.in[2].bits.tail, io.in[1].bits.tail) node in_tails = cat(in_tails_hi, io.in[0].bits.tail) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node in_valids_hi = cat(_in_valids_T_5, _in_valids_T_3) node in_valids = cat(in_valids_hi, _in_valids_T_1) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<3>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) wire _io_out_0_bits_WIRE : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>} node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_6 = or(_io_out_0_bits_T_3, _io_out_0_bits_T_4) node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_6, _io_out_0_bits_T_5) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_7 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _io_out_0_bits_WIRE_3 : UInt<1>[6] node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_10) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_12 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_13, _io_out_0_bits_T_14) node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_15) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_17 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_20) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_25) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_27 connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7 node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_28, _io_out_0_bits_T_29) node _io_out_0_bits_T_32 = or(_io_out_0_bits_T_31, _io_out_0_bits_T_30) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_32 connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8 node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_33, _io_out_0_bits_T_34) node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_35) wire _io_out_0_bits_WIRE_9 : UInt<1> connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_37 connect _io_out_0_bits_WIRE_3[5], _io_out_0_bits_WIRE_9 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_10 : UInt<1>[1] node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_41 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_39) node _io_out_0_bits_T_42 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_40) wire _io_out_0_bits_WIRE_11 : UInt<1> connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_42 connect _io_out_0_bits_WIRE_10[0], _io_out_0_bits_WIRE_11 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_10 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_8 = bits(chosen, 0, 0) node _T_9 = and(_T_8, io.out[0].ready) when _T_9 : connect io.in[0].ready, UInt<1>(0h1) node _T_10 = bits(chosen, 1, 1) node _T_11 = and(_T_10, io.out[0].ready) when _T_11 : connect io.in[1].ready, UInt<1>(0h1) node _T_12 = bits(chosen, 2, 2) node _T_13 = and(_T_12, io.out[0].ready) when _T_13 : connect io.in[2].ready, UInt<1>(0h1) node _T_14 = or(UInt<3>(0h0), chosen) node _T_15 = and(io.out[0].ready, io.out[0].valid) when _T_15 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_16 = and(io.out[0].ready, io.out[0].valid) when _T_16 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = or(_mask_T, _mask_T_1) node _mask_T_4 = or(_mask_T_3, _mask_T_2) connect mask, _mask_T_4 else : node _mask_T_5 = not(mask) node _mask_T_6 = eq(_mask_T_5, UInt<1>(0h0)) node _mask_T_7 = shl(mask, 1) node _mask_T_8 = or(_mask_T_7, UInt<1>(0h1)) node _mask_T_9 = mux(_mask_T_6, UInt<1>(0h0), _mask_T_8) connect mask, _mask_T_9
module SwitchArbiter_1( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [2:0] unassigned = {io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [2:0] mask; // @[SwitchAllocator.scala:27:21] wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_valids = {io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [2:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[2:0] | sel[5:3]; // @[Mux.scala:50:70] wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [1:0] _GEN = chosen[1:0] | chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38] mask <= 3'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (|_io_out_0_valid_T) ? {chosen[2], _GEN[1], _GEN[0] | chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_112 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], chosen_oh : UInt<3>[1]} regreset lock_0 : UInt<3>, clock, reset, UInt<3>(0h0) node unassigned_hi = cat(io.in[2].valid, io.in[1].valid) node _unassigned_T = cat(unassigned_hi, io.in[0].valid) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire choices : UInt<3>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = mux(_sel_T_8, UInt<6>(0h20), UInt<6>(0h0)) node _sel_T_10 = mux(_sel_T_7, UInt<6>(0h10), _sel_T_9) node _sel_T_11 = mux(_sel_T_6, UInt<6>(0h8), _sel_T_10) node _sel_T_12 = mux(_sel_T_5, UInt<6>(0h4), _sel_T_11) node _sel_T_13 = mux(_sel_T_4, UInt<6>(0h2), _sel_T_12) node sel = mux(_sel_T_3, UInt<6>(0h1), _sel_T_13) node _choices_0_T = shr(sel, 3) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = mux(_T_4, UInt<3>(0h4), UInt<3>(0h0)) node _T_6 = mux(_T_3, UInt<3>(0h2), _T_5) node _T_7 = mux(_T_2, UInt<3>(0h1), _T_6) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) node in_tails_hi = cat(io.in[2].bits.tail, io.in[1].bits.tail) node in_tails = cat(in_tails_hi, io.in[0].bits.tail) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node in_valids_hi = cat(_in_valids_T_5, _in_valids_T_3) node in_valids = cat(in_valids_hi, _in_valids_T_1) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<3>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) wire _io_out_0_bits_WIRE : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>} node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_6 = or(_io_out_0_bits_T_3, _io_out_0_bits_T_4) node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_6, _io_out_0_bits_T_5) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_7 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `1` : UInt<1>[1], `0` : UInt<1>[3]} wire _io_out_0_bits_WIRE_3 : UInt<1>[3] node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_10) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_12 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_13, _io_out_0_bits_T_14) node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_15) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_17 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_20) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_7 : UInt<1>[1] node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_25) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_27 connect _io_out_0_bits_WIRE_7[0], _io_out_0_bits_WIRE_8 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_7 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_8 = bits(chosen, 0, 0) node _T_9 = and(_T_8, io.out[0].ready) when _T_9 : connect io.in[0].ready, UInt<1>(0h1) node _T_10 = bits(chosen, 1, 1) node _T_11 = and(_T_10, io.out[0].ready) when _T_11 : connect io.in[1].ready, UInt<1>(0h1) node _T_12 = bits(chosen, 2, 2) node _T_13 = and(_T_12, io.out[0].ready) when _T_13 : connect io.in[2].ready, UInt<1>(0h1) node _T_14 = or(UInt<3>(0h0), chosen) node _T_15 = and(io.out[0].ready, io.out[0].valid) when _T_15 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_16 = and(io.out[0].ready, io.out[0].valid) when _T_16 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = or(_mask_T, _mask_T_1) node _mask_T_4 = or(_mask_T_3, _mask_T_2) connect mask, _mask_T_4 else : node _mask_T_5 = not(mask) node _mask_T_6 = eq(_mask_T_5, UInt<1>(0h0)) node _mask_T_7 = shl(mask, 1) node _mask_T_8 = or(_mask_T_7, UInt<1>(0h1)) node _mask_T_9 = mux(_mask_T_6, UInt<1>(0h0), _mask_T_8) connect mask, _mask_T_9
module SwitchArbiter_112( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [2:0] unassigned = {io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [2:0] mask; // @[SwitchAllocator.scala:27:21] wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_valids = {io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [2:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[2:0] | sel[5:3]; // @[Mux.scala:50:70] wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire _GEN = io_out_0_ready & (|_io_out_0_valid_T); // @[Decoupled.scala:51:35] wire [1:0] _GEN_0 = chosen[1:0] | chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38] mask <= 3'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN) // @[Decoupled.scala:51:35] lock_0 <= chosen & ~{io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN ? {chosen[2], _GEN_0[1], _GEN_0[0] | chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module ProtocolNoC_2 : input clock : Clock input reset : Reset output io : { protocol : { `0` : { in : { flip `3` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip `2` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip `1` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip `0` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}, out : { `4` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, `3` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, `2` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, `1` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, `0` : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}}}} inst noc of NoC_2 connect noc.clock, clock connect noc.reset, reset connect noc.io.router_clocks[0].clock, clock connect noc.io.router_clocks[1].clock, clock connect noc.io.router_clocks[2].clock, clock connect noc.io.router_clocks[3].clock, clock connect noc.io.router_clocks[4].clock, clock connect noc.io.router_clocks[5].clock, clock connect noc.io.router_clocks[6].clock, clock connect noc.io.router_clocks[7].clock, clock connect noc.io.router_clocks[8].clock, clock connect noc.io.router_clocks[9].clock, clock connect noc.io.router_clocks[10].clock, clock connect noc.io.router_clocks[11].clock, clock connect noc.io.router_clocks[12].clock, clock connect noc.io.router_clocks[13].clock, clock connect noc.io.router_clocks[14].clock, clock connect noc.io.router_clocks[15].clock, clock connect noc.io.router_clocks[0].reset, reset connect noc.io.router_clocks[1].reset, reset connect noc.io.router_clocks[2].reset, reset connect noc.io.router_clocks[3].reset, reset connect noc.io.router_clocks[4].reset, reset connect noc.io.router_clocks[5].reset, reset connect noc.io.router_clocks[6].reset, reset connect noc.io.router_clocks[7].reset, reset connect noc.io.router_clocks[8].reset, reset connect noc.io.router_clocks[9].reset, reset connect noc.io.router_clocks[10].reset, reset connect noc.io.router_clocks[11].reset, reset connect noc.io.router_clocks[12].reset, reset connect noc.io.router_clocks[13].reset, reset connect noc.io.router_clocks[14].reset, reset connect noc.io.router_clocks[15].reset, reset wire terminals : { ingress : { flip `21` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `20` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `19` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}}, egress : { `22` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `21` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `20` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `19` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `18` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `17` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `16` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `15` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `14` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `13` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `12` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `11` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `10` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `9` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `8` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `7` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `6` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `5` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `4` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `3` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `2` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `1` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, `0` : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}}} connect noc.io.ingress.`0`, terminals.ingress.`0` connect noc.io.ingress.`1`, terminals.ingress.`1` connect noc.io.ingress.`2`, terminals.ingress.`2` connect noc.io.ingress.`3`, terminals.ingress.`3` connect noc.io.ingress.`4`, terminals.ingress.`4` connect noc.io.ingress.`5`, terminals.ingress.`5` connect noc.io.ingress.`6`, terminals.ingress.`6` connect noc.io.ingress.`7`, terminals.ingress.`7` connect noc.io.ingress.`8`, terminals.ingress.`8` connect noc.io.ingress.`9`, terminals.ingress.`9` connect noc.io.ingress.`10`, terminals.ingress.`10` connect noc.io.ingress.`11`, terminals.ingress.`11` connect noc.io.ingress.`12`, terminals.ingress.`12` connect noc.io.ingress.`13`, terminals.ingress.`13` connect noc.io.ingress.`14`, terminals.ingress.`14` connect noc.io.ingress.`15`, terminals.ingress.`15` connect noc.io.ingress.`16`, terminals.ingress.`16` connect noc.io.ingress.`17`, terminals.ingress.`17` connect noc.io.ingress.`18`, terminals.ingress.`18` connect noc.io.ingress.`19`, terminals.ingress.`19` connect noc.io.ingress.`20`, terminals.ingress.`20` connect noc.io.ingress.`21`, terminals.ingress.`21` connect terminals.egress.`0`.flit.bits, noc.io.egress.`0`.flit.bits connect terminals.egress.`0`.flit.valid, noc.io.egress.`0`.flit.valid connect noc.io.egress.`0`.flit.ready, terminals.egress.`0`.flit.ready connect terminals.egress.`1`.flit.bits, noc.io.egress.`1`.flit.bits connect terminals.egress.`1`.flit.valid, noc.io.egress.`1`.flit.valid connect noc.io.egress.`1`.flit.ready, terminals.egress.`1`.flit.ready connect terminals.egress.`2`.flit.bits, noc.io.egress.`2`.flit.bits connect terminals.egress.`2`.flit.valid, noc.io.egress.`2`.flit.valid connect noc.io.egress.`2`.flit.ready, terminals.egress.`2`.flit.ready connect terminals.egress.`3`.flit.bits, noc.io.egress.`3`.flit.bits connect terminals.egress.`3`.flit.valid, noc.io.egress.`3`.flit.valid connect noc.io.egress.`3`.flit.ready, terminals.egress.`3`.flit.ready connect terminals.egress.`4`.flit.bits, noc.io.egress.`4`.flit.bits connect terminals.egress.`4`.flit.valid, noc.io.egress.`4`.flit.valid connect noc.io.egress.`4`.flit.ready, terminals.egress.`4`.flit.ready connect terminals.egress.`5`.flit.bits, noc.io.egress.`5`.flit.bits connect terminals.egress.`5`.flit.valid, noc.io.egress.`5`.flit.valid connect noc.io.egress.`5`.flit.ready, terminals.egress.`5`.flit.ready connect terminals.egress.`6`.flit.bits, noc.io.egress.`6`.flit.bits connect terminals.egress.`6`.flit.valid, noc.io.egress.`6`.flit.valid connect noc.io.egress.`6`.flit.ready, terminals.egress.`6`.flit.ready connect terminals.egress.`7`.flit.bits, noc.io.egress.`7`.flit.bits connect terminals.egress.`7`.flit.valid, noc.io.egress.`7`.flit.valid connect noc.io.egress.`7`.flit.ready, terminals.egress.`7`.flit.ready connect terminals.egress.`8`.flit.bits, noc.io.egress.`8`.flit.bits connect terminals.egress.`8`.flit.valid, noc.io.egress.`8`.flit.valid connect noc.io.egress.`8`.flit.ready, terminals.egress.`8`.flit.ready connect terminals.egress.`9`.flit.bits, noc.io.egress.`9`.flit.bits connect terminals.egress.`9`.flit.valid, noc.io.egress.`9`.flit.valid connect noc.io.egress.`9`.flit.ready, terminals.egress.`9`.flit.ready connect terminals.egress.`10`.flit.bits, noc.io.egress.`10`.flit.bits connect terminals.egress.`10`.flit.valid, noc.io.egress.`10`.flit.valid connect noc.io.egress.`10`.flit.ready, terminals.egress.`10`.flit.ready connect terminals.egress.`11`.flit.bits, noc.io.egress.`11`.flit.bits connect terminals.egress.`11`.flit.valid, noc.io.egress.`11`.flit.valid connect noc.io.egress.`11`.flit.ready, terminals.egress.`11`.flit.ready connect terminals.egress.`12`.flit.bits, noc.io.egress.`12`.flit.bits connect terminals.egress.`12`.flit.valid, noc.io.egress.`12`.flit.valid connect noc.io.egress.`12`.flit.ready, terminals.egress.`12`.flit.ready connect terminals.egress.`13`.flit.bits, noc.io.egress.`13`.flit.bits connect terminals.egress.`13`.flit.valid, noc.io.egress.`13`.flit.valid connect noc.io.egress.`13`.flit.ready, terminals.egress.`13`.flit.ready connect terminals.egress.`14`.flit.bits, noc.io.egress.`14`.flit.bits connect terminals.egress.`14`.flit.valid, noc.io.egress.`14`.flit.valid connect noc.io.egress.`14`.flit.ready, terminals.egress.`14`.flit.ready connect terminals.egress.`15`.flit.bits, noc.io.egress.`15`.flit.bits connect terminals.egress.`15`.flit.valid, noc.io.egress.`15`.flit.valid connect noc.io.egress.`15`.flit.ready, terminals.egress.`15`.flit.ready connect terminals.egress.`16`.flit.bits, noc.io.egress.`16`.flit.bits connect terminals.egress.`16`.flit.valid, noc.io.egress.`16`.flit.valid connect noc.io.egress.`16`.flit.ready, terminals.egress.`16`.flit.ready connect terminals.egress.`17`.flit.bits, noc.io.egress.`17`.flit.bits connect terminals.egress.`17`.flit.valid, noc.io.egress.`17`.flit.valid connect noc.io.egress.`17`.flit.ready, terminals.egress.`17`.flit.ready connect terminals.egress.`18`.flit.bits, noc.io.egress.`18`.flit.bits connect terminals.egress.`18`.flit.valid, noc.io.egress.`18`.flit.valid connect noc.io.egress.`18`.flit.ready, terminals.egress.`18`.flit.ready connect terminals.egress.`19`.flit.bits, noc.io.egress.`19`.flit.bits connect terminals.egress.`19`.flit.valid, noc.io.egress.`19`.flit.valid connect noc.io.egress.`19`.flit.ready, terminals.egress.`19`.flit.ready connect terminals.egress.`20`.flit.bits, noc.io.egress.`20`.flit.bits connect terminals.egress.`20`.flit.valid, noc.io.egress.`20`.flit.valid connect noc.io.egress.`20`.flit.ready, terminals.egress.`20`.flit.ready connect terminals.egress.`21`.flit.bits, noc.io.egress.`21`.flit.bits connect terminals.egress.`21`.flit.valid, noc.io.egress.`21`.flit.valid connect noc.io.egress.`21`.flit.ready, terminals.egress.`21`.flit.ready connect terminals.egress.`22`.flit.bits, noc.io.egress.`22`.flit.bits connect terminals.egress.`22`.flit.valid, noc.io.egress.`22`.flit.valid connect noc.io.egress.`22`.flit.ready, terminals.egress.`22`.flit.ready inst nif_master of TLMasterToNoC_10 connect nif_master.clock, clock connect nif_master.reset, reset invalidate nif_master.io.tilelink.d.bits.corrupt invalidate nif_master.io.tilelink.d.bits.data invalidate nif_master.io.tilelink.d.bits.denied invalidate nif_master.io.tilelink.d.bits.sink invalidate nif_master.io.tilelink.d.bits.source invalidate nif_master.io.tilelink.d.bits.size invalidate nif_master.io.tilelink.d.bits.param invalidate nif_master.io.tilelink.d.bits.opcode invalidate nif_master.io.tilelink.d.valid invalidate nif_master.io.tilelink.d.ready invalidate nif_master.io.tilelink.a.bits.corrupt invalidate nif_master.io.tilelink.a.bits.data invalidate nif_master.io.tilelink.a.bits.mask invalidate nif_master.io.tilelink.a.bits.address invalidate nif_master.io.tilelink.a.bits.source invalidate nif_master.io.tilelink.a.bits.size invalidate nif_master.io.tilelink.a.bits.param invalidate nif_master.io.tilelink.a.bits.opcode invalidate nif_master.io.tilelink.a.valid invalidate nif_master.io.tilelink.a.ready connect nif_master.io.tilelink.a.valid, UInt<1>(0h0) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<3>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_2.bits.sink, UInt<1>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) connect nif_master.io.tilelink.a.valid, io.protocol.`0`.in.`0`.a.valid connect io.protocol.`0`.in.`0`.a.ready, nif_master.io.tilelink.a.ready connect nif_master.io.tilelink.a.bits.corrupt, io.protocol.`0`.in.`0`.a.bits.corrupt connect nif_master.io.tilelink.a.bits.data, io.protocol.`0`.in.`0`.a.bits.data connect nif_master.io.tilelink.a.bits.mask, io.protocol.`0`.in.`0`.a.bits.mask connect nif_master.io.tilelink.a.bits.address, io.protocol.`0`.in.`0`.a.bits.address connect nif_master.io.tilelink.a.bits.source, io.protocol.`0`.in.`0`.a.bits.source connect nif_master.io.tilelink.a.bits.size, io.protocol.`0`.in.`0`.a.bits.size connect nif_master.io.tilelink.a.bits.param, io.protocol.`0`.in.`0`.a.bits.param connect nif_master.io.tilelink.a.bits.opcode, io.protocol.`0`.in.`0`.a.bits.opcode connect io.protocol.`0`.in.`0`.d.valid, nif_master.io.tilelink.d.valid connect nif_master.io.tilelink.d.ready, io.protocol.`0`.in.`0`.d.ready connect io.protocol.`0`.in.`0`.d.bits.corrupt, nif_master.io.tilelink.d.bits.corrupt connect io.protocol.`0`.in.`0`.d.bits.data, nif_master.io.tilelink.d.bits.data connect io.protocol.`0`.in.`0`.d.bits.denied, nif_master.io.tilelink.d.bits.denied connect io.protocol.`0`.in.`0`.d.bits.sink, nif_master.io.tilelink.d.bits.sink connect io.protocol.`0`.in.`0`.d.bits.source, nif_master.io.tilelink.d.bits.source connect io.protocol.`0`.in.`0`.d.bits.size, nif_master.io.tilelink.d.bits.size connect io.protocol.`0`.in.`0`.d.bits.param, nif_master.io.tilelink.d.bits.param connect io.protocol.`0`.in.`0`.d.bits.opcode, nif_master.io.tilelink.d.bits.opcode connect terminals.ingress.`0`.flit.bits, nif_master.io.flits.a.bits connect terminals.ingress.`0`.flit.valid, nif_master.io.flits.a.valid connect nif_master.io.flits.a.ready, terminals.ingress.`0`.flit.ready connect terminals.ingress.`1`.flit.bits, nif_master.io.flits.c.bits connect terminals.ingress.`1`.flit.valid, nif_master.io.flits.c.valid connect nif_master.io.flits.c.ready, terminals.ingress.`1`.flit.ready connect terminals.ingress.`2`.flit.bits, nif_master.io.flits.e.bits connect terminals.ingress.`2`.flit.valid, nif_master.io.flits.e.valid connect nif_master.io.flits.e.ready, terminals.ingress.`2`.flit.ready connect nif_master.io.flits.b, terminals.egress.`0`.flit connect nif_master.io.flits.d, terminals.egress.`1`.flit inst nif_master_1 of TLMasterToNoC_11 connect nif_master_1.clock, clock connect nif_master_1.reset, reset invalidate nif_master_1.io.tilelink.d.bits.corrupt invalidate nif_master_1.io.tilelink.d.bits.data invalidate nif_master_1.io.tilelink.d.bits.denied invalidate nif_master_1.io.tilelink.d.bits.sink invalidate nif_master_1.io.tilelink.d.bits.source invalidate nif_master_1.io.tilelink.d.bits.size invalidate nif_master_1.io.tilelink.d.bits.param invalidate nif_master_1.io.tilelink.d.bits.opcode invalidate nif_master_1.io.tilelink.d.valid invalidate nif_master_1.io.tilelink.d.ready invalidate nif_master_1.io.tilelink.a.bits.corrupt invalidate nif_master_1.io.tilelink.a.bits.data invalidate nif_master_1.io.tilelink.a.bits.mask invalidate nif_master_1.io.tilelink.a.bits.address invalidate nif_master_1.io.tilelink.a.bits.source invalidate nif_master_1.io.tilelink.a.bits.size invalidate nif_master_1.io.tilelink.a.bits.param invalidate nif_master_1.io.tilelink.a.bits.opcode invalidate nif_master_1.io.tilelink.a.valid invalidate nif_master_1.io.tilelink.a.ready connect nif_master_1.io.tilelink.a.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_6.bits.sink, UInt<1>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) connect nif_master_1.io.tilelink.a.valid, io.protocol.`0`.in.`1`.a.valid connect io.protocol.`0`.in.`1`.a.ready, nif_master_1.io.tilelink.a.ready connect nif_master_1.io.tilelink.a.bits.corrupt, io.protocol.`0`.in.`1`.a.bits.corrupt connect nif_master_1.io.tilelink.a.bits.data, io.protocol.`0`.in.`1`.a.bits.data connect nif_master_1.io.tilelink.a.bits.mask, io.protocol.`0`.in.`1`.a.bits.mask connect nif_master_1.io.tilelink.a.bits.address, io.protocol.`0`.in.`1`.a.bits.address connect nif_master_1.io.tilelink.a.bits.source, io.protocol.`0`.in.`1`.a.bits.source connect nif_master_1.io.tilelink.a.bits.size, io.protocol.`0`.in.`1`.a.bits.size connect nif_master_1.io.tilelink.a.bits.param, io.protocol.`0`.in.`1`.a.bits.param connect nif_master_1.io.tilelink.a.bits.opcode, io.protocol.`0`.in.`1`.a.bits.opcode connect io.protocol.`0`.in.`1`.d.valid, nif_master_1.io.tilelink.d.valid connect nif_master_1.io.tilelink.d.ready, io.protocol.`0`.in.`1`.d.ready connect io.protocol.`0`.in.`1`.d.bits.corrupt, nif_master_1.io.tilelink.d.bits.corrupt connect io.protocol.`0`.in.`1`.d.bits.data, nif_master_1.io.tilelink.d.bits.data connect io.protocol.`0`.in.`1`.d.bits.denied, nif_master_1.io.tilelink.d.bits.denied connect io.protocol.`0`.in.`1`.d.bits.sink, nif_master_1.io.tilelink.d.bits.sink connect io.protocol.`0`.in.`1`.d.bits.source, nif_master_1.io.tilelink.d.bits.source connect io.protocol.`0`.in.`1`.d.bits.size, nif_master_1.io.tilelink.d.bits.size connect io.protocol.`0`.in.`1`.d.bits.param, nif_master_1.io.tilelink.d.bits.param connect io.protocol.`0`.in.`1`.d.bits.opcode, nif_master_1.io.tilelink.d.bits.opcode connect terminals.ingress.`3`.flit.bits, nif_master_1.io.flits.a.bits connect terminals.ingress.`3`.flit.valid, nif_master_1.io.flits.a.valid connect nif_master_1.io.flits.a.ready, terminals.ingress.`3`.flit.ready connect terminals.ingress.`4`.flit.bits, nif_master_1.io.flits.c.bits connect terminals.ingress.`4`.flit.valid, nif_master_1.io.flits.c.valid connect nif_master_1.io.flits.c.ready, terminals.ingress.`4`.flit.ready connect terminals.ingress.`5`.flit.bits, nif_master_1.io.flits.e.bits connect terminals.ingress.`5`.flit.valid, nif_master_1.io.flits.e.valid connect nif_master_1.io.flits.e.ready, terminals.ingress.`5`.flit.ready connect nif_master_1.io.flits.b, terminals.egress.`2`.flit connect nif_master_1.io.flits.d, terminals.egress.`3`.flit inst nif_master_2 of TLMasterToNoC_12 connect nif_master_2.clock, clock connect nif_master_2.reset, reset invalidate nif_master_2.io.tilelink.d.bits.corrupt invalidate nif_master_2.io.tilelink.d.bits.data invalidate nif_master_2.io.tilelink.d.bits.denied invalidate nif_master_2.io.tilelink.d.bits.sink invalidate nif_master_2.io.tilelink.d.bits.source invalidate nif_master_2.io.tilelink.d.bits.size invalidate nif_master_2.io.tilelink.d.bits.param invalidate nif_master_2.io.tilelink.d.bits.opcode invalidate nif_master_2.io.tilelink.d.valid invalidate nif_master_2.io.tilelink.d.ready invalidate nif_master_2.io.tilelink.a.bits.corrupt invalidate nif_master_2.io.tilelink.a.bits.data invalidate nif_master_2.io.tilelink.a.bits.mask invalidate nif_master_2.io.tilelink.a.bits.address invalidate nif_master_2.io.tilelink.a.bits.source invalidate nif_master_2.io.tilelink.a.bits.size invalidate nif_master_2.io.tilelink.a.bits.param invalidate nif_master_2.io.tilelink.a.bits.opcode invalidate nif_master_2.io.tilelink.a.valid invalidate nif_master_2.io.tilelink.a.ready connect nif_master_2.io.tilelink.a.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) connect nif_master_2.io.tilelink.a.valid, io.protocol.`0`.in.`2`.a.valid connect io.protocol.`0`.in.`2`.a.ready, nif_master_2.io.tilelink.a.ready connect nif_master_2.io.tilelink.a.bits.corrupt, io.protocol.`0`.in.`2`.a.bits.corrupt connect nif_master_2.io.tilelink.a.bits.data, io.protocol.`0`.in.`2`.a.bits.data connect nif_master_2.io.tilelink.a.bits.mask, io.protocol.`0`.in.`2`.a.bits.mask connect nif_master_2.io.tilelink.a.bits.address, io.protocol.`0`.in.`2`.a.bits.address connect nif_master_2.io.tilelink.a.bits.source, io.protocol.`0`.in.`2`.a.bits.source connect nif_master_2.io.tilelink.a.bits.size, io.protocol.`0`.in.`2`.a.bits.size connect nif_master_2.io.tilelink.a.bits.param, io.protocol.`0`.in.`2`.a.bits.param connect nif_master_2.io.tilelink.a.bits.opcode, io.protocol.`0`.in.`2`.a.bits.opcode connect io.protocol.`0`.in.`2`.d.valid, nif_master_2.io.tilelink.d.valid connect nif_master_2.io.tilelink.d.ready, io.protocol.`0`.in.`2`.d.ready connect io.protocol.`0`.in.`2`.d.bits.corrupt, nif_master_2.io.tilelink.d.bits.corrupt connect io.protocol.`0`.in.`2`.d.bits.data, nif_master_2.io.tilelink.d.bits.data connect io.protocol.`0`.in.`2`.d.bits.denied, nif_master_2.io.tilelink.d.bits.denied connect io.protocol.`0`.in.`2`.d.bits.sink, nif_master_2.io.tilelink.d.bits.sink connect io.protocol.`0`.in.`2`.d.bits.source, nif_master_2.io.tilelink.d.bits.source connect io.protocol.`0`.in.`2`.d.bits.size, nif_master_2.io.tilelink.d.bits.size connect io.protocol.`0`.in.`2`.d.bits.param, nif_master_2.io.tilelink.d.bits.param connect io.protocol.`0`.in.`2`.d.bits.opcode, nif_master_2.io.tilelink.d.bits.opcode connect terminals.ingress.`6`.flit.bits, nif_master_2.io.flits.a.bits connect terminals.ingress.`6`.flit.valid, nif_master_2.io.flits.a.valid connect nif_master_2.io.flits.a.ready, terminals.ingress.`6`.flit.ready connect terminals.ingress.`7`.flit.bits, nif_master_2.io.flits.c.bits connect terminals.ingress.`7`.flit.valid, nif_master_2.io.flits.c.valid connect nif_master_2.io.flits.c.ready, terminals.ingress.`7`.flit.ready connect terminals.ingress.`8`.flit.bits, nif_master_2.io.flits.e.bits connect terminals.ingress.`8`.flit.valid, nif_master_2.io.flits.e.valid connect nif_master_2.io.flits.e.ready, terminals.ingress.`8`.flit.ready connect nif_master_2.io.flits.b, terminals.egress.`4`.flit connect nif_master_2.io.flits.d, terminals.egress.`5`.flit inst nif_master_3 of TLMasterToNoC_13 connect nif_master_3.clock, clock connect nif_master_3.reset, reset invalidate nif_master_3.io.tilelink.d.bits.corrupt invalidate nif_master_3.io.tilelink.d.bits.data invalidate nif_master_3.io.tilelink.d.bits.denied invalidate nif_master_3.io.tilelink.d.bits.sink invalidate nif_master_3.io.tilelink.d.bits.source invalidate nif_master_3.io.tilelink.d.bits.size invalidate nif_master_3.io.tilelink.d.bits.param invalidate nif_master_3.io.tilelink.d.bits.opcode invalidate nif_master_3.io.tilelink.d.valid invalidate nif_master_3.io.tilelink.d.ready invalidate nif_master_3.io.tilelink.a.bits.corrupt invalidate nif_master_3.io.tilelink.a.bits.data invalidate nif_master_3.io.tilelink.a.bits.mask invalidate nif_master_3.io.tilelink.a.bits.address invalidate nif_master_3.io.tilelink.a.bits.source invalidate nif_master_3.io.tilelink.a.bits.size invalidate nif_master_3.io.tilelink.a.bits.param invalidate nif_master_3.io.tilelink.a.bits.opcode invalidate nif_master_3.io.tilelink.a.valid invalidate nif_master_3.io.tilelink.a.ready connect nif_master_3.io.tilelink.a.valid, UInt<1>(0h0) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.valid, UInt<1>(0h0) connect nif_master_3.io.tilelink.a.valid, io.protocol.`0`.in.`3`.a.valid connect io.protocol.`0`.in.`3`.a.ready, nif_master_3.io.tilelink.a.ready connect nif_master_3.io.tilelink.a.bits.corrupt, io.protocol.`0`.in.`3`.a.bits.corrupt connect nif_master_3.io.tilelink.a.bits.data, io.protocol.`0`.in.`3`.a.bits.data connect nif_master_3.io.tilelink.a.bits.mask, io.protocol.`0`.in.`3`.a.bits.mask connect nif_master_3.io.tilelink.a.bits.address, io.protocol.`0`.in.`3`.a.bits.address connect nif_master_3.io.tilelink.a.bits.source, io.protocol.`0`.in.`3`.a.bits.source connect nif_master_3.io.tilelink.a.bits.size, io.protocol.`0`.in.`3`.a.bits.size connect nif_master_3.io.tilelink.a.bits.param, io.protocol.`0`.in.`3`.a.bits.param connect nif_master_3.io.tilelink.a.bits.opcode, io.protocol.`0`.in.`3`.a.bits.opcode connect io.protocol.`0`.in.`3`.d.valid, nif_master_3.io.tilelink.d.valid connect nif_master_3.io.tilelink.d.ready, io.protocol.`0`.in.`3`.d.ready connect io.protocol.`0`.in.`3`.d.bits.corrupt, nif_master_3.io.tilelink.d.bits.corrupt connect io.protocol.`0`.in.`3`.d.bits.data, nif_master_3.io.tilelink.d.bits.data connect io.protocol.`0`.in.`3`.d.bits.denied, nif_master_3.io.tilelink.d.bits.denied connect io.protocol.`0`.in.`3`.d.bits.sink, nif_master_3.io.tilelink.d.bits.sink connect io.protocol.`0`.in.`3`.d.bits.source, nif_master_3.io.tilelink.d.bits.source connect io.protocol.`0`.in.`3`.d.bits.size, nif_master_3.io.tilelink.d.bits.size connect io.protocol.`0`.in.`3`.d.bits.param, nif_master_3.io.tilelink.d.bits.param connect io.protocol.`0`.in.`3`.d.bits.opcode, nif_master_3.io.tilelink.d.bits.opcode connect terminals.ingress.`9`.flit.bits, nif_master_3.io.flits.a.bits connect terminals.ingress.`9`.flit.valid, nif_master_3.io.flits.a.valid connect nif_master_3.io.flits.a.ready, terminals.ingress.`9`.flit.ready connect terminals.ingress.`10`.flit.bits, nif_master_3.io.flits.c.bits connect terminals.ingress.`10`.flit.valid, nif_master_3.io.flits.c.valid connect nif_master_3.io.flits.c.ready, terminals.ingress.`10`.flit.ready connect terminals.ingress.`11`.flit.bits, nif_master_3.io.flits.e.bits connect terminals.ingress.`11`.flit.valid, nif_master_3.io.flits.e.valid connect nif_master_3.io.flits.e.ready, terminals.ingress.`11`.flit.ready connect nif_master_3.io.flits.b, terminals.egress.`6`.flit connect nif_master_3.io.flits.d, terminals.egress.`7`.flit inst nif_slave of TLSlaveToNoC_13 connect nif_slave.clock, clock connect nif_slave.reset, reset invalidate nif_slave.io.tilelink.d.bits.corrupt invalidate nif_slave.io.tilelink.d.bits.data invalidate nif_slave.io.tilelink.d.bits.denied invalidate nif_slave.io.tilelink.d.bits.sink invalidate nif_slave.io.tilelink.d.bits.source invalidate nif_slave.io.tilelink.d.bits.size invalidate nif_slave.io.tilelink.d.bits.param invalidate nif_slave.io.tilelink.d.bits.opcode invalidate nif_slave.io.tilelink.d.valid invalidate nif_slave.io.tilelink.d.ready invalidate nif_slave.io.tilelink.a.bits.corrupt invalidate nif_slave.io.tilelink.a.bits.data invalidate nif_slave.io.tilelink.a.bits.mask invalidate nif_slave.io.tilelink.a.bits.address invalidate nif_slave.io.tilelink.a.bits.source invalidate nif_slave.io.tilelink.a.bits.size invalidate nif_slave.io.tilelink.a.bits.param invalidate nif_slave.io.tilelink.a.bits.opcode invalidate nif_slave.io.tilelink.a.valid invalidate nif_slave.io.tilelink.a.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.mask, UInt<8>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<2>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready connect _WIRE_17.valid, UInt<1>(0h0) connect nif_slave.io.tilelink.d.valid, UInt<1>(0h0) connect io.protocol.`0`.out.`0`.a.valid, nif_slave.io.tilelink.a.valid connect nif_slave.io.tilelink.a.ready, io.protocol.`0`.out.`0`.a.ready connect io.protocol.`0`.out.`0`.a.bits.corrupt, nif_slave.io.tilelink.a.bits.corrupt connect io.protocol.`0`.out.`0`.a.bits.data, nif_slave.io.tilelink.a.bits.data connect io.protocol.`0`.out.`0`.a.bits.mask, nif_slave.io.tilelink.a.bits.mask connect io.protocol.`0`.out.`0`.a.bits.address, nif_slave.io.tilelink.a.bits.address connect io.protocol.`0`.out.`0`.a.bits.source, nif_slave.io.tilelink.a.bits.source connect io.protocol.`0`.out.`0`.a.bits.size, nif_slave.io.tilelink.a.bits.size connect io.protocol.`0`.out.`0`.a.bits.param, nif_slave.io.tilelink.a.bits.param connect io.protocol.`0`.out.`0`.a.bits.opcode, nif_slave.io.tilelink.a.bits.opcode connect nif_slave.io.tilelink.d.valid, io.protocol.`0`.out.`0`.d.valid connect io.protocol.`0`.out.`0`.d.ready, nif_slave.io.tilelink.d.ready connect nif_slave.io.tilelink.d.bits.corrupt, io.protocol.`0`.out.`0`.d.bits.corrupt connect nif_slave.io.tilelink.d.bits.data, io.protocol.`0`.out.`0`.d.bits.data connect nif_slave.io.tilelink.d.bits.denied, io.protocol.`0`.out.`0`.d.bits.denied connect nif_slave.io.tilelink.d.bits.sink, io.protocol.`0`.out.`0`.d.bits.sink connect nif_slave.io.tilelink.d.bits.source, io.protocol.`0`.out.`0`.d.bits.source connect nif_slave.io.tilelink.d.bits.size, io.protocol.`0`.out.`0`.d.bits.size connect nif_slave.io.tilelink.d.bits.param, io.protocol.`0`.out.`0`.d.bits.param connect nif_slave.io.tilelink.d.bits.opcode, io.protocol.`0`.out.`0`.d.bits.opcode connect terminals.ingress.`12`.flit.bits, nif_slave.io.flits.b.bits connect terminals.ingress.`12`.flit.valid, nif_slave.io.flits.b.valid connect nif_slave.io.flits.b.ready, terminals.ingress.`12`.flit.ready connect terminals.ingress.`13`.flit.bits, nif_slave.io.flits.d.bits connect terminals.ingress.`13`.flit.valid, nif_slave.io.flits.d.valid connect nif_slave.io.flits.d.ready, terminals.ingress.`13`.flit.ready connect nif_slave.io.flits.a, terminals.egress.`8`.flit connect nif_slave.io.flits.c, terminals.egress.`9`.flit connect nif_slave.io.flits.e, terminals.egress.`10`.flit inst nif_slave_1 of TLSlaveToNoC_14 connect nif_slave_1.clock, clock connect nif_slave_1.reset, reset invalidate nif_slave_1.io.tilelink.d.bits.corrupt invalidate nif_slave_1.io.tilelink.d.bits.data invalidate nif_slave_1.io.tilelink.d.bits.denied invalidate nif_slave_1.io.tilelink.d.bits.sink invalidate nif_slave_1.io.tilelink.d.bits.source invalidate nif_slave_1.io.tilelink.d.bits.size invalidate nif_slave_1.io.tilelink.d.bits.param invalidate nif_slave_1.io.tilelink.d.bits.opcode invalidate nif_slave_1.io.tilelink.d.valid invalidate nif_slave_1.io.tilelink.d.ready invalidate nif_slave_1.io.tilelink.a.bits.corrupt invalidate nif_slave_1.io.tilelink.a.bits.data invalidate nif_slave_1.io.tilelink.a.bits.mask invalidate nif_slave_1.io.tilelink.a.bits.address invalidate nif_slave_1.io.tilelink.a.bits.source invalidate nif_slave_1.io.tilelink.a.bits.size invalidate nif_slave_1.io.tilelink.a.bits.param invalidate nif_slave_1.io.tilelink.a.bits.opcode invalidate nif_slave_1.io.tilelink.a.valid invalidate nif_slave_1.io.tilelink.a.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.mask, UInt<8>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) connect nif_slave_1.io.tilelink.d.valid, UInt<1>(0h0) connect io.protocol.`0`.out.`1`.a.valid, nif_slave_1.io.tilelink.a.valid connect nif_slave_1.io.tilelink.a.ready, io.protocol.`0`.out.`1`.a.ready connect io.protocol.`0`.out.`1`.a.bits.corrupt, nif_slave_1.io.tilelink.a.bits.corrupt connect io.protocol.`0`.out.`1`.a.bits.data, nif_slave_1.io.tilelink.a.bits.data connect io.protocol.`0`.out.`1`.a.bits.mask, nif_slave_1.io.tilelink.a.bits.mask connect io.protocol.`0`.out.`1`.a.bits.address, nif_slave_1.io.tilelink.a.bits.address connect io.protocol.`0`.out.`1`.a.bits.source, nif_slave_1.io.tilelink.a.bits.source connect io.protocol.`0`.out.`1`.a.bits.size, nif_slave_1.io.tilelink.a.bits.size connect io.protocol.`0`.out.`1`.a.bits.param, nif_slave_1.io.tilelink.a.bits.param connect io.protocol.`0`.out.`1`.a.bits.opcode, nif_slave_1.io.tilelink.a.bits.opcode connect nif_slave_1.io.tilelink.d.valid, io.protocol.`0`.out.`1`.d.valid connect io.protocol.`0`.out.`1`.d.ready, nif_slave_1.io.tilelink.d.ready connect nif_slave_1.io.tilelink.d.bits.corrupt, io.protocol.`0`.out.`1`.d.bits.corrupt connect nif_slave_1.io.tilelink.d.bits.data, io.protocol.`0`.out.`1`.d.bits.data connect nif_slave_1.io.tilelink.d.bits.denied, io.protocol.`0`.out.`1`.d.bits.denied connect nif_slave_1.io.tilelink.d.bits.sink, io.protocol.`0`.out.`1`.d.bits.sink connect nif_slave_1.io.tilelink.d.bits.source, io.protocol.`0`.out.`1`.d.bits.source connect nif_slave_1.io.tilelink.d.bits.size, io.protocol.`0`.out.`1`.d.bits.size connect nif_slave_1.io.tilelink.d.bits.param, io.protocol.`0`.out.`1`.d.bits.param connect nif_slave_1.io.tilelink.d.bits.opcode, io.protocol.`0`.out.`1`.d.bits.opcode connect terminals.ingress.`14`.flit.bits, nif_slave_1.io.flits.b.bits connect terminals.ingress.`14`.flit.valid, nif_slave_1.io.flits.b.valid connect nif_slave_1.io.flits.b.ready, terminals.ingress.`14`.flit.ready connect terminals.ingress.`15`.flit.bits, nif_slave_1.io.flits.d.bits connect terminals.ingress.`15`.flit.valid, nif_slave_1.io.flits.d.valid connect nif_slave_1.io.flits.d.ready, terminals.ingress.`15`.flit.ready connect nif_slave_1.io.flits.a, terminals.egress.`11`.flit connect nif_slave_1.io.flits.c, terminals.egress.`12`.flit connect nif_slave_1.io.flits.e, terminals.egress.`13`.flit inst nif_slave_2 of TLSlaveToNoC_15 connect nif_slave_2.clock, clock connect nif_slave_2.reset, reset invalidate nif_slave_2.io.tilelink.d.bits.corrupt invalidate nif_slave_2.io.tilelink.d.bits.data invalidate nif_slave_2.io.tilelink.d.bits.denied invalidate nif_slave_2.io.tilelink.d.bits.sink invalidate nif_slave_2.io.tilelink.d.bits.source invalidate nif_slave_2.io.tilelink.d.bits.size invalidate nif_slave_2.io.tilelink.d.bits.param invalidate nif_slave_2.io.tilelink.d.bits.opcode invalidate nif_slave_2.io.tilelink.d.valid invalidate nif_slave_2.io.tilelink.d.ready invalidate nif_slave_2.io.tilelink.a.bits.corrupt invalidate nif_slave_2.io.tilelink.a.bits.data invalidate nif_slave_2.io.tilelink.a.bits.mask invalidate nif_slave_2.io.tilelink.a.bits.address invalidate nif_slave_2.io.tilelink.a.bits.source invalidate nif_slave_2.io.tilelink.a.bits.size invalidate nif_slave_2.io.tilelink.a.bits.param invalidate nif_slave_2.io.tilelink.a.bits.opcode invalidate nif_slave_2.io.tilelink.a.valid invalidate nif_slave_2.io.tilelink.a.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.mask, UInt<8>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<2>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) connect nif_slave_2.io.tilelink.d.valid, UInt<1>(0h0) connect io.protocol.`0`.out.`2`.a.valid, nif_slave_2.io.tilelink.a.valid connect nif_slave_2.io.tilelink.a.ready, io.protocol.`0`.out.`2`.a.ready connect io.protocol.`0`.out.`2`.a.bits.corrupt, nif_slave_2.io.tilelink.a.bits.corrupt connect io.protocol.`0`.out.`2`.a.bits.data, nif_slave_2.io.tilelink.a.bits.data connect io.protocol.`0`.out.`2`.a.bits.mask, nif_slave_2.io.tilelink.a.bits.mask connect io.protocol.`0`.out.`2`.a.bits.address, nif_slave_2.io.tilelink.a.bits.address connect io.protocol.`0`.out.`2`.a.bits.source, nif_slave_2.io.tilelink.a.bits.source connect io.protocol.`0`.out.`2`.a.bits.size, nif_slave_2.io.tilelink.a.bits.size connect io.protocol.`0`.out.`2`.a.bits.param, nif_slave_2.io.tilelink.a.bits.param connect io.protocol.`0`.out.`2`.a.bits.opcode, nif_slave_2.io.tilelink.a.bits.opcode connect nif_slave_2.io.tilelink.d.valid, io.protocol.`0`.out.`2`.d.valid connect io.protocol.`0`.out.`2`.d.ready, nif_slave_2.io.tilelink.d.ready connect nif_slave_2.io.tilelink.d.bits.corrupt, io.protocol.`0`.out.`2`.d.bits.corrupt connect nif_slave_2.io.tilelink.d.bits.data, io.protocol.`0`.out.`2`.d.bits.data connect nif_slave_2.io.tilelink.d.bits.denied, io.protocol.`0`.out.`2`.d.bits.denied connect nif_slave_2.io.tilelink.d.bits.sink, io.protocol.`0`.out.`2`.d.bits.sink connect nif_slave_2.io.tilelink.d.bits.source, io.protocol.`0`.out.`2`.d.bits.source connect nif_slave_2.io.tilelink.d.bits.size, io.protocol.`0`.out.`2`.d.bits.size connect nif_slave_2.io.tilelink.d.bits.param, io.protocol.`0`.out.`2`.d.bits.param connect nif_slave_2.io.tilelink.d.bits.opcode, io.protocol.`0`.out.`2`.d.bits.opcode connect terminals.ingress.`16`.flit.bits, nif_slave_2.io.flits.b.bits connect terminals.ingress.`16`.flit.valid, nif_slave_2.io.flits.b.valid connect nif_slave_2.io.flits.b.ready, terminals.ingress.`16`.flit.ready connect terminals.ingress.`17`.flit.bits, nif_slave_2.io.flits.d.bits connect terminals.ingress.`17`.flit.valid, nif_slave_2.io.flits.d.valid connect nif_slave_2.io.flits.d.ready, terminals.ingress.`17`.flit.ready connect nif_slave_2.io.flits.a, terminals.egress.`14`.flit connect nif_slave_2.io.flits.c, terminals.egress.`15`.flit connect nif_slave_2.io.flits.e, terminals.egress.`16`.flit inst nif_slave_3 of TLSlaveToNoC_16 connect nif_slave_3.clock, clock connect nif_slave_3.reset, reset invalidate nif_slave_3.io.tilelink.d.bits.corrupt invalidate nif_slave_3.io.tilelink.d.bits.data invalidate nif_slave_3.io.tilelink.d.bits.denied invalidate nif_slave_3.io.tilelink.d.bits.sink invalidate nif_slave_3.io.tilelink.d.bits.source invalidate nif_slave_3.io.tilelink.d.bits.size invalidate nif_slave_3.io.tilelink.d.bits.param invalidate nif_slave_3.io.tilelink.d.bits.opcode invalidate nif_slave_3.io.tilelink.d.valid invalidate nif_slave_3.io.tilelink.d.ready invalidate nif_slave_3.io.tilelink.a.bits.corrupt invalidate nif_slave_3.io.tilelink.a.bits.data invalidate nif_slave_3.io.tilelink.a.bits.mask invalidate nif_slave_3.io.tilelink.a.bits.address invalidate nif_slave_3.io.tilelink.a.bits.source invalidate nif_slave_3.io.tilelink.a.bits.size invalidate nif_slave_3.io.tilelink.a.bits.param invalidate nif_slave_3.io.tilelink.a.bits.opcode invalidate nif_slave_3.io.tilelink.a.valid invalidate nif_slave_3.io.tilelink.a.ready wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.mask, UInt<8>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<2>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.valid, UInt<1>(0h0) connect nif_slave_3.io.tilelink.d.valid, UInt<1>(0h0) connect io.protocol.`0`.out.`3`.a.valid, nif_slave_3.io.tilelink.a.valid connect nif_slave_3.io.tilelink.a.ready, io.protocol.`0`.out.`3`.a.ready connect io.protocol.`0`.out.`3`.a.bits.corrupt, nif_slave_3.io.tilelink.a.bits.corrupt connect io.protocol.`0`.out.`3`.a.bits.data, nif_slave_3.io.tilelink.a.bits.data connect io.protocol.`0`.out.`3`.a.bits.mask, nif_slave_3.io.tilelink.a.bits.mask connect io.protocol.`0`.out.`3`.a.bits.address, nif_slave_3.io.tilelink.a.bits.address connect io.protocol.`0`.out.`3`.a.bits.source, nif_slave_3.io.tilelink.a.bits.source connect io.protocol.`0`.out.`3`.a.bits.size, nif_slave_3.io.tilelink.a.bits.size connect io.protocol.`0`.out.`3`.a.bits.param, nif_slave_3.io.tilelink.a.bits.param connect io.protocol.`0`.out.`3`.a.bits.opcode, nif_slave_3.io.tilelink.a.bits.opcode connect nif_slave_3.io.tilelink.d.valid, io.protocol.`0`.out.`3`.d.valid connect io.protocol.`0`.out.`3`.d.ready, nif_slave_3.io.tilelink.d.ready connect nif_slave_3.io.tilelink.d.bits.corrupt, io.protocol.`0`.out.`3`.d.bits.corrupt connect nif_slave_3.io.tilelink.d.bits.data, io.protocol.`0`.out.`3`.d.bits.data connect nif_slave_3.io.tilelink.d.bits.denied, io.protocol.`0`.out.`3`.d.bits.denied connect nif_slave_3.io.tilelink.d.bits.sink, io.protocol.`0`.out.`3`.d.bits.sink connect nif_slave_3.io.tilelink.d.bits.source, io.protocol.`0`.out.`3`.d.bits.source connect nif_slave_3.io.tilelink.d.bits.size, io.protocol.`0`.out.`3`.d.bits.size connect nif_slave_3.io.tilelink.d.bits.param, io.protocol.`0`.out.`3`.d.bits.param connect nif_slave_3.io.tilelink.d.bits.opcode, io.protocol.`0`.out.`3`.d.bits.opcode connect terminals.ingress.`18`.flit.bits, nif_slave_3.io.flits.b.bits connect terminals.ingress.`18`.flit.valid, nif_slave_3.io.flits.b.valid connect nif_slave_3.io.flits.b.ready, terminals.ingress.`18`.flit.ready connect terminals.ingress.`19`.flit.bits, nif_slave_3.io.flits.d.bits connect terminals.ingress.`19`.flit.valid, nif_slave_3.io.flits.d.valid connect nif_slave_3.io.flits.d.ready, terminals.ingress.`19`.flit.ready connect nif_slave_3.io.flits.a, terminals.egress.`17`.flit connect nif_slave_3.io.flits.c, terminals.egress.`18`.flit connect nif_slave_3.io.flits.e, terminals.egress.`19`.flit inst nif_slave_4 of TLSlaveToNoC_17 connect nif_slave_4.clock, clock connect nif_slave_4.reset, reset invalidate nif_slave_4.io.tilelink.d.bits.corrupt invalidate nif_slave_4.io.tilelink.d.bits.data invalidate nif_slave_4.io.tilelink.d.bits.denied invalidate nif_slave_4.io.tilelink.d.bits.sink invalidate nif_slave_4.io.tilelink.d.bits.source invalidate nif_slave_4.io.tilelink.d.bits.size invalidate nif_slave_4.io.tilelink.d.bits.param invalidate nif_slave_4.io.tilelink.d.bits.opcode invalidate nif_slave_4.io.tilelink.d.valid invalidate nif_slave_4.io.tilelink.d.ready invalidate nif_slave_4.io.tilelink.a.bits.corrupt invalidate nif_slave_4.io.tilelink.a.bits.data invalidate nif_slave_4.io.tilelink.a.bits.mask invalidate nif_slave_4.io.tilelink.a.bits.address invalidate nif_slave_4.io.tilelink.a.bits.source invalidate nif_slave_4.io.tilelink.a.bits.size invalidate nif_slave_4.io.tilelink.a.bits.param invalidate nif_slave_4.io.tilelink.a.bits.opcode invalidate nif_slave_4.io.tilelink.a.valid invalidate nif_slave_4.io.tilelink.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.valid, UInt<1>(0h0) connect nif_slave_4.io.tilelink.d.valid, UInt<1>(0h0) connect io.protocol.`0`.out.`4`.a.valid, nif_slave_4.io.tilelink.a.valid connect nif_slave_4.io.tilelink.a.ready, io.protocol.`0`.out.`4`.a.ready connect io.protocol.`0`.out.`4`.a.bits.corrupt, nif_slave_4.io.tilelink.a.bits.corrupt connect io.protocol.`0`.out.`4`.a.bits.data, nif_slave_4.io.tilelink.a.bits.data connect io.protocol.`0`.out.`4`.a.bits.mask, nif_slave_4.io.tilelink.a.bits.mask connect io.protocol.`0`.out.`4`.a.bits.address, nif_slave_4.io.tilelink.a.bits.address connect io.protocol.`0`.out.`4`.a.bits.source, nif_slave_4.io.tilelink.a.bits.source connect io.protocol.`0`.out.`4`.a.bits.size, nif_slave_4.io.tilelink.a.bits.size connect io.protocol.`0`.out.`4`.a.bits.param, nif_slave_4.io.tilelink.a.bits.param connect io.protocol.`0`.out.`4`.a.bits.opcode, nif_slave_4.io.tilelink.a.bits.opcode connect nif_slave_4.io.tilelink.d.valid, io.protocol.`0`.out.`4`.d.valid connect io.protocol.`0`.out.`4`.d.ready, nif_slave_4.io.tilelink.d.ready connect nif_slave_4.io.tilelink.d.bits.corrupt, io.protocol.`0`.out.`4`.d.bits.corrupt connect nif_slave_4.io.tilelink.d.bits.data, io.protocol.`0`.out.`4`.d.bits.data connect nif_slave_4.io.tilelink.d.bits.denied, io.protocol.`0`.out.`4`.d.bits.denied connect nif_slave_4.io.tilelink.d.bits.sink, io.protocol.`0`.out.`4`.d.bits.sink connect nif_slave_4.io.tilelink.d.bits.source, io.protocol.`0`.out.`4`.d.bits.source connect nif_slave_4.io.tilelink.d.bits.size, io.protocol.`0`.out.`4`.d.bits.size connect nif_slave_4.io.tilelink.d.bits.param, io.protocol.`0`.out.`4`.d.bits.param connect nif_slave_4.io.tilelink.d.bits.opcode, io.protocol.`0`.out.`4`.d.bits.opcode connect terminals.ingress.`20`.flit.bits, nif_slave_4.io.flits.b.bits connect terminals.ingress.`20`.flit.valid, nif_slave_4.io.flits.b.valid connect nif_slave_4.io.flits.b.ready, terminals.ingress.`20`.flit.ready connect terminals.ingress.`21`.flit.bits, nif_slave_4.io.flits.d.bits connect terminals.ingress.`21`.flit.valid, nif_slave_4.io.flits.d.valid connect nif_slave_4.io.flits.d.ready, terminals.ingress.`21`.flit.ready connect nif_slave_4.io.flits.a, terminals.egress.`20`.flit connect nif_slave_4.io.flits.c, terminals.egress.`21`.flit connect nif_slave_4.io.flits.e, terminals.egress.`22`.flit
module ProtocolNoC_2( // @[Protocol.scala:70:7] input clock, // @[Protocol.scala:70:7] input reset, // @[Protocol.scala:70:7] output io_protocol_0_in_3_a_ready, // @[Protocol.scala:71:14] input io_protocol_0_in_3_a_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_3_a_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_3_a_bits_param, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_3_a_bits_size, // @[Protocol.scala:71:14] input [3:0] io_protocol_0_in_3_a_bits_source, // @[Protocol.scala:71:14] input [31:0] io_protocol_0_in_3_a_bits_address, // @[Protocol.scala:71:14] input [7:0] io_protocol_0_in_3_a_bits_mask, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_in_3_a_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_in_3_a_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_in_3_d_ready, // @[Protocol.scala:71:14] output io_protocol_0_in_3_d_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_3_d_bits_opcode, // @[Protocol.scala:71:14] output [1:0] io_protocol_0_in_3_d_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_3_d_bits_size, // @[Protocol.scala:71:14] output [3:0] io_protocol_0_in_3_d_bits_source, // @[Protocol.scala:71:14] output io_protocol_0_in_3_d_bits_sink, // @[Protocol.scala:71:14] output io_protocol_0_in_3_d_bits_denied, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_in_3_d_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_in_3_d_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_in_2_a_ready, // @[Protocol.scala:71:14] input io_protocol_0_in_2_a_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_2_a_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_2_a_bits_param, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_2_a_bits_size, // @[Protocol.scala:71:14] input [3:0] io_protocol_0_in_2_a_bits_source, // @[Protocol.scala:71:14] input [31:0] io_protocol_0_in_2_a_bits_address, // @[Protocol.scala:71:14] input [7:0] io_protocol_0_in_2_a_bits_mask, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_in_2_a_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_in_2_a_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_in_2_d_ready, // @[Protocol.scala:71:14] output io_protocol_0_in_2_d_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_2_d_bits_opcode, // @[Protocol.scala:71:14] output [1:0] io_protocol_0_in_2_d_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_2_d_bits_size, // @[Protocol.scala:71:14] output [3:0] io_protocol_0_in_2_d_bits_source, // @[Protocol.scala:71:14] output io_protocol_0_in_2_d_bits_sink, // @[Protocol.scala:71:14] output io_protocol_0_in_2_d_bits_denied, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_in_2_d_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_in_2_d_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_in_1_a_ready, // @[Protocol.scala:71:14] input io_protocol_0_in_1_a_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_1_a_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_1_a_bits_param, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_1_a_bits_size, // @[Protocol.scala:71:14] input [3:0] io_protocol_0_in_1_a_bits_source, // @[Protocol.scala:71:14] input [31:0] io_protocol_0_in_1_a_bits_address, // @[Protocol.scala:71:14] input [7:0] io_protocol_0_in_1_a_bits_mask, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_in_1_a_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_in_1_a_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_in_1_d_ready, // @[Protocol.scala:71:14] output io_protocol_0_in_1_d_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_1_d_bits_opcode, // @[Protocol.scala:71:14] output [1:0] io_protocol_0_in_1_d_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_1_d_bits_size, // @[Protocol.scala:71:14] output [3:0] io_protocol_0_in_1_d_bits_source, // @[Protocol.scala:71:14] output io_protocol_0_in_1_d_bits_sink, // @[Protocol.scala:71:14] output io_protocol_0_in_1_d_bits_denied, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_in_1_d_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_in_1_d_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_in_0_a_ready, // @[Protocol.scala:71:14] input io_protocol_0_in_0_a_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_0_a_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_0_a_bits_param, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_in_0_a_bits_size, // @[Protocol.scala:71:14] input [3:0] io_protocol_0_in_0_a_bits_source, // @[Protocol.scala:71:14] input [31:0] io_protocol_0_in_0_a_bits_address, // @[Protocol.scala:71:14] input [7:0] io_protocol_0_in_0_a_bits_mask, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_in_0_a_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_in_0_a_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_in_0_d_ready, // @[Protocol.scala:71:14] output io_protocol_0_in_0_d_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_0_d_bits_opcode, // @[Protocol.scala:71:14] output [1:0] io_protocol_0_in_0_d_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_in_0_d_bits_size, // @[Protocol.scala:71:14] output [3:0] io_protocol_0_in_0_d_bits_source, // @[Protocol.scala:71:14] output io_protocol_0_in_0_d_bits_sink, // @[Protocol.scala:71:14] output io_protocol_0_in_0_d_bits_denied, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_in_0_d_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_in_0_d_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_out_4_a_ready, // @[Protocol.scala:71:14] output io_protocol_0_out_4_a_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_4_a_bits_opcode, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_4_a_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_4_a_bits_size, // @[Protocol.scala:71:14] output [5:0] io_protocol_0_out_4_a_bits_source, // @[Protocol.scala:71:14] output [27:0] io_protocol_0_out_4_a_bits_address, // @[Protocol.scala:71:14] output [7:0] io_protocol_0_out_4_a_bits_mask, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_out_4_a_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_out_4_a_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_out_4_d_ready, // @[Protocol.scala:71:14] input io_protocol_0_out_4_d_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_4_d_bits_opcode, // @[Protocol.scala:71:14] input [1:0] io_protocol_0_out_4_d_bits_param, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_4_d_bits_size, // @[Protocol.scala:71:14] input [5:0] io_protocol_0_out_4_d_bits_source, // @[Protocol.scala:71:14] input io_protocol_0_out_4_d_bits_sink, // @[Protocol.scala:71:14] input io_protocol_0_out_4_d_bits_denied, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_out_4_d_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_out_4_d_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_out_3_a_ready, // @[Protocol.scala:71:14] output io_protocol_0_out_3_a_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_3_a_bits_opcode, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_3_a_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_3_a_bits_size, // @[Protocol.scala:71:14] output [5:0] io_protocol_0_out_3_a_bits_source, // @[Protocol.scala:71:14] output [31:0] io_protocol_0_out_3_a_bits_address, // @[Protocol.scala:71:14] output [7:0] io_protocol_0_out_3_a_bits_mask, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_out_3_a_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_out_3_a_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_out_3_d_ready, // @[Protocol.scala:71:14] input io_protocol_0_out_3_d_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_3_d_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_3_d_bits_size, // @[Protocol.scala:71:14] input [5:0] io_protocol_0_out_3_d_bits_source, // @[Protocol.scala:71:14] input io_protocol_0_out_3_d_bits_denied, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_out_3_d_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_out_3_d_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_out_2_a_ready, // @[Protocol.scala:71:14] output io_protocol_0_out_2_a_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_2_a_bits_opcode, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_2_a_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_2_a_bits_size, // @[Protocol.scala:71:14] output [5:0] io_protocol_0_out_2_a_bits_source, // @[Protocol.scala:71:14] output [31:0] io_protocol_0_out_2_a_bits_address, // @[Protocol.scala:71:14] output [7:0] io_protocol_0_out_2_a_bits_mask, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_out_2_a_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_out_2_a_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_out_2_d_ready, // @[Protocol.scala:71:14] input io_protocol_0_out_2_d_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_2_d_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_2_d_bits_size, // @[Protocol.scala:71:14] input [5:0] io_protocol_0_out_2_d_bits_source, // @[Protocol.scala:71:14] input io_protocol_0_out_2_d_bits_denied, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_out_2_d_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_out_2_d_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_out_1_a_ready, // @[Protocol.scala:71:14] output io_protocol_0_out_1_a_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_1_a_bits_opcode, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_1_a_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_1_a_bits_size, // @[Protocol.scala:71:14] output [5:0] io_protocol_0_out_1_a_bits_source, // @[Protocol.scala:71:14] output [31:0] io_protocol_0_out_1_a_bits_address, // @[Protocol.scala:71:14] output [7:0] io_protocol_0_out_1_a_bits_mask, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_out_1_a_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_out_1_a_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_out_1_d_ready, // @[Protocol.scala:71:14] input io_protocol_0_out_1_d_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_1_d_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_1_d_bits_size, // @[Protocol.scala:71:14] input [5:0] io_protocol_0_out_1_d_bits_source, // @[Protocol.scala:71:14] input io_protocol_0_out_1_d_bits_denied, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_out_1_d_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_out_1_d_bits_corrupt, // @[Protocol.scala:71:14] input io_protocol_0_out_0_a_ready, // @[Protocol.scala:71:14] output io_protocol_0_out_0_a_valid, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_0_a_bits_opcode, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_0_a_bits_param, // @[Protocol.scala:71:14] output [2:0] io_protocol_0_out_0_a_bits_size, // @[Protocol.scala:71:14] output [5:0] io_protocol_0_out_0_a_bits_source, // @[Protocol.scala:71:14] output [31:0] io_protocol_0_out_0_a_bits_address, // @[Protocol.scala:71:14] output [7:0] io_protocol_0_out_0_a_bits_mask, // @[Protocol.scala:71:14] output [63:0] io_protocol_0_out_0_a_bits_data, // @[Protocol.scala:71:14] output io_protocol_0_out_0_a_bits_corrupt, // @[Protocol.scala:71:14] output io_protocol_0_out_0_d_ready, // @[Protocol.scala:71:14] input io_protocol_0_out_0_d_valid, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_0_d_bits_opcode, // @[Protocol.scala:71:14] input [2:0] io_protocol_0_out_0_d_bits_size, // @[Protocol.scala:71:14] input [5:0] io_protocol_0_out_0_d_bits_source, // @[Protocol.scala:71:14] input io_protocol_0_out_0_d_bits_denied, // @[Protocol.scala:71:14] input [63:0] io_protocol_0_out_0_d_bits_data, // @[Protocol.scala:71:14] input io_protocol_0_out_0_d_bits_corrupt // @[Protocol.scala:71:14] ); wire [31:0] _nif_slave_4_io_tilelink_a_bits_address; // @[Tilelink.scala:303:31] wire _nif_slave_4_io_flits_a_ready; // @[Tilelink.scala:303:31] wire _nif_slave_4_io_flits_c_ready; // @[Tilelink.scala:303:31] wire _nif_slave_4_io_flits_d_valid; // @[Tilelink.scala:303:31] wire _nif_slave_4_io_flits_d_bits_head; // @[Tilelink.scala:303:31] wire _nif_slave_4_io_flits_d_bits_tail; // @[Tilelink.scala:303:31] wire [72:0] _nif_slave_4_io_flits_d_bits_payload; // @[Tilelink.scala:303:31] wire [2:0] _nif_slave_4_io_flits_d_bits_egress_id; // @[Tilelink.scala:303:31] wire _nif_slave_4_io_flits_e_ready; // @[Tilelink.scala:303:31] wire _nif_slave_3_io_flits_a_ready; // @[Tilelink.scala:303:31] wire _nif_slave_3_io_flits_c_ready; // @[Tilelink.scala:303:31] wire _nif_slave_3_io_flits_d_valid; // @[Tilelink.scala:303:31] wire _nif_slave_3_io_flits_d_bits_head; // @[Tilelink.scala:303:31] wire _nif_slave_3_io_flits_d_bits_tail; // @[Tilelink.scala:303:31] wire [72:0] _nif_slave_3_io_flits_d_bits_payload; // @[Tilelink.scala:303:31] wire [2:0] _nif_slave_3_io_flits_d_bits_egress_id; // @[Tilelink.scala:303:31] wire _nif_slave_3_io_flits_e_ready; // @[Tilelink.scala:303:31] wire _nif_slave_2_io_flits_a_ready; // @[Tilelink.scala:303:31] wire _nif_slave_2_io_flits_c_ready; // @[Tilelink.scala:303:31] wire _nif_slave_2_io_flits_d_valid; // @[Tilelink.scala:303:31] wire _nif_slave_2_io_flits_d_bits_head; // @[Tilelink.scala:303:31] wire _nif_slave_2_io_flits_d_bits_tail; // @[Tilelink.scala:303:31] wire [72:0] _nif_slave_2_io_flits_d_bits_payload; // @[Tilelink.scala:303:31] wire [2:0] _nif_slave_2_io_flits_d_bits_egress_id; // @[Tilelink.scala:303:31] wire _nif_slave_2_io_flits_e_ready; // @[Tilelink.scala:303:31] wire _nif_slave_1_io_flits_a_ready; // @[Tilelink.scala:303:31] wire _nif_slave_1_io_flits_c_ready; // @[Tilelink.scala:303:31] wire _nif_slave_1_io_flits_d_valid; // @[Tilelink.scala:303:31] wire _nif_slave_1_io_flits_d_bits_head; // @[Tilelink.scala:303:31] wire _nif_slave_1_io_flits_d_bits_tail; // @[Tilelink.scala:303:31] wire [72:0] _nif_slave_1_io_flits_d_bits_payload; // @[Tilelink.scala:303:31] wire [2:0] _nif_slave_1_io_flits_d_bits_egress_id; // @[Tilelink.scala:303:31] wire _nif_slave_1_io_flits_e_ready; // @[Tilelink.scala:303:31] wire _nif_slave_io_flits_a_ready; // @[Tilelink.scala:303:31] wire _nif_slave_io_flits_c_ready; // @[Tilelink.scala:303:31] wire _nif_slave_io_flits_d_valid; // @[Tilelink.scala:303:31] wire _nif_slave_io_flits_d_bits_head; // @[Tilelink.scala:303:31] wire _nif_slave_io_flits_d_bits_tail; // @[Tilelink.scala:303:31] wire [72:0] _nif_slave_io_flits_d_bits_payload; // @[Tilelink.scala:303:31] wire [2:0] _nif_slave_io_flits_d_bits_egress_id; // @[Tilelink.scala:303:31] wire _nif_slave_io_flits_e_ready; // @[Tilelink.scala:303:31] wire [5:0] _nif_master_3_io_tilelink_d_bits_source; // @[Tilelink.scala:276:32] wire _nif_master_3_io_flits_a_valid; // @[Tilelink.scala:276:32] wire _nif_master_3_io_flits_a_bits_head; // @[Tilelink.scala:276:32] wire _nif_master_3_io_flits_a_bits_tail; // @[Tilelink.scala:276:32] wire [72:0] _nif_master_3_io_flits_a_bits_payload; // @[Tilelink.scala:276:32] wire [4:0] _nif_master_3_io_flits_a_bits_egress_id; // @[Tilelink.scala:276:32] wire _nif_master_3_io_flits_b_ready; // @[Tilelink.scala:276:32] wire _nif_master_3_io_flits_d_ready; // @[Tilelink.scala:276:32] wire [5:0] _nif_master_2_io_tilelink_d_bits_source; // @[Tilelink.scala:276:32] wire _nif_master_2_io_flits_a_valid; // @[Tilelink.scala:276:32] wire _nif_master_2_io_flits_a_bits_head; // @[Tilelink.scala:276:32] wire _nif_master_2_io_flits_a_bits_tail; // @[Tilelink.scala:276:32] wire [72:0] _nif_master_2_io_flits_a_bits_payload; // @[Tilelink.scala:276:32] wire [4:0] _nif_master_2_io_flits_a_bits_egress_id; // @[Tilelink.scala:276:32] wire _nif_master_2_io_flits_b_ready; // @[Tilelink.scala:276:32] wire _nif_master_2_io_flits_d_ready; // @[Tilelink.scala:276:32] wire [5:0] _nif_master_1_io_tilelink_d_bits_source; // @[Tilelink.scala:276:32] wire _nif_master_1_io_flits_a_valid; // @[Tilelink.scala:276:32] wire _nif_master_1_io_flits_a_bits_head; // @[Tilelink.scala:276:32] wire _nif_master_1_io_flits_a_bits_tail; // @[Tilelink.scala:276:32] wire [72:0] _nif_master_1_io_flits_a_bits_payload; // @[Tilelink.scala:276:32] wire [4:0] _nif_master_1_io_flits_a_bits_egress_id; // @[Tilelink.scala:276:32] wire _nif_master_1_io_flits_b_ready; // @[Tilelink.scala:276:32] wire _nif_master_1_io_flits_d_ready; // @[Tilelink.scala:276:32] wire [5:0] _nif_master_io_tilelink_d_bits_source; // @[Tilelink.scala:276:32] wire _nif_master_io_flits_a_valid; // @[Tilelink.scala:276:32] wire _nif_master_io_flits_a_bits_head; // @[Tilelink.scala:276:32] wire _nif_master_io_flits_a_bits_tail; // @[Tilelink.scala:276:32] wire [72:0] _nif_master_io_flits_a_bits_payload; // @[Tilelink.scala:276:32] wire [4:0] _nif_master_io_flits_a_bits_egress_id; // @[Tilelink.scala:276:32] wire _nif_master_io_flits_b_ready; // @[Tilelink.scala:276:32] wire _nif_master_io_flits_d_ready; // @[Tilelink.scala:276:32] wire _noc_io_ingress_21_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_19_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_17_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_15_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_13_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_9_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_6_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_3_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_ingress_0_flit_ready; // @[Protocol.scala:116:19] wire _noc_io_egress_22_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_22_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_22_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_21_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_21_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_21_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_20_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_20_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_20_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_20_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_19_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_19_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_19_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_18_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_18_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_18_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_17_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_17_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_17_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_17_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_16_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_16_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_16_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_15_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_15_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_15_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_14_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_14_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_14_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_14_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_13_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_13_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_13_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_12_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_12_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_12_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_11_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_11_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_11_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_11_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_10_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_10_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_10_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_9_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_9_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_9_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_8_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_8_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_8_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_8_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_7_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_7_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_7_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_7_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_6_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_6_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_6_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_5_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_5_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_5_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_5_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_4_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_4_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_4_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_3_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_3_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_3_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_3_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_2_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_2_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_2_flit_bits_tail; // @[Protocol.scala:116:19] wire _noc_io_egress_1_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_1_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_1_flit_bits_tail; // @[Protocol.scala:116:19] wire [72:0] _noc_io_egress_1_flit_bits_payload; // @[Protocol.scala:116:19] wire _noc_io_egress_0_flit_valid; // @[Protocol.scala:116:19] wire _noc_io_egress_0_flit_bits_head; // @[Protocol.scala:116:19] wire _noc_io_egress_0_flit_bits_tail; // @[Protocol.scala:116:19] NoC_2 noc ( // @[Protocol.scala:116:19] .clock (clock), .reset (reset), .io_ingress_21_flit_ready (_noc_io_ingress_21_flit_ready), .io_ingress_21_flit_valid (_nif_slave_4_io_flits_d_valid), // @[Tilelink.scala:303:31] .io_ingress_21_flit_bits_head (_nif_slave_4_io_flits_d_bits_head), // @[Tilelink.scala:303:31] .io_ingress_21_flit_bits_tail (_nif_slave_4_io_flits_d_bits_tail), // @[Tilelink.scala:303:31] .io_ingress_21_flit_bits_payload (_nif_slave_4_io_flits_d_bits_payload), // @[Tilelink.scala:303:31] .io_ingress_21_flit_bits_egress_id (_nif_slave_4_io_flits_d_bits_egress_id), // @[Tilelink.scala:303:31] .io_ingress_19_flit_ready (_noc_io_ingress_19_flit_ready), .io_ingress_19_flit_valid (_nif_slave_3_io_flits_d_valid), // @[Tilelink.scala:303:31] .io_ingress_19_flit_bits_head (_nif_slave_3_io_flits_d_bits_head), // @[Tilelink.scala:303:31] .io_ingress_19_flit_bits_tail (_nif_slave_3_io_flits_d_bits_tail), // @[Tilelink.scala:303:31] .io_ingress_19_flit_bits_payload (_nif_slave_3_io_flits_d_bits_payload), // @[Tilelink.scala:303:31] .io_ingress_19_flit_bits_egress_id (_nif_slave_3_io_flits_d_bits_egress_id), // @[Tilelink.scala:303:31] .io_ingress_17_flit_ready (_noc_io_ingress_17_flit_ready), .io_ingress_17_flit_valid (_nif_slave_2_io_flits_d_valid), // @[Tilelink.scala:303:31] .io_ingress_17_flit_bits_head (_nif_slave_2_io_flits_d_bits_head), // @[Tilelink.scala:303:31] .io_ingress_17_flit_bits_tail (_nif_slave_2_io_flits_d_bits_tail), // @[Tilelink.scala:303:31] .io_ingress_17_flit_bits_payload (_nif_slave_2_io_flits_d_bits_payload), // @[Tilelink.scala:303:31] .io_ingress_17_flit_bits_egress_id (_nif_slave_2_io_flits_d_bits_egress_id), // @[Tilelink.scala:303:31] .io_ingress_15_flit_ready (_noc_io_ingress_15_flit_ready), .io_ingress_15_flit_valid (_nif_slave_1_io_flits_d_valid), // @[Tilelink.scala:303:31] .io_ingress_15_flit_bits_head (_nif_slave_1_io_flits_d_bits_head), // @[Tilelink.scala:303:31] .io_ingress_15_flit_bits_tail (_nif_slave_1_io_flits_d_bits_tail), // @[Tilelink.scala:303:31] .io_ingress_15_flit_bits_payload (_nif_slave_1_io_flits_d_bits_payload), // @[Tilelink.scala:303:31] .io_ingress_15_flit_bits_egress_id (_nif_slave_1_io_flits_d_bits_egress_id), // @[Tilelink.scala:303:31] .io_ingress_13_flit_ready (_noc_io_ingress_13_flit_ready), .io_ingress_13_flit_valid (_nif_slave_io_flits_d_valid), // @[Tilelink.scala:303:31] .io_ingress_13_flit_bits_head (_nif_slave_io_flits_d_bits_head), // @[Tilelink.scala:303:31] .io_ingress_13_flit_bits_tail (_nif_slave_io_flits_d_bits_tail), // @[Tilelink.scala:303:31] .io_ingress_13_flit_bits_payload (_nif_slave_io_flits_d_bits_payload), // @[Tilelink.scala:303:31] .io_ingress_13_flit_bits_egress_id (_nif_slave_io_flits_d_bits_egress_id), // @[Tilelink.scala:303:31] .io_ingress_9_flit_ready (_noc_io_ingress_9_flit_ready), .io_ingress_9_flit_valid (_nif_master_3_io_flits_a_valid), // @[Tilelink.scala:276:32] .io_ingress_9_flit_bits_head (_nif_master_3_io_flits_a_bits_head), // @[Tilelink.scala:276:32] .io_ingress_9_flit_bits_tail (_nif_master_3_io_flits_a_bits_tail), // @[Tilelink.scala:276:32] .io_ingress_9_flit_bits_payload (_nif_master_3_io_flits_a_bits_payload), // @[Tilelink.scala:276:32] .io_ingress_9_flit_bits_egress_id (_nif_master_3_io_flits_a_bits_egress_id), // @[Tilelink.scala:276:32] .io_ingress_6_flit_ready (_noc_io_ingress_6_flit_ready), .io_ingress_6_flit_valid (_nif_master_2_io_flits_a_valid), // @[Tilelink.scala:276:32] .io_ingress_6_flit_bits_head (_nif_master_2_io_flits_a_bits_head), // @[Tilelink.scala:276:32] .io_ingress_6_flit_bits_tail (_nif_master_2_io_flits_a_bits_tail), // @[Tilelink.scala:276:32] .io_ingress_6_flit_bits_payload (_nif_master_2_io_flits_a_bits_payload), // @[Tilelink.scala:276:32] .io_ingress_6_flit_bits_egress_id (_nif_master_2_io_flits_a_bits_egress_id), // @[Tilelink.scala:276:32] .io_ingress_3_flit_ready (_noc_io_ingress_3_flit_ready), .io_ingress_3_flit_valid (_nif_master_1_io_flits_a_valid), // @[Tilelink.scala:276:32] .io_ingress_3_flit_bits_head (_nif_master_1_io_flits_a_bits_head), // @[Tilelink.scala:276:32] .io_ingress_3_flit_bits_tail (_nif_master_1_io_flits_a_bits_tail), // @[Tilelink.scala:276:32] .io_ingress_3_flit_bits_payload (_nif_master_1_io_flits_a_bits_payload), // @[Tilelink.scala:276:32] .io_ingress_3_flit_bits_egress_id (_nif_master_1_io_flits_a_bits_egress_id), // @[Tilelink.scala:276:32] .io_ingress_0_flit_ready (_noc_io_ingress_0_flit_ready), .io_ingress_0_flit_valid (_nif_master_io_flits_a_valid), // @[Tilelink.scala:276:32] .io_ingress_0_flit_bits_head (_nif_master_io_flits_a_bits_head), // @[Tilelink.scala:276:32] .io_ingress_0_flit_bits_tail (_nif_master_io_flits_a_bits_tail), // @[Tilelink.scala:276:32] .io_ingress_0_flit_bits_payload (_nif_master_io_flits_a_bits_payload), // @[Tilelink.scala:276:32] .io_ingress_0_flit_bits_egress_id (_nif_master_io_flits_a_bits_egress_id), // @[Tilelink.scala:276:32] .io_egress_22_flit_ready (_nif_slave_4_io_flits_e_ready), // @[Tilelink.scala:303:31] .io_egress_22_flit_valid (_noc_io_egress_22_flit_valid), .io_egress_22_flit_bits_head (_noc_io_egress_22_flit_bits_head), .io_egress_22_flit_bits_tail (_noc_io_egress_22_flit_bits_tail), .io_egress_21_flit_ready (_nif_slave_4_io_flits_c_ready), // @[Tilelink.scala:303:31] .io_egress_21_flit_valid (_noc_io_egress_21_flit_valid), .io_egress_21_flit_bits_head (_noc_io_egress_21_flit_bits_head), .io_egress_21_flit_bits_tail (_noc_io_egress_21_flit_bits_tail), .io_egress_20_flit_ready (_nif_slave_4_io_flits_a_ready), // @[Tilelink.scala:303:31] .io_egress_20_flit_valid (_noc_io_egress_20_flit_valid), .io_egress_20_flit_bits_head (_noc_io_egress_20_flit_bits_head), .io_egress_20_flit_bits_tail (_noc_io_egress_20_flit_bits_tail), .io_egress_20_flit_bits_payload (_noc_io_egress_20_flit_bits_payload), .io_egress_19_flit_ready (_nif_slave_3_io_flits_e_ready), // @[Tilelink.scala:303:31] .io_egress_19_flit_valid (_noc_io_egress_19_flit_valid), .io_egress_19_flit_bits_head (_noc_io_egress_19_flit_bits_head), .io_egress_19_flit_bits_tail (_noc_io_egress_19_flit_bits_tail), .io_egress_18_flit_ready (_nif_slave_3_io_flits_c_ready), // @[Tilelink.scala:303:31] .io_egress_18_flit_valid (_noc_io_egress_18_flit_valid), .io_egress_18_flit_bits_head (_noc_io_egress_18_flit_bits_head), .io_egress_18_flit_bits_tail (_noc_io_egress_18_flit_bits_tail), .io_egress_17_flit_ready (_nif_slave_3_io_flits_a_ready), // @[Tilelink.scala:303:31] .io_egress_17_flit_valid (_noc_io_egress_17_flit_valid), .io_egress_17_flit_bits_head (_noc_io_egress_17_flit_bits_head), .io_egress_17_flit_bits_tail (_noc_io_egress_17_flit_bits_tail), .io_egress_17_flit_bits_payload (_noc_io_egress_17_flit_bits_payload), .io_egress_16_flit_ready (_nif_slave_2_io_flits_e_ready), // @[Tilelink.scala:303:31] .io_egress_16_flit_valid (_noc_io_egress_16_flit_valid), .io_egress_16_flit_bits_head (_noc_io_egress_16_flit_bits_head), .io_egress_16_flit_bits_tail (_noc_io_egress_16_flit_bits_tail), .io_egress_15_flit_ready (_nif_slave_2_io_flits_c_ready), // @[Tilelink.scala:303:31] .io_egress_15_flit_valid (_noc_io_egress_15_flit_valid), .io_egress_15_flit_bits_head (_noc_io_egress_15_flit_bits_head), .io_egress_15_flit_bits_tail (_noc_io_egress_15_flit_bits_tail), .io_egress_14_flit_ready (_nif_slave_2_io_flits_a_ready), // @[Tilelink.scala:303:31] .io_egress_14_flit_valid (_noc_io_egress_14_flit_valid), .io_egress_14_flit_bits_head (_noc_io_egress_14_flit_bits_head), .io_egress_14_flit_bits_tail (_noc_io_egress_14_flit_bits_tail), .io_egress_14_flit_bits_payload (_noc_io_egress_14_flit_bits_payload), .io_egress_13_flit_ready (_nif_slave_1_io_flits_e_ready), // @[Tilelink.scala:303:31] .io_egress_13_flit_valid (_noc_io_egress_13_flit_valid), .io_egress_13_flit_bits_head (_noc_io_egress_13_flit_bits_head), .io_egress_13_flit_bits_tail (_noc_io_egress_13_flit_bits_tail), .io_egress_12_flit_ready (_nif_slave_1_io_flits_c_ready), // @[Tilelink.scala:303:31] .io_egress_12_flit_valid (_noc_io_egress_12_flit_valid), .io_egress_12_flit_bits_head (_noc_io_egress_12_flit_bits_head), .io_egress_12_flit_bits_tail (_noc_io_egress_12_flit_bits_tail), .io_egress_11_flit_ready (_nif_slave_1_io_flits_a_ready), // @[Tilelink.scala:303:31] .io_egress_11_flit_valid (_noc_io_egress_11_flit_valid), .io_egress_11_flit_bits_head (_noc_io_egress_11_flit_bits_head), .io_egress_11_flit_bits_tail (_noc_io_egress_11_flit_bits_tail), .io_egress_11_flit_bits_payload (_noc_io_egress_11_flit_bits_payload), .io_egress_10_flit_ready (_nif_slave_io_flits_e_ready), // @[Tilelink.scala:303:31] .io_egress_10_flit_valid (_noc_io_egress_10_flit_valid), .io_egress_10_flit_bits_head (_noc_io_egress_10_flit_bits_head), .io_egress_10_flit_bits_tail (_noc_io_egress_10_flit_bits_tail), .io_egress_9_flit_ready (_nif_slave_io_flits_c_ready), // @[Tilelink.scala:303:31] .io_egress_9_flit_valid (_noc_io_egress_9_flit_valid), .io_egress_9_flit_bits_head (_noc_io_egress_9_flit_bits_head), .io_egress_9_flit_bits_tail (_noc_io_egress_9_flit_bits_tail), .io_egress_8_flit_ready (_nif_slave_io_flits_a_ready), // @[Tilelink.scala:303:31] .io_egress_8_flit_valid (_noc_io_egress_8_flit_valid), .io_egress_8_flit_bits_head (_noc_io_egress_8_flit_bits_head), .io_egress_8_flit_bits_tail (_noc_io_egress_8_flit_bits_tail), .io_egress_8_flit_bits_payload (_noc_io_egress_8_flit_bits_payload), .io_egress_7_flit_ready (_nif_master_3_io_flits_d_ready), // @[Tilelink.scala:276:32] .io_egress_7_flit_valid (_noc_io_egress_7_flit_valid), .io_egress_7_flit_bits_head (_noc_io_egress_7_flit_bits_head), .io_egress_7_flit_bits_tail (_noc_io_egress_7_flit_bits_tail), .io_egress_7_flit_bits_payload (_noc_io_egress_7_flit_bits_payload), .io_egress_6_flit_ready (_nif_master_3_io_flits_b_ready), // @[Tilelink.scala:276:32] .io_egress_6_flit_valid (_noc_io_egress_6_flit_valid), .io_egress_6_flit_bits_head (_noc_io_egress_6_flit_bits_head), .io_egress_6_flit_bits_tail (_noc_io_egress_6_flit_bits_tail), .io_egress_5_flit_ready (_nif_master_2_io_flits_d_ready), // @[Tilelink.scala:276:32] .io_egress_5_flit_valid (_noc_io_egress_5_flit_valid), .io_egress_5_flit_bits_head (_noc_io_egress_5_flit_bits_head), .io_egress_5_flit_bits_tail (_noc_io_egress_5_flit_bits_tail), .io_egress_5_flit_bits_payload (_noc_io_egress_5_flit_bits_payload), .io_egress_4_flit_ready (_nif_master_2_io_flits_b_ready), // @[Tilelink.scala:276:32] .io_egress_4_flit_valid (_noc_io_egress_4_flit_valid), .io_egress_4_flit_bits_head (_noc_io_egress_4_flit_bits_head), .io_egress_4_flit_bits_tail (_noc_io_egress_4_flit_bits_tail), .io_egress_3_flit_ready (_nif_master_1_io_flits_d_ready), // @[Tilelink.scala:276:32] .io_egress_3_flit_valid (_noc_io_egress_3_flit_valid), .io_egress_3_flit_bits_head (_noc_io_egress_3_flit_bits_head), .io_egress_3_flit_bits_tail (_noc_io_egress_3_flit_bits_tail), .io_egress_3_flit_bits_payload (_noc_io_egress_3_flit_bits_payload), .io_egress_2_flit_ready (_nif_master_1_io_flits_b_ready), // @[Tilelink.scala:276:32] .io_egress_2_flit_valid (_noc_io_egress_2_flit_valid), .io_egress_2_flit_bits_head (_noc_io_egress_2_flit_bits_head), .io_egress_2_flit_bits_tail (_noc_io_egress_2_flit_bits_tail), .io_egress_1_flit_ready (_nif_master_io_flits_d_ready), // @[Tilelink.scala:276:32] .io_egress_1_flit_valid (_noc_io_egress_1_flit_valid), .io_egress_1_flit_bits_head (_noc_io_egress_1_flit_bits_head), .io_egress_1_flit_bits_tail (_noc_io_egress_1_flit_bits_tail), .io_egress_1_flit_bits_payload (_noc_io_egress_1_flit_bits_payload), .io_egress_0_flit_ready (_nif_master_io_flits_b_ready), // @[Tilelink.scala:276:32] .io_egress_0_flit_valid (_noc_io_egress_0_flit_valid), .io_egress_0_flit_bits_head (_noc_io_egress_0_flit_bits_head), .io_egress_0_flit_bits_tail (_noc_io_egress_0_flit_bits_tail), .io_router_clocks_0_clock (clock), .io_router_clocks_0_reset (reset), .io_router_clocks_1_clock (clock), .io_router_clocks_1_reset (reset), .io_router_clocks_2_clock (clock), .io_router_clocks_2_reset (reset), .io_router_clocks_3_clock (clock), .io_router_clocks_3_reset (reset), .io_router_clocks_4_clock (clock), .io_router_clocks_4_reset (reset), .io_router_clocks_5_clock (clock), .io_router_clocks_5_reset (reset), .io_router_clocks_6_clock (clock), .io_router_clocks_6_reset (reset), .io_router_clocks_7_clock (clock), .io_router_clocks_7_reset (reset), .io_router_clocks_8_clock (clock), .io_router_clocks_8_reset (reset), .io_router_clocks_9_clock (clock), .io_router_clocks_9_reset (reset), .io_router_clocks_10_clock (clock), .io_router_clocks_10_reset (reset), .io_router_clocks_11_clock (clock), .io_router_clocks_11_reset (reset), .io_router_clocks_12_clock (clock), .io_router_clocks_12_reset (reset), .io_router_clocks_13_clock (clock), .io_router_clocks_13_reset (reset), .io_router_clocks_14_clock (clock), .io_router_clocks_14_reset (reset), .io_router_clocks_15_clock (clock), .io_router_clocks_15_reset (reset) ); // @[Protocol.scala:116:19] TLMasterToNoC_10 nif_master ( // @[Tilelink.scala:276:32] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_in_0_a_ready), .io_tilelink_a_valid (io_protocol_0_in_0_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_in_0_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_in_0_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_in_0_a_bits_size), .io_tilelink_a_bits_source ({2'h0, io_protocol_0_in_0_a_bits_source}), // @[Tilelink.scala:238:32, :303:31] .io_tilelink_a_bits_address (io_protocol_0_in_0_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_in_0_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_in_0_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_in_0_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_in_0_d_ready), .io_tilelink_d_valid (io_protocol_0_in_0_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_in_0_d_bits_opcode), .io_tilelink_d_bits_param (io_protocol_0_in_0_d_bits_param), .io_tilelink_d_bits_size (io_protocol_0_in_0_d_bits_size), .io_tilelink_d_bits_source (_nif_master_io_tilelink_d_bits_source), .io_tilelink_d_bits_sink (io_protocol_0_in_0_d_bits_sink), .io_tilelink_d_bits_denied (io_protocol_0_in_0_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_in_0_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_in_0_d_bits_corrupt), .io_flits_a_ready (_noc_io_ingress_0_flit_ready), // @[Protocol.scala:116:19] .io_flits_a_valid (_nif_master_io_flits_a_valid), .io_flits_a_bits_head (_nif_master_io_flits_a_bits_head), .io_flits_a_bits_tail (_nif_master_io_flits_a_bits_tail), .io_flits_a_bits_payload (_nif_master_io_flits_a_bits_payload), .io_flits_a_bits_egress_id (_nif_master_io_flits_a_bits_egress_id), .io_flits_b_ready (_nif_master_io_flits_b_ready), .io_flits_b_valid (_noc_io_egress_0_flit_valid), // @[Protocol.scala:116:19] .io_flits_b_bits_head (_noc_io_egress_0_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_b_bits_tail (_noc_io_egress_0_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_nif_master_io_flits_d_ready), .io_flits_d_valid (_noc_io_egress_1_flit_valid), // @[Protocol.scala:116:19] .io_flits_d_bits_head (_noc_io_egress_1_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_d_bits_tail (_noc_io_egress_1_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_bits_payload (_noc_io_egress_1_flit_bits_payload) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:276:32] TLMasterToNoC_11 nif_master_1 ( // @[Tilelink.scala:276:32] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_in_1_a_ready), .io_tilelink_a_valid (io_protocol_0_in_1_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_in_1_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_in_1_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_in_1_a_bits_size), .io_tilelink_a_bits_source ({2'h0, io_protocol_0_in_1_a_bits_source}), // @[Tilelink.scala:238:32, :303:31] .io_tilelink_a_bits_address (io_protocol_0_in_1_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_in_1_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_in_1_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_in_1_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_in_1_d_ready), .io_tilelink_d_valid (io_protocol_0_in_1_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_in_1_d_bits_opcode), .io_tilelink_d_bits_param (io_protocol_0_in_1_d_bits_param), .io_tilelink_d_bits_size (io_protocol_0_in_1_d_bits_size), .io_tilelink_d_bits_source (_nif_master_1_io_tilelink_d_bits_source), .io_tilelink_d_bits_sink (io_protocol_0_in_1_d_bits_sink), .io_tilelink_d_bits_denied (io_protocol_0_in_1_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_in_1_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_in_1_d_bits_corrupt), .io_flits_a_ready (_noc_io_ingress_3_flit_ready), // @[Protocol.scala:116:19] .io_flits_a_valid (_nif_master_1_io_flits_a_valid), .io_flits_a_bits_head (_nif_master_1_io_flits_a_bits_head), .io_flits_a_bits_tail (_nif_master_1_io_flits_a_bits_tail), .io_flits_a_bits_payload (_nif_master_1_io_flits_a_bits_payload), .io_flits_a_bits_egress_id (_nif_master_1_io_flits_a_bits_egress_id), .io_flits_b_ready (_nif_master_1_io_flits_b_ready), .io_flits_b_valid (_noc_io_egress_2_flit_valid), // @[Protocol.scala:116:19] .io_flits_b_bits_head (_noc_io_egress_2_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_b_bits_tail (_noc_io_egress_2_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_nif_master_1_io_flits_d_ready), .io_flits_d_valid (_noc_io_egress_3_flit_valid), // @[Protocol.scala:116:19] .io_flits_d_bits_head (_noc_io_egress_3_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_d_bits_tail (_noc_io_egress_3_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_bits_payload (_noc_io_egress_3_flit_bits_payload) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:276:32] TLMasterToNoC_12 nif_master_2 ( // @[Tilelink.scala:276:32] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_in_2_a_ready), .io_tilelink_a_valid (io_protocol_0_in_2_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_in_2_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_in_2_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_in_2_a_bits_size), .io_tilelink_a_bits_source ({2'h0, io_protocol_0_in_2_a_bits_source}), // @[Tilelink.scala:238:32, :303:31] .io_tilelink_a_bits_address (io_protocol_0_in_2_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_in_2_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_in_2_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_in_2_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_in_2_d_ready), .io_tilelink_d_valid (io_protocol_0_in_2_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_in_2_d_bits_opcode), .io_tilelink_d_bits_param (io_protocol_0_in_2_d_bits_param), .io_tilelink_d_bits_size (io_protocol_0_in_2_d_bits_size), .io_tilelink_d_bits_source (_nif_master_2_io_tilelink_d_bits_source), .io_tilelink_d_bits_sink (io_protocol_0_in_2_d_bits_sink), .io_tilelink_d_bits_denied (io_protocol_0_in_2_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_in_2_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_in_2_d_bits_corrupt), .io_flits_a_ready (_noc_io_ingress_6_flit_ready), // @[Protocol.scala:116:19] .io_flits_a_valid (_nif_master_2_io_flits_a_valid), .io_flits_a_bits_head (_nif_master_2_io_flits_a_bits_head), .io_flits_a_bits_tail (_nif_master_2_io_flits_a_bits_tail), .io_flits_a_bits_payload (_nif_master_2_io_flits_a_bits_payload), .io_flits_a_bits_egress_id (_nif_master_2_io_flits_a_bits_egress_id), .io_flits_b_ready (_nif_master_2_io_flits_b_ready), .io_flits_b_valid (_noc_io_egress_4_flit_valid), // @[Protocol.scala:116:19] .io_flits_b_bits_head (_noc_io_egress_4_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_b_bits_tail (_noc_io_egress_4_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_nif_master_2_io_flits_d_ready), .io_flits_d_valid (_noc_io_egress_5_flit_valid), // @[Protocol.scala:116:19] .io_flits_d_bits_head (_noc_io_egress_5_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_d_bits_tail (_noc_io_egress_5_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_bits_payload (_noc_io_egress_5_flit_bits_payload) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:276:32] TLMasterToNoC_13 nif_master_3 ( // @[Tilelink.scala:276:32] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_in_3_a_ready), .io_tilelink_a_valid (io_protocol_0_in_3_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_in_3_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_in_3_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_in_3_a_bits_size), .io_tilelink_a_bits_source ({2'h0, io_protocol_0_in_3_a_bits_source}), // @[Tilelink.scala:238:32, :303:31] .io_tilelink_a_bits_address (io_protocol_0_in_3_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_in_3_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_in_3_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_in_3_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_in_3_d_ready), .io_tilelink_d_valid (io_protocol_0_in_3_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_in_3_d_bits_opcode), .io_tilelink_d_bits_param (io_protocol_0_in_3_d_bits_param), .io_tilelink_d_bits_size (io_protocol_0_in_3_d_bits_size), .io_tilelink_d_bits_source (_nif_master_3_io_tilelink_d_bits_source), .io_tilelink_d_bits_sink (io_protocol_0_in_3_d_bits_sink), .io_tilelink_d_bits_denied (io_protocol_0_in_3_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_in_3_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_in_3_d_bits_corrupt), .io_flits_a_ready (_noc_io_ingress_9_flit_ready), // @[Protocol.scala:116:19] .io_flits_a_valid (_nif_master_3_io_flits_a_valid), .io_flits_a_bits_head (_nif_master_3_io_flits_a_bits_head), .io_flits_a_bits_tail (_nif_master_3_io_flits_a_bits_tail), .io_flits_a_bits_payload (_nif_master_3_io_flits_a_bits_payload), .io_flits_a_bits_egress_id (_nif_master_3_io_flits_a_bits_egress_id), .io_flits_b_ready (_nif_master_3_io_flits_b_ready), .io_flits_b_valid (_noc_io_egress_6_flit_valid), // @[Protocol.scala:116:19] .io_flits_b_bits_head (_noc_io_egress_6_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_b_bits_tail (_noc_io_egress_6_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_nif_master_3_io_flits_d_ready), .io_flits_d_valid (_noc_io_egress_7_flit_valid), // @[Protocol.scala:116:19] .io_flits_d_bits_head (_noc_io_egress_7_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_d_bits_tail (_noc_io_egress_7_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_bits_payload (_noc_io_egress_7_flit_bits_payload) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:276:32] TLSlaveToNoC_13 nif_slave ( // @[Tilelink.scala:303:31] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_out_0_a_ready), .io_tilelink_a_valid (io_protocol_0_out_0_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_out_0_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_out_0_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_out_0_a_bits_size), .io_tilelink_a_bits_source (io_protocol_0_out_0_a_bits_source), .io_tilelink_a_bits_address (io_protocol_0_out_0_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_out_0_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_out_0_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_out_0_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_out_0_d_ready), .io_tilelink_d_valid (io_protocol_0_out_0_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_out_0_d_bits_opcode), .io_tilelink_d_bits_param (2'h0), // @[Tilelink.scala:303:31] .io_tilelink_d_bits_size (io_protocol_0_out_0_d_bits_size), .io_tilelink_d_bits_source (io_protocol_0_out_0_d_bits_source), .io_tilelink_d_bits_sink (1'h0), // @[Tilelink.scala:276:32, :303:31] .io_tilelink_d_bits_denied (io_protocol_0_out_0_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_out_0_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_out_0_d_bits_corrupt), .io_flits_a_ready (_nif_slave_io_flits_a_ready), .io_flits_a_valid (_noc_io_egress_8_flit_valid), // @[Protocol.scala:116:19] .io_flits_a_bits_head (_noc_io_egress_8_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_a_bits_tail (_noc_io_egress_8_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_a_bits_payload (_noc_io_egress_8_flit_bits_payload), // @[Protocol.scala:116:19] .io_flits_c_ready (_nif_slave_io_flits_c_ready), .io_flits_c_valid (_noc_io_egress_9_flit_valid), // @[Protocol.scala:116:19] .io_flits_c_bits_head (_noc_io_egress_9_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_c_bits_tail (_noc_io_egress_9_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_noc_io_ingress_13_flit_ready), // @[Protocol.scala:116:19] .io_flits_d_valid (_nif_slave_io_flits_d_valid), .io_flits_d_bits_head (_nif_slave_io_flits_d_bits_head), .io_flits_d_bits_tail (_nif_slave_io_flits_d_bits_tail), .io_flits_d_bits_payload (_nif_slave_io_flits_d_bits_payload), .io_flits_d_bits_egress_id (_nif_slave_io_flits_d_bits_egress_id), .io_flits_e_ready (_nif_slave_io_flits_e_ready), .io_flits_e_valid (_noc_io_egress_10_flit_valid), // @[Protocol.scala:116:19] .io_flits_e_bits_head (_noc_io_egress_10_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_e_bits_tail (_noc_io_egress_10_flit_bits_tail) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:303:31] TLSlaveToNoC_13 nif_slave_1 ( // @[Tilelink.scala:303:31] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_out_1_a_ready), .io_tilelink_a_valid (io_protocol_0_out_1_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_out_1_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_out_1_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_out_1_a_bits_size), .io_tilelink_a_bits_source (io_protocol_0_out_1_a_bits_source), .io_tilelink_a_bits_address (io_protocol_0_out_1_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_out_1_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_out_1_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_out_1_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_out_1_d_ready), .io_tilelink_d_valid (io_protocol_0_out_1_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_out_1_d_bits_opcode), .io_tilelink_d_bits_param (2'h0), // @[Tilelink.scala:303:31] .io_tilelink_d_bits_size (io_protocol_0_out_1_d_bits_size), .io_tilelink_d_bits_source (io_protocol_0_out_1_d_bits_source), .io_tilelink_d_bits_sink (1'h0), // @[Tilelink.scala:276:32, :303:31] .io_tilelink_d_bits_denied (io_protocol_0_out_1_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_out_1_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_out_1_d_bits_corrupt), .io_flits_a_ready (_nif_slave_1_io_flits_a_ready), .io_flits_a_valid (_noc_io_egress_11_flit_valid), // @[Protocol.scala:116:19] .io_flits_a_bits_head (_noc_io_egress_11_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_a_bits_tail (_noc_io_egress_11_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_a_bits_payload (_noc_io_egress_11_flit_bits_payload), // @[Protocol.scala:116:19] .io_flits_c_ready (_nif_slave_1_io_flits_c_ready), .io_flits_c_valid (_noc_io_egress_12_flit_valid), // @[Protocol.scala:116:19] .io_flits_c_bits_head (_noc_io_egress_12_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_c_bits_tail (_noc_io_egress_12_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_noc_io_ingress_15_flit_ready), // @[Protocol.scala:116:19] .io_flits_d_valid (_nif_slave_1_io_flits_d_valid), .io_flits_d_bits_head (_nif_slave_1_io_flits_d_bits_head), .io_flits_d_bits_tail (_nif_slave_1_io_flits_d_bits_tail), .io_flits_d_bits_payload (_nif_slave_1_io_flits_d_bits_payload), .io_flits_d_bits_egress_id (_nif_slave_1_io_flits_d_bits_egress_id), .io_flits_e_ready (_nif_slave_1_io_flits_e_ready), .io_flits_e_valid (_noc_io_egress_13_flit_valid), // @[Protocol.scala:116:19] .io_flits_e_bits_head (_noc_io_egress_13_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_e_bits_tail (_noc_io_egress_13_flit_bits_tail) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:303:31] TLSlaveToNoC_13 nif_slave_2 ( // @[Tilelink.scala:303:31] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_out_2_a_ready), .io_tilelink_a_valid (io_protocol_0_out_2_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_out_2_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_out_2_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_out_2_a_bits_size), .io_tilelink_a_bits_source (io_protocol_0_out_2_a_bits_source), .io_tilelink_a_bits_address (io_protocol_0_out_2_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_out_2_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_out_2_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_out_2_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_out_2_d_ready), .io_tilelink_d_valid (io_protocol_0_out_2_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_out_2_d_bits_opcode), .io_tilelink_d_bits_param (2'h0), // @[Tilelink.scala:303:31] .io_tilelink_d_bits_size (io_protocol_0_out_2_d_bits_size), .io_tilelink_d_bits_source (io_protocol_0_out_2_d_bits_source), .io_tilelink_d_bits_sink (1'h0), // @[Tilelink.scala:276:32, :303:31] .io_tilelink_d_bits_denied (io_protocol_0_out_2_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_out_2_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_out_2_d_bits_corrupt), .io_flits_a_ready (_nif_slave_2_io_flits_a_ready), .io_flits_a_valid (_noc_io_egress_14_flit_valid), // @[Protocol.scala:116:19] .io_flits_a_bits_head (_noc_io_egress_14_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_a_bits_tail (_noc_io_egress_14_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_a_bits_payload (_noc_io_egress_14_flit_bits_payload), // @[Protocol.scala:116:19] .io_flits_c_ready (_nif_slave_2_io_flits_c_ready), .io_flits_c_valid (_noc_io_egress_15_flit_valid), // @[Protocol.scala:116:19] .io_flits_c_bits_head (_noc_io_egress_15_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_c_bits_tail (_noc_io_egress_15_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_noc_io_ingress_17_flit_ready), // @[Protocol.scala:116:19] .io_flits_d_valid (_nif_slave_2_io_flits_d_valid), .io_flits_d_bits_head (_nif_slave_2_io_flits_d_bits_head), .io_flits_d_bits_tail (_nif_slave_2_io_flits_d_bits_tail), .io_flits_d_bits_payload (_nif_slave_2_io_flits_d_bits_payload), .io_flits_d_bits_egress_id (_nif_slave_2_io_flits_d_bits_egress_id), .io_flits_e_ready (_nif_slave_2_io_flits_e_ready), .io_flits_e_valid (_noc_io_egress_16_flit_valid), // @[Protocol.scala:116:19] .io_flits_e_bits_head (_noc_io_egress_16_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_e_bits_tail (_noc_io_egress_16_flit_bits_tail) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:303:31] TLSlaveToNoC_13 nif_slave_3 ( // @[Tilelink.scala:303:31] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_out_3_a_ready), .io_tilelink_a_valid (io_protocol_0_out_3_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_out_3_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_out_3_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_out_3_a_bits_size), .io_tilelink_a_bits_source (io_protocol_0_out_3_a_bits_source), .io_tilelink_a_bits_address (io_protocol_0_out_3_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_out_3_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_out_3_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_out_3_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_out_3_d_ready), .io_tilelink_d_valid (io_protocol_0_out_3_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_out_3_d_bits_opcode), .io_tilelink_d_bits_param (2'h0), // @[Tilelink.scala:303:31] .io_tilelink_d_bits_size (io_protocol_0_out_3_d_bits_size), .io_tilelink_d_bits_source (io_protocol_0_out_3_d_bits_source), .io_tilelink_d_bits_sink (1'h0), // @[Tilelink.scala:276:32, :303:31] .io_tilelink_d_bits_denied (io_protocol_0_out_3_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_out_3_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_out_3_d_bits_corrupt), .io_flits_a_ready (_nif_slave_3_io_flits_a_ready), .io_flits_a_valid (_noc_io_egress_17_flit_valid), // @[Protocol.scala:116:19] .io_flits_a_bits_head (_noc_io_egress_17_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_a_bits_tail (_noc_io_egress_17_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_a_bits_payload (_noc_io_egress_17_flit_bits_payload), // @[Protocol.scala:116:19] .io_flits_c_ready (_nif_slave_3_io_flits_c_ready), .io_flits_c_valid (_noc_io_egress_18_flit_valid), // @[Protocol.scala:116:19] .io_flits_c_bits_head (_noc_io_egress_18_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_c_bits_tail (_noc_io_egress_18_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_noc_io_ingress_19_flit_ready), // @[Protocol.scala:116:19] .io_flits_d_valid (_nif_slave_3_io_flits_d_valid), .io_flits_d_bits_head (_nif_slave_3_io_flits_d_bits_head), .io_flits_d_bits_tail (_nif_slave_3_io_flits_d_bits_tail), .io_flits_d_bits_payload (_nif_slave_3_io_flits_d_bits_payload), .io_flits_d_bits_egress_id (_nif_slave_3_io_flits_d_bits_egress_id), .io_flits_e_ready (_nif_slave_3_io_flits_e_ready), .io_flits_e_valid (_noc_io_egress_19_flit_valid), // @[Protocol.scala:116:19] .io_flits_e_bits_head (_noc_io_egress_19_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_e_bits_tail (_noc_io_egress_19_flit_bits_tail) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:303:31] TLSlaveToNoC_13 nif_slave_4 ( // @[Tilelink.scala:303:31] .clock (clock), .reset (reset), .io_tilelink_a_ready (io_protocol_0_out_4_a_ready), .io_tilelink_a_valid (io_protocol_0_out_4_a_valid), .io_tilelink_a_bits_opcode (io_protocol_0_out_4_a_bits_opcode), .io_tilelink_a_bits_param (io_protocol_0_out_4_a_bits_param), .io_tilelink_a_bits_size (io_protocol_0_out_4_a_bits_size), .io_tilelink_a_bits_source (io_protocol_0_out_4_a_bits_source), .io_tilelink_a_bits_address (_nif_slave_4_io_tilelink_a_bits_address), .io_tilelink_a_bits_mask (io_protocol_0_out_4_a_bits_mask), .io_tilelink_a_bits_data (io_protocol_0_out_4_a_bits_data), .io_tilelink_a_bits_corrupt (io_protocol_0_out_4_a_bits_corrupt), .io_tilelink_d_ready (io_protocol_0_out_4_d_ready), .io_tilelink_d_valid (io_protocol_0_out_4_d_valid), .io_tilelink_d_bits_opcode (io_protocol_0_out_4_d_bits_opcode), .io_tilelink_d_bits_param (io_protocol_0_out_4_d_bits_param), .io_tilelink_d_bits_size (io_protocol_0_out_4_d_bits_size), .io_tilelink_d_bits_source (io_protocol_0_out_4_d_bits_source), .io_tilelink_d_bits_sink (io_protocol_0_out_4_d_bits_sink), .io_tilelink_d_bits_denied (io_protocol_0_out_4_d_bits_denied), .io_tilelink_d_bits_data (io_protocol_0_out_4_d_bits_data), .io_tilelink_d_bits_corrupt (io_protocol_0_out_4_d_bits_corrupt), .io_flits_a_ready (_nif_slave_4_io_flits_a_ready), .io_flits_a_valid (_noc_io_egress_20_flit_valid), // @[Protocol.scala:116:19] .io_flits_a_bits_head (_noc_io_egress_20_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_a_bits_tail (_noc_io_egress_20_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_a_bits_payload (_noc_io_egress_20_flit_bits_payload), // @[Protocol.scala:116:19] .io_flits_c_ready (_nif_slave_4_io_flits_c_ready), .io_flits_c_valid (_noc_io_egress_21_flit_valid), // @[Protocol.scala:116:19] .io_flits_c_bits_head (_noc_io_egress_21_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_c_bits_tail (_noc_io_egress_21_flit_bits_tail), // @[Protocol.scala:116:19] .io_flits_d_ready (_noc_io_ingress_21_flit_ready), // @[Protocol.scala:116:19] .io_flits_d_valid (_nif_slave_4_io_flits_d_valid), .io_flits_d_bits_head (_nif_slave_4_io_flits_d_bits_head), .io_flits_d_bits_tail (_nif_slave_4_io_flits_d_bits_tail), .io_flits_d_bits_payload (_nif_slave_4_io_flits_d_bits_payload), .io_flits_d_bits_egress_id (_nif_slave_4_io_flits_d_bits_egress_id), .io_flits_e_ready (_nif_slave_4_io_flits_e_ready), .io_flits_e_valid (_noc_io_egress_22_flit_valid), // @[Protocol.scala:116:19] .io_flits_e_bits_head (_noc_io_egress_22_flit_bits_head), // @[Protocol.scala:116:19] .io_flits_e_bits_tail (_noc_io_egress_22_flit_bits_tail) // @[Protocol.scala:116:19] ); // @[Tilelink.scala:303:31] assign io_protocol_0_in_3_d_bits_source = _nif_master_3_io_tilelink_d_bits_source[3:0]; // @[Tilelink.scala:238:32, :276:32] assign io_protocol_0_in_2_d_bits_source = _nif_master_2_io_tilelink_d_bits_source[3:0]; // @[Tilelink.scala:238:32, :276:32] assign io_protocol_0_in_1_d_bits_source = _nif_master_1_io_tilelink_d_bits_source[3:0]; // @[Tilelink.scala:238:32, :276:32] assign io_protocol_0_in_0_d_bits_source = _nif_master_io_tilelink_d_bits_source[3:0]; // @[Tilelink.scala:238:32, :276:32] assign io_protocol_0_out_4_a_bits_address = _nif_slave_4_io_tilelink_a_bits_address[27:0]; // @[Tilelink.scala:238:32, :303:31] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_141 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_249 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_141( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_249 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_5 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0h80))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 64, 39) node _adjustedSig_T_1 = bits(io.in.sig, 38, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_5( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [9:0] _sAdjustedExp_T = {io_in_sExp_0[8], io_in_sExp_0} + 10'h80; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [25:0] _adjustedSig_T = io_in_sig_0[64:39]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [38:0] _adjustedSig_T_1 = io_in_sig_0[38:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_15 = {25'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_204 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_204( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_128 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_128( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module HellaFlowQueue_4 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<2>}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<2>}, count : UInt<7>} wire do_flow : UInt<1> node _do_enq_T = and(io.enq.ready, io.enq.valid) node _do_enq_T_1 = eq(do_flow, UInt<1>(0h0)) node do_enq = and(_do_enq_T, _do_enq_T_1) node _do_deq_T = and(io.deq.ready, io.deq.valid) node _do_deq_T_1 = eq(do_flow, UInt<1>(0h0)) node do_deq = and(_do_deq_T, _do_deq_T_1) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset enq_ptr : UInt<6>, clock, reset, UInt<6>(0h0) wire enq_ptr_wrap : UInt<1> connect enq_ptr_wrap, UInt<1>(0h0) when do_enq : node enq_ptr_wrap_wrap = eq(enq_ptr, UInt<6>(0h3f)) node _enq_ptr_wrap_value_T = add(enq_ptr, UInt<1>(0h1)) node _enq_ptr_wrap_value_T_1 = tail(_enq_ptr_wrap_value_T, 1) connect enq_ptr, _enq_ptr_wrap_value_T_1 connect enq_ptr_wrap, enq_ptr_wrap_wrap regreset deq_ptr : UInt<6>, clock, reset, UInt<6>(0h0) wire deq_done : UInt<1> connect deq_done, UInt<1>(0h0) when do_deq : node wrap_wrap = eq(deq_ptr, UInt<6>(0h3f)) node _wrap_value_T = add(deq_ptr, UInt<1>(0h1)) node _wrap_value_T_1 = tail(_wrap_value_T, 1) connect deq_ptr, _wrap_value_T_1 connect deq_done, wrap_wrap node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node ptr_match = eq(enq_ptr, deq_ptr) node _empty_T = eq(maybe_full, UInt<1>(0h0)) node empty = and(ptr_match, _empty_T) node full = and(ptr_match, maybe_full) node _atLeastTwo_T = sub(enq_ptr, deq_ptr) node _atLeastTwo_T_1 = tail(_atLeastTwo_T, 1) node _atLeastTwo_T_2 = geq(_atLeastTwo_T_1, UInt<2>(0h2)) node atLeastTwo = or(full, _atLeastTwo_T_2) node _do_flow_T = and(empty, io.deq.ready) connect do_flow, _do_flow_T smem ram : UInt<2> [64] when do_enq : write mport MPORT = ram[enq_ptr], clock connect MPORT, io.enq.bits node _ren_T = eq(io.deq.valid, UInt<1>(0h0)) node _ren_T_1 = eq(empty, UInt<1>(0h0)) node _ren_T_2 = and(_ren_T, _ren_T_1) node _ren_T_3 = or(atLeastTwo, _ren_T_2) node ren = and(io.deq.ready, _ren_T_3) node _raddr_T = add(deq_ptr, UInt<1>(0h1)) node _raddr_T_1 = tail(_raddr_T, 1) node _raddr_T_2 = mux(deq_done, UInt<1>(0h0), _raddr_T_1) node raddr = mux(io.deq.valid, _raddr_T_2, deq_ptr) reg ram_out_valid : UInt<1>, clock connect ram_out_valid, ren node _io_deq_valid_T = mux(empty, io.enq.valid, ram_out_valid) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire _io_deq_bits_WIRE : UInt<6> invalidate _io_deq_bits_WIRE when ren : connect _io_deq_bits_WIRE, raddr read mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock node _io_deq_bits_T = mux(empty, io.enq.bits, io_deq_bits_MPORT) connect io.deq.bits, _io_deq_bits_T invalidate io.count
module HellaFlowQueue_4( // @[HellaQueue.scala:8:7] input clock, // @[HellaQueue.scala:8:7] input reset, // @[HellaQueue.scala:8:7] output io_enq_ready, // @[HellaQueue.scala:9:14] input io_enq_valid, // @[HellaQueue.scala:9:14] input [1:0] io_enq_bits, // @[HellaQueue.scala:9:14] input io_deq_ready, // @[HellaQueue.scala:9:14] output io_deq_valid, // @[HellaQueue.scala:9:14] output [1:0] io_deq_bits // @[HellaQueue.scala:9:14] ); wire [1:0] _ram_R0_data; // @[HellaQueue.scala:27:24] wire io_enq_valid_0 = io_enq_valid; // @[HellaQueue.scala:8:7] wire [1:0] io_enq_bits_0 = io_enq_bits; // @[HellaQueue.scala:8:7] wire io_deq_ready_0 = io_deq_ready; // @[HellaQueue.scala:8:7] wire [6:0] io_count = 7'h0; // @[HellaQueue.scala:8:7] wire _io_enq_ready_T; // @[HellaQueue.scala:37:19] wire _io_deq_valid_T; // @[HellaQueue.scala:36:22] wire [1:0] _io_deq_bits_T; // @[HellaQueue.scala:38:21] wire io_enq_ready_0; // @[HellaQueue.scala:8:7] wire io_deq_valid_0; // @[HellaQueue.scala:8:7] wire [1:0] io_deq_bits_0; // @[HellaQueue.scala:8:7] wire _do_flow_T; // @[HellaQueue.scala:25:20] wire do_flow; // @[HellaQueue.scala:12:21] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_1 = ~do_flow; // @[HellaQueue.scala:12:21, :13:31] wire do_enq = _do_enq_T & _do_enq_T_1; // @[Decoupled.scala:51:35] wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _do_deq_T_1 = ~do_flow; // @[HellaQueue.scala:12:21, :13:31, :14:31] wire do_deq = _do_deq_T & _do_deq_T_1; // @[Decoupled.scala:51:35] reg maybe_full; // @[HellaQueue.scala:16:27] reg [5:0] enq_ptr; // @[Counter.scala:61:40] wire enq_ptr_wrap; // @[Counter.scala:117:24] wire enq_ptr_wrap_wrap = &enq_ptr; // @[Counter.scala:61:40, :73:24] wire [6:0] _GEN = {1'h0, enq_ptr}; // @[Counter.scala:61:40, :77:24] wire [6:0] _enq_ptr_wrap_value_T = _GEN + 7'h1; // @[Counter.scala:77:24] wire [5:0] _enq_ptr_wrap_value_T_1 = _enq_ptr_wrap_value_T[5:0]; // @[Counter.scala:77:24] assign enq_ptr_wrap = do_enq & enq_ptr_wrap_wrap; // @[Counter.scala:73:24, :117:24, :118:{16,23}] reg [5:0] deq_ptr; // @[Counter.scala:61:40] wire deq_done; // @[Counter.scala:117:24] wire wrap_wrap = &deq_ptr; // @[Counter.scala:61:40, :73:24] wire [6:0] _GEN_0 = {1'h0, deq_ptr}; // @[Counter.scala:61:40, :77:24] wire [6:0] _GEN_1 = _GEN_0 + 7'h1; // @[Counter.scala:77:24] wire [6:0] _wrap_value_T; // @[Counter.scala:77:24] assign _wrap_value_T = _GEN_1; // @[Counter.scala:77:24] wire [6:0] _raddr_T; // @[HellaQueue.scala:33:60] assign _raddr_T = _GEN_1; // @[Counter.scala:77:24] wire [5:0] _wrap_value_T_1 = _wrap_value_T[5:0]; // @[Counter.scala:77:24] assign deq_done = do_deq & wrap_wrap; // @[Counter.scala:73:24, :117:24, :118:{16,23}] wire ptr_match = enq_ptr == deq_ptr; // @[Counter.scala:61:40] wire _empty_T = ~maybe_full; // @[HellaQueue.scala:16:27, :22:28] wire empty = ptr_match & _empty_T; // @[HellaQueue.scala:21:27, :22:{25,28}] wire full = ptr_match & maybe_full; // @[HellaQueue.scala:16:27, :21:27, :23:24] wire [6:0] _atLeastTwo_T = _GEN - _GEN_0; // @[Counter.scala:77:24] wire [5:0] _atLeastTwo_T_1 = _atLeastTwo_T[5:0]; // @[HellaQueue.scala:24:36] wire _atLeastTwo_T_2 = |(_atLeastTwo_T_1[5:1]); // @[HellaQueue.scala:24:{36,46}] wire atLeastTwo = full | _atLeastTwo_T_2; // @[HellaQueue.scala:23:24, :24:{25,46}] assign _do_flow_T = empty & io_deq_ready_0; // @[HellaQueue.scala:8:7, :22:25, :25:20] assign do_flow = _do_flow_T; // @[HellaQueue.scala:12:21, :25:20] wire _ren_T = ~io_deq_valid_0; // @[HellaQueue.scala:8:7, :32:44] wire _ren_T_1 = ~empty; // @[HellaQueue.scala:22:25, :32:61] wire _ren_T_2 = _ren_T & _ren_T_1; // @[HellaQueue.scala:32:{44,58,61}] wire _ren_T_3 = atLeastTwo | _ren_T_2; // @[HellaQueue.scala:24:25, :32:{41,58}] wire ren = io_deq_ready_0 & _ren_T_3; // @[HellaQueue.scala:8:7, :32:{26,41}] wire [5:0] _raddr_T_1 = _raddr_T[5:0]; // @[HellaQueue.scala:33:60] wire [5:0] _raddr_T_2 = deq_done ? 6'h0 : _raddr_T_1; // @[Counter.scala:117:24] wire [5:0] raddr = io_deq_valid_0 ? _raddr_T_2 : deq_ptr; // @[Counter.scala:61:40] wire [5:0] _io_deq_bits_WIRE = raddr; // @[HellaQueue.scala:33:18, :38:50] reg ram_out_valid; // @[HellaQueue.scala:34:30] assign _io_deq_valid_T = empty ? io_enq_valid_0 : ram_out_valid; // @[HellaQueue.scala:8:7, :22:25, :34:30, :36:22] assign io_deq_valid_0 = _io_deq_valid_T; // @[HellaQueue.scala:8:7, :36:22] assign _io_enq_ready_T = ~full; // @[HellaQueue.scala:23:24, :37:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[HellaQueue.scala:8:7, :37:19] assign _io_deq_bits_T = empty ? io_enq_bits_0 : _ram_R0_data; // @[HellaQueue.scala:8:7, :22:25, :27:24, :38:21] assign io_deq_bits_0 = _io_deq_bits_T; // @[HellaQueue.scala:8:7, :38:21] always @(posedge clock) begin // @[HellaQueue.scala:8:7] if (reset) begin // @[HellaQueue.scala:8:7] maybe_full <= 1'h0; // @[HellaQueue.scala:16:27] enq_ptr <= 6'h0; // @[Counter.scala:61:40] deq_ptr <= 6'h0; // @[Counter.scala:61:40] end else begin // @[HellaQueue.scala:8:7] if (~(do_enq == do_deq)) // @[HellaQueue.scala:13:28, :14:28, :16:27, :19:{16,28,41}] maybe_full <= do_enq; // @[HellaQueue.scala:13:28, :16:27] if (do_enq) // @[HellaQueue.scala:13:28] enq_ptr <= _enq_ptr_wrap_value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[HellaQueue.scala:14:28] deq_ptr <= _wrap_value_T_1; // @[Counter.scala:61:40, :77:24] end ram_out_valid <= ren; // @[HellaQueue.scala:32:26, :34:30] always @(posedge) ram_3 ram ( // @[HellaQueue.scala:27:24] .R0_addr (_io_deq_bits_WIRE), // @[HellaQueue.scala:38:50] .R0_en (ren), // @[HellaQueue.scala:32:26] .R0_clk (clock), .R0_data (_ram_R0_data), .W0_addr (enq_ptr), // @[Counter.scala:61:40] .W0_en (do_enq), // @[HellaQueue.scala:13:28] .W0_clk (clock), .W0_data (io_enq_bits_0) // @[HellaQueue.scala:8:7] ); // @[HellaQueue.scala:27:24] assign io_enq_ready = io_enq_ready_0; // @[HellaQueue.scala:8:7] assign io_deq_valid = io_deq_valid_0; // @[HellaQueue.scala:8:7] assign io_deq_bits = io_deq_bits_0; // @[HellaQueue.scala:8:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_70 : input clock : Clock input reset : Reset output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}}[8]} cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} [24] wire _heads_WIRE : UInt<5>[8] connect _heads_WIRE[0], UInt<5>(0h0) connect _heads_WIRE[1], UInt<5>(0h0) connect _heads_WIRE[2], UInt<5>(0h0) connect _heads_WIRE[3], UInt<5>(0h4) connect _heads_WIRE[4], UInt<5>(0h8) connect _heads_WIRE[5], UInt<5>(0hc) connect _heads_WIRE[6], UInt<5>(0h10) connect _heads_WIRE[7], UInt<5>(0h14) regreset heads : UInt<5>[8], clock, reset, _heads_WIRE wire _tails_WIRE : UInt<5>[8] connect _tails_WIRE[0], UInt<5>(0h0) connect _tails_WIRE[1], UInt<5>(0h0) connect _tails_WIRE[2], UInt<5>(0h0) connect _tails_WIRE[3], UInt<5>(0h4) connect _tails_WIRE[4], UInt<5>(0h8) connect _tails_WIRE[5], UInt<5>(0hc) connect _tails_WIRE[6], UInt<5>(0h10) connect _tails_WIRE[7], UInt<5>(0h14) regreset tails : UInt<5>[8], clock, reset, _tails_WIRE node empty_0 = eq(heads[0], tails[0]) node empty_1 = eq(heads[1], tails[1]) node empty_2 = eq(heads[2], tails[2]) node empty_3 = eq(heads[3], tails[3]) node empty_4 = eq(heads[4], tails[4]) node empty_5 = eq(heads[5], tails[5]) node empty_6 = eq(heads[6], tails[6]) node empty_7 = eq(heads[7], tails[7]) inst qs_0 of Queue1_BaseFlit_560 connect qs_0.clock, clock connect qs_0.reset, reset inst qs_1 of Queue1_BaseFlit_561 connect qs_1.clock, clock connect qs_1.reset, reset inst qs_2 of Queue1_BaseFlit_562 connect qs_2.clock, clock connect qs_2.reset, reset inst qs_3 of Queue1_BaseFlit_563 connect qs_3.clock, clock connect qs_3.reset, reset inst qs_4 of Queue1_BaseFlit_564 connect qs_4.clock, clock connect qs_4.reset, reset inst qs_5 of Queue1_BaseFlit_565 connect qs_5.clock, clock connect qs_5.reset, reset inst qs_6 of Queue1_BaseFlit_566 connect qs_6.clock, clock connect qs_6.reset, reset inst qs_7 of Queue1_BaseFlit_567 connect qs_7.clock, clock connect qs_7.reset, reset connect qs_0.io.enq.valid, UInt<1>(0h0) connect qs_1.io.enq.valid, UInt<1>(0h0) connect qs_2.io.enq.valid, UInt<1>(0h0) connect qs_3.io.enq.valid, UInt<1>(0h0) connect qs_4.io.enq.valid, UInt<1>(0h0) connect qs_5.io.enq.valid, UInt<1>(0h0) connect qs_6.io.enq.valid, UInt<1>(0h0) connect qs_7.io.enq.valid, UInt<1>(0h0) invalidate qs_0.io.enq.bits.payload invalidate qs_0.io.enq.bits.tail invalidate qs_0.io.enq.bits.head invalidate qs_1.io.enq.bits.payload invalidate qs_1.io.enq.bits.tail invalidate qs_1.io.enq.bits.head invalidate qs_2.io.enq.bits.payload invalidate qs_2.io.enq.bits.tail invalidate qs_2.io.enq.bits.head invalidate qs_3.io.enq.bits.payload invalidate qs_3.io.enq.bits.tail invalidate qs_3.io.enq.bits.head invalidate qs_4.io.enq.bits.payload invalidate qs_4.io.enq.bits.tail invalidate qs_4.io.enq.bits.head invalidate qs_5.io.enq.bits.payload invalidate qs_5.io.enq.bits.tail invalidate qs_5.io.enq.bits.head invalidate qs_6.io.enq.bits.payload invalidate qs_6.io.enq.bits.tail invalidate qs_6.io.enq.bits.head invalidate qs_7.io.enq.bits.payload invalidate qs_7.io.enq.bits.tail invalidate qs_7.io.enq.bits.head node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id) wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} node _direct_to_q_T = bits(vc_sel, 0, 0) node _direct_to_q_T_1 = bits(vc_sel, 1, 1) node _direct_to_q_T_2 = bits(vc_sel, 2, 2) node _direct_to_q_T_3 = bits(vc_sel, 3, 3) node _direct_to_q_T_4 = bits(vc_sel, 4, 4) node _direct_to_q_T_5 = bits(vc_sel, 5, 5) node _direct_to_q_T_6 = bits(vc_sel, 6, 6) node _direct_to_q_T_7 = bits(vc_sel, 7, 7) node _direct_to_q_T_8 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_9 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_10 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_11 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_12 = mux(_direct_to_q_T_4, qs_4.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_13 = mux(_direct_to_q_T_5, qs_5.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_14 = mux(_direct_to_q_T_6, qs_6.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_15 = mux(_direct_to_q_T_7, qs_7.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_16 = or(_direct_to_q_T_8, _direct_to_q_T_9) node _direct_to_q_T_17 = or(_direct_to_q_T_16, _direct_to_q_T_10) node _direct_to_q_T_18 = or(_direct_to_q_T_17, _direct_to_q_T_11) node _direct_to_q_T_19 = or(_direct_to_q_T_18, _direct_to_q_T_12) node _direct_to_q_T_20 = or(_direct_to_q_T_19, _direct_to_q_T_13) node _direct_to_q_T_21 = or(_direct_to_q_T_20, _direct_to_q_T_14) node _direct_to_q_T_22 = or(_direct_to_q_T_21, _direct_to_q_T_15) wire _direct_to_q_WIRE : UInt<1> connect _direct_to_q_WIRE, _direct_to_q_T_22 node _direct_to_q_T_23 = bits(vc_sel, 0, 0) node _direct_to_q_T_24 = bits(vc_sel, 1, 1) node _direct_to_q_T_25 = bits(vc_sel, 2, 2) node _direct_to_q_T_26 = bits(vc_sel, 3, 3) node _direct_to_q_T_27 = bits(vc_sel, 4, 4) node _direct_to_q_T_28 = bits(vc_sel, 5, 5) node _direct_to_q_T_29 = bits(vc_sel, 6, 6) node _direct_to_q_T_30 = bits(vc_sel, 7, 7) node _direct_to_q_T_31 = mux(_direct_to_q_T_23, empty_0, UInt<1>(0h0)) node _direct_to_q_T_32 = mux(_direct_to_q_T_24, empty_1, UInt<1>(0h0)) node _direct_to_q_T_33 = mux(_direct_to_q_T_25, empty_2, UInt<1>(0h0)) node _direct_to_q_T_34 = mux(_direct_to_q_T_26, empty_3, UInt<1>(0h0)) node _direct_to_q_T_35 = mux(_direct_to_q_T_27, empty_4, UInt<1>(0h0)) node _direct_to_q_T_36 = mux(_direct_to_q_T_28, empty_5, UInt<1>(0h0)) node _direct_to_q_T_37 = mux(_direct_to_q_T_29, empty_6, UInt<1>(0h0)) node _direct_to_q_T_38 = mux(_direct_to_q_T_30, empty_7, UInt<1>(0h0)) node _direct_to_q_T_39 = or(_direct_to_q_T_31, _direct_to_q_T_32) node _direct_to_q_T_40 = or(_direct_to_q_T_39, _direct_to_q_T_33) node _direct_to_q_T_41 = or(_direct_to_q_T_40, _direct_to_q_T_34) node _direct_to_q_T_42 = or(_direct_to_q_T_41, _direct_to_q_T_35) node _direct_to_q_T_43 = or(_direct_to_q_T_42, _direct_to_q_T_36) node _direct_to_q_T_44 = or(_direct_to_q_T_43, _direct_to_q_T_37) node _direct_to_q_T_45 = or(_direct_to_q_T_44, _direct_to_q_T_38) wire _direct_to_q_WIRE_1 : UInt<1> connect _direct_to_q_WIRE_1, _direct_to_q_T_45 node _direct_to_q_T_46 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1) node direct_to_q = and(_direct_to_q_T_46, UInt<1>(0h1)) connect flit.head, io.enq[0].bits.head connect flit.tail, io.enq[0].bits.tail connect flit.payload, io.enq[0].bits.payload node _T = eq(direct_to_q, UInt<1>(0h0)) node _T_1 = and(io.enq[0].valid, _T) when _T_1 : write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock connect MPORT, flit node _tails_T = bits(vc_sel, 0, 0) node _tails_T_1 = bits(vc_sel, 1, 1) node _tails_T_2 = bits(vc_sel, 2, 2) node _tails_T_3 = bits(vc_sel, 3, 3) node _tails_T_4 = bits(vc_sel, 4, 4) node _tails_T_5 = bits(vc_sel, 5, 5) node _tails_T_6 = bits(vc_sel, 6, 6) node _tails_T_7 = bits(vc_sel, 7, 7) node _tails_T_8 = mux(_tails_T, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_9 = mux(_tails_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_10 = mux(_tails_T_2, UInt<2>(0h3), UInt<1>(0h0)) node _tails_T_11 = mux(_tails_T_3, UInt<3>(0h7), UInt<1>(0h0)) node _tails_T_12 = mux(_tails_T_4, UInt<4>(0hb), UInt<1>(0h0)) node _tails_T_13 = mux(_tails_T_5, UInt<4>(0hf), UInt<1>(0h0)) node _tails_T_14 = mux(_tails_T_6, UInt<5>(0h13), UInt<1>(0h0)) node _tails_T_15 = mux(_tails_T_7, UInt<5>(0h17), UInt<1>(0h0)) node _tails_T_16 = or(_tails_T_8, _tails_T_9) node _tails_T_17 = or(_tails_T_16, _tails_T_10) node _tails_T_18 = or(_tails_T_17, _tails_T_11) node _tails_T_19 = or(_tails_T_18, _tails_T_12) node _tails_T_20 = or(_tails_T_19, _tails_T_13) node _tails_T_21 = or(_tails_T_20, _tails_T_14) node _tails_T_22 = or(_tails_T_21, _tails_T_15) wire _tails_WIRE_1 : UInt<5> connect _tails_WIRE_1, _tails_T_22 node _tails_T_23 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1) node _tails_T_24 = bits(vc_sel, 0, 0) node _tails_T_25 = bits(vc_sel, 1, 1) node _tails_T_26 = bits(vc_sel, 2, 2) node _tails_T_27 = bits(vc_sel, 3, 3) node _tails_T_28 = bits(vc_sel, 4, 4) node _tails_T_29 = bits(vc_sel, 5, 5) node _tails_T_30 = bits(vc_sel, 6, 6) node _tails_T_31 = bits(vc_sel, 7, 7) node _tails_T_32 = mux(_tails_T_24, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_33 = mux(_tails_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_34 = mux(_tails_T_26, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_35 = mux(_tails_T_27, UInt<3>(0h4), UInt<1>(0h0)) node _tails_T_36 = mux(_tails_T_28, UInt<4>(0h8), UInt<1>(0h0)) node _tails_T_37 = mux(_tails_T_29, UInt<4>(0hc), UInt<1>(0h0)) node _tails_T_38 = mux(_tails_T_30, UInt<5>(0h10), UInt<1>(0h0)) node _tails_T_39 = mux(_tails_T_31, UInt<5>(0h14), UInt<1>(0h0)) node _tails_T_40 = or(_tails_T_32, _tails_T_33) node _tails_T_41 = or(_tails_T_40, _tails_T_34) node _tails_T_42 = or(_tails_T_41, _tails_T_35) node _tails_T_43 = or(_tails_T_42, _tails_T_36) node _tails_T_44 = or(_tails_T_43, _tails_T_37) node _tails_T_45 = or(_tails_T_44, _tails_T_38) node _tails_T_46 = or(_tails_T_45, _tails_T_39) wire _tails_WIRE_2 : UInt<5> connect _tails_WIRE_2, _tails_T_46 node _tails_T_47 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1)) node _tails_T_48 = tail(_tails_T_47, 1) node _tails_T_49 = mux(_tails_T_23, _tails_WIRE_2, _tails_T_48) connect tails[io.enq[0].bits.virt_channel_id], _tails_T_49 else : node _T_2 = and(io.enq[0].valid, direct_to_q) when _T_2 : node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0)) when _T_3 : connect qs_0.io.enq.valid, UInt<1>(0h1) connect qs_0.io.enq.bits.payload, flit.payload connect qs_0.io.enq.bits.tail, flit.tail connect qs_0.io.enq.bits.head, flit.head node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1)) when _T_4 : connect qs_1.io.enq.valid, UInt<1>(0h1) connect qs_1.io.enq.bits.payload, flit.payload connect qs_1.io.enq.bits.tail, flit.tail connect qs_1.io.enq.bits.head, flit.head node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2)) when _T_5 : connect qs_2.io.enq.valid, UInt<1>(0h1) connect qs_2.io.enq.bits.payload, flit.payload connect qs_2.io.enq.bits.tail, flit.tail connect qs_2.io.enq.bits.head, flit.head node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3)) when _T_6 : connect qs_3.io.enq.valid, UInt<1>(0h1) connect qs_3.io.enq.bits.payload, flit.payload connect qs_3.io.enq.bits.tail, flit.tail connect qs_3.io.enq.bits.head, flit.head node _T_7 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h4)) when _T_7 : connect qs_4.io.enq.valid, UInt<1>(0h1) connect qs_4.io.enq.bits.payload, flit.payload connect qs_4.io.enq.bits.tail, flit.tail connect qs_4.io.enq.bits.head, flit.head node _T_8 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h5)) when _T_8 : connect qs_5.io.enq.valid, UInt<1>(0h1) connect qs_5.io.enq.bits.payload, flit.payload connect qs_5.io.enq.bits.tail, flit.tail connect qs_5.io.enq.bits.head, flit.head node _T_9 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h6)) when _T_9 : connect qs_6.io.enq.valid, UInt<1>(0h1) connect qs_6.io.enq.bits.payload, flit.payload connect qs_6.io.enq.bits.tail, flit.tail connect qs_6.io.enq.bits.head, flit.head node _T_10 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h7)) when _T_10 : connect qs_7.io.enq.valid, UInt<1>(0h1) connect qs_7.io.enq.bits.payload, flit.payload connect qs_7.io.enq.bits.tail, flit.tail connect qs_7.io.enq.bits.head, flit.head node _can_to_q_T = eq(empty_0, UInt<1>(0h0)) node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready) node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0)) node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready) node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0)) node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready) node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0)) node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready) node _can_to_q_T_4 = eq(empty_4, UInt<1>(0h0)) node can_to_q_4 = and(_can_to_q_T_4, qs_4.io.enq.ready) node _can_to_q_T_5 = eq(empty_5, UInt<1>(0h0)) node can_to_q_5 = and(_can_to_q_T_5, qs_5.io.enq.ready) node _can_to_q_T_6 = eq(empty_6, UInt<1>(0h0)) node can_to_q_6 = and(_can_to_q_T_6, qs_6.io.enq.ready) node _can_to_q_T_7 = eq(empty_7, UInt<1>(0h0)) node can_to_q_7 = and(_can_to_q_T_7, qs_7.io.enq.ready) node _to_q_oh_enc_T = mux(can_to_q_7, UInt<8>(0h80), UInt<8>(0h0)) node _to_q_oh_enc_T_1 = mux(can_to_q_6, UInt<8>(0h40), _to_q_oh_enc_T) node _to_q_oh_enc_T_2 = mux(can_to_q_5, UInt<8>(0h20), _to_q_oh_enc_T_1) node _to_q_oh_enc_T_3 = mux(can_to_q_4, UInt<8>(0h10), _to_q_oh_enc_T_2) node _to_q_oh_enc_T_4 = mux(can_to_q_3, UInt<8>(0h8), _to_q_oh_enc_T_3) node _to_q_oh_enc_T_5 = mux(can_to_q_2, UInt<8>(0h4), _to_q_oh_enc_T_4) node _to_q_oh_enc_T_6 = mux(can_to_q_1, UInt<8>(0h2), _to_q_oh_enc_T_5) node to_q_oh_enc = mux(can_to_q_0, UInt<8>(0h1), _to_q_oh_enc_T_6) node to_q_oh_0 = bits(to_q_oh_enc, 0, 0) node to_q_oh_1 = bits(to_q_oh_enc, 1, 1) node to_q_oh_2 = bits(to_q_oh_enc, 2, 2) node to_q_oh_3 = bits(to_q_oh_enc, 3, 3) node to_q_oh_4 = bits(to_q_oh_enc, 4, 4) node to_q_oh_5 = bits(to_q_oh_enc, 5, 5) node to_q_oh_6 = bits(to_q_oh_enc, 6, 6) node to_q_oh_7 = bits(to_q_oh_enc, 7, 7) node to_q_lo_lo = cat(to_q_oh_1, to_q_oh_0) node to_q_lo_hi = cat(to_q_oh_3, to_q_oh_2) node to_q_lo = cat(to_q_lo_hi, to_q_lo_lo) node to_q_hi_lo = cat(to_q_oh_5, to_q_oh_4) node to_q_hi_hi = cat(to_q_oh_7, to_q_oh_6) node to_q_hi = cat(to_q_hi_hi, to_q_hi_lo) node _to_q_T = cat(to_q_hi, to_q_lo) node to_q_hi_1 = bits(_to_q_T, 7, 4) node to_q_lo_1 = bits(_to_q_T, 3, 0) node _to_q_T_1 = orr(to_q_hi_1) node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1) node to_q_hi_2 = bits(_to_q_T_2, 3, 2) node to_q_lo_2 = bits(_to_q_T_2, 1, 0) node _to_q_T_3 = orr(to_q_hi_2) node _to_q_T_4 = or(to_q_hi_2, to_q_lo_2) node _to_q_T_5 = bits(_to_q_T_4, 1, 1) node _to_q_T_6 = cat(_to_q_T_3, _to_q_T_5) node to_q = cat(_to_q_T_1, _to_q_T_6) node _T_11 = or(can_to_q_0, can_to_q_1) node _T_12 = or(_T_11, can_to_q_2) node _T_13 = or(_T_12, can_to_q_3) node _T_14 = or(_T_13, can_to_q_4) node _T_15 = or(_T_14, can_to_q_5) node _T_16 = or(_T_15, can_to_q_6) node _T_17 = or(_T_16, can_to_q_7) when _T_17 : node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0)) node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0)) node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0)) node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0)) node _head_T_4 = mux(to_q_oh_4, heads[4], UInt<1>(0h0)) node _head_T_5 = mux(to_q_oh_5, heads[5], UInt<1>(0h0)) node _head_T_6 = mux(to_q_oh_6, heads[6], UInt<1>(0h0)) node _head_T_7 = mux(to_q_oh_7, heads[7], UInt<1>(0h0)) node _head_T_8 = or(_head_T, _head_T_1) node _head_T_9 = or(_head_T_8, _head_T_2) node _head_T_10 = or(_head_T_9, _head_T_3) node _head_T_11 = or(_head_T_10, _head_T_4) node _head_T_12 = or(_head_T_11, _head_T_5) node _head_T_13 = or(_head_T_12, _head_T_6) node _head_T_14 = or(_head_T_13, _head_T_7) wire head : UInt<5> connect head, _head_T_14 node _heads_T = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_1 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_2 = mux(to_q_oh_2, UInt<2>(0h3), UInt<1>(0h0)) node _heads_T_3 = mux(to_q_oh_3, UInt<3>(0h7), UInt<1>(0h0)) node _heads_T_4 = mux(to_q_oh_4, UInt<4>(0hb), UInt<1>(0h0)) node _heads_T_5 = mux(to_q_oh_5, UInt<4>(0hf), UInt<1>(0h0)) node _heads_T_6 = mux(to_q_oh_6, UInt<5>(0h13), UInt<1>(0h0)) node _heads_T_7 = mux(to_q_oh_7, UInt<5>(0h17), UInt<1>(0h0)) node _heads_T_8 = or(_heads_T, _heads_T_1) node _heads_T_9 = or(_heads_T_8, _heads_T_2) node _heads_T_10 = or(_heads_T_9, _heads_T_3) node _heads_T_11 = or(_heads_T_10, _heads_T_4) node _heads_T_12 = or(_heads_T_11, _heads_T_5) node _heads_T_13 = or(_heads_T_12, _heads_T_6) node _heads_T_14 = or(_heads_T_13, _heads_T_7) wire _heads_WIRE_1 : UInt<5> connect _heads_WIRE_1, _heads_T_14 node _heads_T_15 = eq(head, _heads_WIRE_1) node _heads_T_16 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_17 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_18 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_19 = mux(to_q_oh_3, UInt<3>(0h4), UInt<1>(0h0)) node _heads_T_20 = mux(to_q_oh_4, UInt<4>(0h8), UInt<1>(0h0)) node _heads_T_21 = mux(to_q_oh_5, UInt<4>(0hc), UInt<1>(0h0)) node _heads_T_22 = mux(to_q_oh_6, UInt<5>(0h10), UInt<1>(0h0)) node _heads_T_23 = mux(to_q_oh_7, UInt<5>(0h14), UInt<1>(0h0)) node _heads_T_24 = or(_heads_T_16, _heads_T_17) node _heads_T_25 = or(_heads_T_24, _heads_T_18) node _heads_T_26 = or(_heads_T_25, _heads_T_19) node _heads_T_27 = or(_heads_T_26, _heads_T_20) node _heads_T_28 = or(_heads_T_27, _heads_T_21) node _heads_T_29 = or(_heads_T_28, _heads_T_22) node _heads_T_30 = or(_heads_T_29, _heads_T_23) wire _heads_WIRE_2 : UInt<5> connect _heads_WIRE_2, _heads_T_30 node _heads_T_31 = add(head, UInt<1>(0h1)) node _heads_T_32 = tail(_heads_T_31, 1) node _heads_T_33 = mux(_heads_T_15, _heads_WIRE_2, _heads_T_32) connect heads[to_q], _heads_T_33 when to_q_oh_0 : connect qs_0.io.enq.valid, UInt<1>(0h1) read mport qs_0_io_enq_bits_MPORT = mem[head], clock connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head when to_q_oh_1 : connect qs_1.io.enq.valid, UInt<1>(0h1) read mport qs_1_io_enq_bits_MPORT = mem[head], clock connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head when to_q_oh_2 : connect qs_2.io.enq.valid, UInt<1>(0h1) read mport qs_2_io_enq_bits_MPORT = mem[head], clock connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head when to_q_oh_3 : connect qs_3.io.enq.valid, UInt<1>(0h1) read mport qs_3_io_enq_bits_MPORT = mem[head], clock connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head when to_q_oh_4 : connect qs_4.io.enq.valid, UInt<1>(0h1) read mport qs_4_io_enq_bits_MPORT = mem[head], clock connect qs_4.io.enq.bits.payload, qs_4_io_enq_bits_MPORT.payload connect qs_4.io.enq.bits.tail, qs_4_io_enq_bits_MPORT.tail connect qs_4.io.enq.bits.head, qs_4_io_enq_bits_MPORT.head when to_q_oh_5 : connect qs_5.io.enq.valid, UInt<1>(0h1) read mport qs_5_io_enq_bits_MPORT = mem[head], clock connect qs_5.io.enq.bits.payload, qs_5_io_enq_bits_MPORT.payload connect qs_5.io.enq.bits.tail, qs_5_io_enq_bits_MPORT.tail connect qs_5.io.enq.bits.head, qs_5_io_enq_bits_MPORT.head when to_q_oh_6 : connect qs_6.io.enq.valid, UInt<1>(0h1) read mport qs_6_io_enq_bits_MPORT = mem[head], clock connect qs_6.io.enq.bits.payload, qs_6_io_enq_bits_MPORT.payload connect qs_6.io.enq.bits.tail, qs_6_io_enq_bits_MPORT.tail connect qs_6.io.enq.bits.head, qs_6_io_enq_bits_MPORT.head when to_q_oh_7 : connect qs_7.io.enq.valid, UInt<1>(0h1) read mport qs_7_io_enq_bits_MPORT = mem[head], clock connect qs_7.io.enq.bits.payload, qs_7_io_enq_bits_MPORT.payload connect qs_7.io.enq.bits.tail, qs_7_io_enq_bits_MPORT.tail connect qs_7.io.enq.bits.head, qs_7_io_enq_bits_MPORT.head connect io.deq[0].bits, qs_0.io.deq.bits connect io.deq[0].valid, qs_0.io.deq.valid connect qs_0.io.deq.ready, io.deq[0].ready connect io.deq[1].bits, qs_1.io.deq.bits connect io.deq[1].valid, qs_1.io.deq.valid connect qs_1.io.deq.ready, io.deq[1].ready connect io.deq[2].bits, qs_2.io.deq.bits connect io.deq[2].valid, qs_2.io.deq.valid connect qs_2.io.deq.ready, io.deq[2].ready connect io.deq[3].bits, qs_3.io.deq.bits connect io.deq[3].valid, qs_3.io.deq.valid connect qs_3.io.deq.ready, io.deq[3].ready connect io.deq[4].bits, qs_4.io.deq.bits connect io.deq[4].valid, qs_4.io.deq.valid connect qs_4.io.deq.ready, io.deq[4].ready connect io.deq[5].bits, qs_5.io.deq.bits connect io.deq[5].valid, qs_5.io.deq.valid connect qs_5.io.deq.ready, io.deq[5].ready connect io.deq[6].bits, qs_6.io.deq.bits connect io.deq[6].valid, qs_6.io.deq.valid connect qs_6.io.deq.ready, io.deq[6].ready connect io.deq[7].bits, qs_7.io.deq.bits connect io.deq[7].valid, qs_7.io.deq.valid connect qs_7.io.deq.ready, io.deq[7].ready
module InputBuffer_70( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [2:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] input io_deq_2_ready, // @[InputUnit.scala:51:14] output io_deq_2_valid, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] input io_deq_4_ready, // @[InputUnit.scala:51:14] output io_deq_4_valid, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] input io_deq_5_ready, // @[InputUnit.scala:51:14] output io_deq_5_valid, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] input io_deq_6_ready, // @[InputUnit.scala:51:14] output io_deq_6_valid, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] input io_deq_7_ready, // @[InputUnit.scala:51:14] output io_deq_7_valid, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] reg [4:0] heads_0; // @[InputUnit.scala:86:24] reg [4:0] heads_1; // @[InputUnit.scala:86:24] reg [4:0] heads_2; // @[InputUnit.scala:86:24] reg [4:0] heads_3; // @[InputUnit.scala:86:24] reg [4:0] heads_4; // @[InputUnit.scala:86:24] reg [4:0] heads_5; // @[InputUnit.scala:86:24] reg [4:0] heads_6; // @[InputUnit.scala:86:24] reg [4:0] heads_7; // @[InputUnit.scala:86:24] reg [4:0] tails_0; // @[InputUnit.scala:87:24] reg [4:0] tails_1; // @[InputUnit.scala:87:24] reg [4:0] tails_2; // @[InputUnit.scala:87:24] reg [4:0] tails_3; // @[InputUnit.scala:87:24] reg [4:0] tails_4; // @[InputUnit.scala:87:24] reg [4:0] tails_5; // @[InputUnit.scala:87:24] reg [4:0] tails_6; // @[InputUnit.scala:87:24] reg [4:0] tails_7; // @[InputUnit.scala:87:24] wire _tails_T_24 = io_enq_0_bits_virt_channel_id == 3'h0; // @[Mux.scala:32:36] wire _tails_T_25 = io_enq_0_bits_virt_channel_id == 3'h1; // @[Mux.scala:32:36] wire _tails_T_26 = io_enq_0_bits_virt_channel_id == 3'h2; // @[Mux.scala:32:36] wire _tails_T_27 = io_enq_0_bits_virt_channel_id == 3'h3; // @[Mux.scala:32:36] wire _tails_T_28 = io_enq_0_bits_virt_channel_id == 3'h4; // @[Mux.scala:32:36] wire _tails_T_29 = io_enq_0_bits_virt_channel_id == 3'h5; // @[Mux.scala:32:36] wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 3'h6; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_24 & _qs_0_io_enq_ready | _tails_T_25 & _qs_1_io_enq_ready | _tails_T_26 & _qs_2_io_enq_ready | _tails_T_27 & _qs_3_io_enq_ready | _tails_T_28 & _qs_4_io_enq_ready | _tails_T_29 & _qs_5_io_enq_ready | _tails_T_30 & _qs_6_io_enq_ready | (&io_enq_0_bits_virt_channel_id) & _qs_7_io_enq_ready) & (_tails_T_24 & heads_0 == tails_0 | _tails_T_25 & heads_1 == tails_1 | _tails_T_26 & heads_2 == tails_2 | _tails_T_27 & heads_3 == tails_3 | _tails_T_28 & heads_4 == tails_4 | _tails_T_29 & heads_5 == tails_5 | _tails_T_30 & heads_6 == tails_6 | (&io_enq_0_bits_virt_channel_id) & heads_7 == tails_7); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [7:0][4:0] _GEN = {{tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 3'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 3'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 3'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 3'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 3'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 3'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 3'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [7:0] to_q_oh_enc = can_to_q_0 ? 8'h1 : can_to_q_1 ? 8'h2 : can_to_q_2 ? 8'h4 : can_to_q_3 ? 8'h8 : can_to_q_4 ? 8'h10 : can_to_q_5 ? 8'h20 : can_to_q_6 ? 8'h40 : {can_to_q_7, 7'h0}; // @[OneHot.scala:58:35] wire _GEN_8 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5 | can_to_q_6 | can_to_q_7; // @[package.scala:81:59] wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) | (to_q_oh_enc[1] ? heads_1 : 5'h0) | (to_q_oh_enc[2] ? heads_2 : 5'h0) | (to_q_oh_enc[3] ? heads_3 : 5'h0) | (to_q_oh_enc[4] ? heads_4 : 5'h0) | (to_q_oh_enc[5] ? heads_5 : 5'h0) | (to_q_oh_enc[6] ? heads_6 : 5'h0) | (to_q_oh_enc[7] ? heads_7 : 5'h0); // @[OneHot.scala:83:30] wire _GEN_9 = _GEN_8 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_10 = _GEN_8 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_11 = _GEN_8 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_12 = _GEN_8 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_13 = _GEN_8 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_14 = _GEN_8 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_15 = _GEN_8 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_16 = _GEN_8 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire [4:0] _tails_T_49 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_26}}} | {3{_tails_T_27}}} | (_tails_T_28 ? 4'hB : 4'h0) | {4{_tails_T_29}}} | (_tails_T_30 ? 5'h13 : 5'h0) | ((&io_enq_0_bits_virt_channel_id) ? 5'h17 : 5'h0)) ? {_tails_T_30, {_tails_T_28, _tails_T_27, 2'h0} | (_tails_T_29 ? 4'hC : 4'h0)} | ((&io_enq_0_bits_virt_channel_id) ? 5'h14 : 5'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36] wire [2:0] _to_q_T_2 = to_q_oh_enc[7:5] | to_q_oh_enc[3:1]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_4 = _to_q_T_2[2] | _to_q_T_2[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] to_q = {|(to_q_oh_enc[7:4]), |(_to_q_T_2[2:1]), _to_q_T_4}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [4:0] _heads_T_33 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[2]}}} | {3{to_q_oh_enc[3]}}} | (to_q_oh_enc[4] ? 4'hB : 4'h0) | {4{to_q_oh_enc[5]}}} | (to_q_oh_enc[6] ? 5'h13 : 5'h0) | (to_q_oh_enc[7] ? 5'h17 : 5'h0)) ? {to_q_oh_enc[6], {to_q_oh_enc[4:3], 2'h0} | (to_q_oh_enc[5] ? 4'hC : 4'h0)} | (to_q_oh_enc[7] ? 5'h14 : 5'h0) : head + 5'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 5'h0; // @[InputUnit.scala:86:24] heads_1 <= 5'h0; // @[InputUnit.scala:86:24] heads_2 <= 5'h0; // @[InputUnit.scala:86:24] heads_3 <= 5'h4; // @[InputUnit.scala:86:24] heads_4 <= 5'h8; // @[InputUnit.scala:86:24] heads_5 <= 5'hC; // @[InputUnit.scala:86:24] heads_6 <= 5'h10; // @[InputUnit.scala:86:24] heads_7 <= 5'h14; // @[InputUnit.scala:86:24] tails_0 <= 5'h0; // @[InputUnit.scala:87:24] tails_1 <= 5'h0; // @[InputUnit.scala:87:24] tails_2 <= 5'h0; // @[InputUnit.scala:87:24] tails_3 <= 5'h4; // @[InputUnit.scala:87:24] tails_4 <= 5'h8; // @[InputUnit.scala:87:24] tails_5 <= 5'hC; // @[InputUnit.scala:87:24] tails_6 <= 5'h10; // @[InputUnit.scala:87:24] tails_7 <= 5'h14; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_8 & {to_q_oh_enc[7:4], |(_to_q_T_2[2:1]), _to_q_T_4} == 6'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & (&to_q)) // @[OneHot.scala:32:10] heads_7 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & (&io_enq_0_bits_virt_channel_id)) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MSHR_17 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_17( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_136 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_136 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RoundRawFNToRecFN_e8_s24_136( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_136 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_41 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_51 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_41( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_51 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_50 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_50( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_82 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_83 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_17 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_37 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_17( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_37 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_cbus_out_i1_o8_a32d64s7k1z4u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_16 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready wire x1_anonOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut_1.d.bits.corrupt invalidate x1_anonOut_1.d.bits.data invalidate x1_anonOut_1.d.bits.denied invalidate x1_anonOut_1.d.bits.sink invalidate x1_anonOut_1.d.bits.source invalidate x1_anonOut_1.d.bits.size invalidate x1_anonOut_1.d.bits.param invalidate x1_anonOut_1.d.bits.opcode invalidate x1_anonOut_1.d.valid invalidate x1_anonOut_1.d.ready invalidate x1_anonOut_1.a.bits.corrupt invalidate x1_anonOut_1.a.bits.data invalidate x1_anonOut_1.a.bits.mask invalidate x1_anonOut_1.a.bits.address invalidate x1_anonOut_1.a.bits.source invalidate x1_anonOut_1.a.bits.size invalidate x1_anonOut_1.a.bits.param invalidate x1_anonOut_1.a.bits.opcode invalidate x1_anonOut_1.a.valid invalidate x1_anonOut_1.a.ready wire x1_anonOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut_2.d.bits.corrupt invalidate x1_anonOut_2.d.bits.data invalidate x1_anonOut_2.d.bits.denied invalidate x1_anonOut_2.d.bits.sink invalidate x1_anonOut_2.d.bits.source invalidate x1_anonOut_2.d.bits.size invalidate x1_anonOut_2.d.bits.param invalidate x1_anonOut_2.d.bits.opcode invalidate x1_anonOut_2.d.valid invalidate x1_anonOut_2.d.ready invalidate x1_anonOut_2.a.bits.corrupt invalidate x1_anonOut_2.a.bits.data invalidate x1_anonOut_2.a.bits.mask invalidate x1_anonOut_2.a.bits.address invalidate x1_anonOut_2.a.bits.source invalidate x1_anonOut_2.a.bits.size invalidate x1_anonOut_2.a.bits.param invalidate x1_anonOut_2.a.bits.opcode invalidate x1_anonOut_2.a.valid invalidate x1_anonOut_2.a.ready wire x1_anonOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut_3.d.bits.corrupt invalidate x1_anonOut_3.d.bits.data invalidate x1_anonOut_3.d.bits.denied invalidate x1_anonOut_3.d.bits.sink invalidate x1_anonOut_3.d.bits.source invalidate x1_anonOut_3.d.bits.size invalidate x1_anonOut_3.d.bits.param invalidate x1_anonOut_3.d.bits.opcode invalidate x1_anonOut_3.d.valid invalidate x1_anonOut_3.d.ready invalidate x1_anonOut_3.a.bits.corrupt invalidate x1_anonOut_3.a.bits.data invalidate x1_anonOut_3.a.bits.mask invalidate x1_anonOut_3.a.bits.address invalidate x1_anonOut_3.a.bits.source invalidate x1_anonOut_3.a.bits.size invalidate x1_anonOut_3.a.bits.param invalidate x1_anonOut_3.a.bits.opcode invalidate x1_anonOut_3.a.valid invalidate x1_anonOut_3.a.ready wire x1_anonOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut_4.d.bits.corrupt invalidate x1_anonOut_4.d.bits.data invalidate x1_anonOut_4.d.bits.denied invalidate x1_anonOut_4.d.bits.sink invalidate x1_anonOut_4.d.bits.source invalidate x1_anonOut_4.d.bits.size invalidate x1_anonOut_4.d.bits.param invalidate x1_anonOut_4.d.bits.opcode invalidate x1_anonOut_4.d.valid invalidate x1_anonOut_4.d.ready invalidate x1_anonOut_4.a.bits.corrupt invalidate x1_anonOut_4.a.bits.data invalidate x1_anonOut_4.a.bits.mask invalidate x1_anonOut_4.a.bits.address invalidate x1_anonOut_4.a.bits.source invalidate x1_anonOut_4.a.bits.size invalidate x1_anonOut_4.a.bits.param invalidate x1_anonOut_4.a.bits.opcode invalidate x1_anonOut_4.a.valid invalidate x1_anonOut_4.a.ready wire x1_anonOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut_5.d.bits.corrupt invalidate x1_anonOut_5.d.bits.data invalidate x1_anonOut_5.d.bits.denied invalidate x1_anonOut_5.d.bits.sink invalidate x1_anonOut_5.d.bits.source invalidate x1_anonOut_5.d.bits.size invalidate x1_anonOut_5.d.bits.param invalidate x1_anonOut_5.d.bits.opcode invalidate x1_anonOut_5.d.valid invalidate x1_anonOut_5.d.ready invalidate x1_anonOut_5.a.bits.corrupt invalidate x1_anonOut_5.a.bits.data invalidate x1_anonOut_5.a.bits.mask invalidate x1_anonOut_5.a.bits.address invalidate x1_anonOut_5.a.bits.source invalidate x1_anonOut_5.a.bits.size invalidate x1_anonOut_5.a.bits.param invalidate x1_anonOut_5.a.bits.opcode invalidate x1_anonOut_5.a.valid invalidate x1_anonOut_5.a.ready wire x1_anonOut_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut_6.d.bits.corrupt invalidate x1_anonOut_6.d.bits.data invalidate x1_anonOut_6.d.bits.denied invalidate x1_anonOut_6.d.bits.sink invalidate x1_anonOut_6.d.bits.source invalidate x1_anonOut_6.d.bits.size invalidate x1_anonOut_6.d.bits.param invalidate x1_anonOut_6.d.bits.opcode invalidate x1_anonOut_6.d.valid invalidate x1_anonOut_6.d.ready invalidate x1_anonOut_6.a.bits.corrupt invalidate x1_anonOut_6.a.bits.data invalidate x1_anonOut_6.a.bits.mask invalidate x1_anonOut_6.a.bits.address invalidate x1_anonOut_6.a.bits.source invalidate x1_anonOut_6.a.bits.size invalidate x1_anonOut_6.a.bits.param invalidate x1_anonOut_6.a.bits.opcode invalidate x1_anonOut_6.a.valid invalidate x1_anonOut_6.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect auto.anon_out_2, x1_anonOut_1 connect auto.anon_out_3, x1_anonOut_2 connect auto.anon_out_4, x1_anonOut_3 connect auto.anon_out_5, x1_anonOut_4 connect auto.anon_out_6, x1_anonOut_5 connect auto.anon_out_7, x1_anonOut_6 connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 6, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[8] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<14>(0h0) connect _WIRE_30.bits.source, UInt<7>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<7>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<14>(0h0) connect _WIRE_34.bits.source, UInt<7>(0h0) connect _WIRE_34.bits.size, UInt<4>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<7>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<14>(0h0) connect _WIRE_38.bits.source, UInt<7>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<7>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<29>(0h0) connect _WIRE_50.bits.source, UInt<7>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<7>(0h0) connect _WIRE_52.bits.size, UInt<4>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<29>(0h0) connect _WIRE_54.bits.source, UInt<7>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<7>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<29>(0h0) connect _WIRE_58.bits.source, UInt<7>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<7>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<29>(0h0) connect _WIRE_62.bits.source, UInt<7>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) connect x1_anonOut_1.a.bits.corrupt, out[2].a.bits.corrupt connect x1_anonOut_1.a.bits.data, out[2].a.bits.data connect x1_anonOut_1.a.bits.mask, out[2].a.bits.mask connect x1_anonOut_1.a.bits.address, out[2].a.bits.address connect x1_anonOut_1.a.bits.source, out[2].a.bits.source connect x1_anonOut_1.a.bits.size, out[2].a.bits.size connect x1_anonOut_1.a.bits.param, out[2].a.bits.param connect x1_anonOut_1.a.bits.opcode, out[2].a.bits.opcode connect x1_anonOut_1.a.valid, out[2].a.valid connect out[2].a.ready, x1_anonOut_1.a.ready wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.mask, UInt<8>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<7>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<2>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.mask invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode invalidate _WIRE_73.valid invalidate _WIRE_73.ready wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_74.bits.corrupt, UInt<1>(0h0) connect _WIRE_74.bits.data, UInt<64>(0h0) connect _WIRE_74.bits.mask, UInt<8>(0h0) connect _WIRE_74.bits.address, UInt<26>(0h0) connect _WIRE_74.bits.source, UInt<7>(0h0) connect _WIRE_74.bits.size, UInt<3>(0h0) connect _WIRE_74.bits.param, UInt<2>(0h0) connect _WIRE_74.bits.opcode, UInt<3>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.corrupt invalidate _WIRE_75.bits.data invalidate _WIRE_75.bits.mask invalidate _WIRE_75.bits.address invalidate _WIRE_75.bits.source invalidate _WIRE_75.bits.size invalidate _WIRE_75.bits.param invalidate _WIRE_75.bits.opcode invalidate _WIRE_75.valid invalidate _WIRE_75.ready wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.mask, UInt<8>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<7>(0h0) connect _WIRE_76.bits.size, UInt<4>(0h0) connect _WIRE_76.bits.param, UInt<2>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready connect _WIRE_77.valid, UInt<1>(0h0) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<64>(0h0) connect _WIRE_78.bits.mask, UInt<8>(0h0) connect _WIRE_78.bits.address, UInt<26>(0h0) connect _WIRE_78.bits.source, UInt<7>(0h0) connect _WIRE_78.bits.size, UInt<3>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready connect _WIRE_79.ready, UInt<1>(0h1) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.address, UInt<32>(0h0) connect _WIRE_80.bits.source, UInt<7>(0h0) connect _WIRE_80.bits.size, UInt<4>(0h0) connect _WIRE_80.bits.param, UInt<3>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode invalidate _WIRE_81.valid invalidate _WIRE_81.ready wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_82.bits.corrupt, UInt<1>(0h0) connect _WIRE_82.bits.data, UInt<64>(0h0) connect _WIRE_82.bits.address, UInt<26>(0h0) connect _WIRE_82.bits.source, UInt<7>(0h0) connect _WIRE_82.bits.size, UInt<3>(0h0) connect _WIRE_82.bits.param, UInt<3>(0h0) connect _WIRE_82.bits.opcode, UInt<3>(0h0) connect _WIRE_82.valid, UInt<1>(0h0) connect _WIRE_82.ready, UInt<1>(0h0) wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_83.bits, _WIRE_82.bits connect _WIRE_83.valid, _WIRE_82.valid connect _WIRE_83.ready, _WIRE_82.ready invalidate _WIRE_83.bits.corrupt invalidate _WIRE_83.bits.data invalidate _WIRE_83.bits.address invalidate _WIRE_83.bits.source invalidate _WIRE_83.bits.size invalidate _WIRE_83.bits.param invalidate _WIRE_83.bits.opcode invalidate _WIRE_83.valid invalidate _WIRE_83.ready wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_84.bits.corrupt, UInt<1>(0h0) connect _WIRE_84.bits.data, UInt<64>(0h0) connect _WIRE_84.bits.address, UInt<32>(0h0) connect _WIRE_84.bits.source, UInt<7>(0h0) connect _WIRE_84.bits.size, UInt<4>(0h0) connect _WIRE_84.bits.param, UInt<3>(0h0) connect _WIRE_84.bits.opcode, UInt<3>(0h0) connect _WIRE_84.valid, UInt<1>(0h0) connect _WIRE_84.ready, UInt<1>(0h0) wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_85.bits, _WIRE_84.bits connect _WIRE_85.valid, _WIRE_84.valid connect _WIRE_85.ready, _WIRE_84.ready connect _WIRE_85.ready, UInt<1>(0h1) wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_86.bits.corrupt, UInt<1>(0h0) connect _WIRE_86.bits.data, UInt<64>(0h0) connect _WIRE_86.bits.address, UInt<26>(0h0) connect _WIRE_86.bits.source, UInt<7>(0h0) connect _WIRE_86.bits.size, UInt<3>(0h0) connect _WIRE_86.bits.param, UInt<3>(0h0) connect _WIRE_86.bits.opcode, UInt<3>(0h0) connect _WIRE_86.valid, UInt<1>(0h0) connect _WIRE_86.ready, UInt<1>(0h0) wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_87.bits, _WIRE_86.bits connect _WIRE_87.valid, _WIRE_86.valid connect _WIRE_87.ready, _WIRE_86.ready connect _WIRE_87.valid, UInt<1>(0h0) connect out[2].d.bits.corrupt, x1_anonOut_1.d.bits.corrupt connect out[2].d.bits.data, x1_anonOut_1.d.bits.data connect out[2].d.bits.denied, x1_anonOut_1.d.bits.denied connect out[2].d.bits.sink, x1_anonOut_1.d.bits.sink connect out[2].d.bits.source, x1_anonOut_1.d.bits.source connect out[2].d.bits.size, x1_anonOut_1.d.bits.size connect out[2].d.bits.param, x1_anonOut_1.d.bits.param connect out[2].d.bits.opcode, x1_anonOut_1.d.bits.opcode connect out[2].d.valid, x1_anonOut_1.d.valid connect x1_anonOut_1.d.ready, out[2].d.ready node _out_2_d_bits_sink_T = or(x1_anonOut_1.d.bits.sink, UInt<1>(0h0)) connect out[2].d.bits.sink, _out_2_d_bits_sink_T wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_88.bits.sink, UInt<1>(0h0) connect _WIRE_88.valid, UInt<1>(0h0) connect _WIRE_88.ready, UInt<1>(0h0) wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_89.bits, _WIRE_88.bits connect _WIRE_89.valid, _WIRE_88.valid connect _WIRE_89.ready, _WIRE_88.ready invalidate _WIRE_89.bits.sink invalidate _WIRE_89.valid invalidate _WIRE_89.ready wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_90.bits.sink, UInt<1>(0h0) connect _WIRE_90.valid, UInt<1>(0h0) connect _WIRE_90.ready, UInt<1>(0h0) wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_91.bits, _WIRE_90.bits connect _WIRE_91.valid, _WIRE_90.valid connect _WIRE_91.ready, _WIRE_90.ready invalidate _WIRE_91.bits.sink invalidate _WIRE_91.valid invalidate _WIRE_91.ready wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_92.bits.sink, UInt<1>(0h0) connect _WIRE_92.valid, UInt<1>(0h0) connect _WIRE_92.ready, UInt<1>(0h0) wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_93.bits, _WIRE_92.bits connect _WIRE_93.valid, _WIRE_92.valid connect _WIRE_93.ready, _WIRE_92.ready connect _WIRE_93.ready, UInt<1>(0h1) wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_94.bits.sink, UInt<1>(0h0) connect _WIRE_94.valid, UInt<1>(0h0) connect _WIRE_94.ready, UInt<1>(0h0) wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_95.bits, _WIRE_94.bits connect _WIRE_95.valid, _WIRE_94.valid connect _WIRE_95.ready, _WIRE_94.ready connect _WIRE_95.valid, UInt<1>(0h0) connect x1_anonOut_2.a.bits.corrupt, out[3].a.bits.corrupt connect x1_anonOut_2.a.bits.data, out[3].a.bits.data connect x1_anonOut_2.a.bits.mask, out[3].a.bits.mask connect x1_anonOut_2.a.bits.address, out[3].a.bits.address connect x1_anonOut_2.a.bits.source, out[3].a.bits.source connect x1_anonOut_2.a.bits.size, out[3].a.bits.size connect x1_anonOut_2.a.bits.param, out[3].a.bits.param connect x1_anonOut_2.a.bits.opcode, out[3].a.bits.opcode connect x1_anonOut_2.a.valid, out[3].a.valid connect out[3].a.ready, x1_anonOut_2.a.ready wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_96.bits.corrupt, UInt<1>(0h0) connect _WIRE_96.bits.data, UInt<64>(0h0) connect _WIRE_96.bits.mask, UInt<8>(0h0) connect _WIRE_96.bits.address, UInt<32>(0h0) connect _WIRE_96.bits.source, UInt<7>(0h0) connect _WIRE_96.bits.size, UInt<4>(0h0) connect _WIRE_96.bits.param, UInt<2>(0h0) connect _WIRE_96.bits.opcode, UInt<3>(0h0) connect _WIRE_96.valid, UInt<1>(0h0) connect _WIRE_96.ready, UInt<1>(0h0) wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_97.bits, _WIRE_96.bits connect _WIRE_97.valid, _WIRE_96.valid connect _WIRE_97.ready, _WIRE_96.ready invalidate _WIRE_97.bits.corrupt invalidate _WIRE_97.bits.data invalidate _WIRE_97.bits.mask invalidate _WIRE_97.bits.address invalidate _WIRE_97.bits.source invalidate _WIRE_97.bits.size invalidate _WIRE_97.bits.param invalidate _WIRE_97.bits.opcode invalidate _WIRE_97.valid invalidate _WIRE_97.ready wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_98.bits.corrupt, UInt<1>(0h0) connect _WIRE_98.bits.data, UInt<64>(0h0) connect _WIRE_98.bits.mask, UInt<8>(0h0) connect _WIRE_98.bits.address, UInt<28>(0h0) connect _WIRE_98.bits.source, UInt<7>(0h0) connect _WIRE_98.bits.size, UInt<3>(0h0) connect _WIRE_98.bits.param, UInt<2>(0h0) connect _WIRE_98.bits.opcode, UInt<3>(0h0) connect _WIRE_98.valid, UInt<1>(0h0) connect _WIRE_98.ready, UInt<1>(0h0) wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_99.bits, _WIRE_98.bits connect _WIRE_99.valid, _WIRE_98.valid connect _WIRE_99.ready, _WIRE_98.ready invalidate _WIRE_99.bits.corrupt invalidate _WIRE_99.bits.data invalidate _WIRE_99.bits.mask invalidate _WIRE_99.bits.address invalidate _WIRE_99.bits.source invalidate _WIRE_99.bits.size invalidate _WIRE_99.bits.param invalidate _WIRE_99.bits.opcode invalidate _WIRE_99.valid invalidate _WIRE_99.ready wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_100.bits.corrupt, UInt<1>(0h0) connect _WIRE_100.bits.data, UInt<64>(0h0) connect _WIRE_100.bits.mask, UInt<8>(0h0) connect _WIRE_100.bits.address, UInt<32>(0h0) connect _WIRE_100.bits.source, UInt<7>(0h0) connect _WIRE_100.bits.size, UInt<4>(0h0) connect _WIRE_100.bits.param, UInt<2>(0h0) connect _WIRE_100.bits.opcode, UInt<3>(0h0) connect _WIRE_100.valid, UInt<1>(0h0) connect _WIRE_100.ready, UInt<1>(0h0) wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_101.bits, _WIRE_100.bits connect _WIRE_101.valid, _WIRE_100.valid connect _WIRE_101.ready, _WIRE_100.ready connect _WIRE_101.valid, UInt<1>(0h0) wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_102.bits.corrupt, UInt<1>(0h0) connect _WIRE_102.bits.data, UInt<64>(0h0) connect _WIRE_102.bits.mask, UInt<8>(0h0) connect _WIRE_102.bits.address, UInt<28>(0h0) connect _WIRE_102.bits.source, UInt<7>(0h0) connect _WIRE_102.bits.size, UInt<3>(0h0) connect _WIRE_102.bits.param, UInt<2>(0h0) connect _WIRE_102.bits.opcode, UInt<3>(0h0) connect _WIRE_102.valid, UInt<1>(0h0) connect _WIRE_102.ready, UInt<1>(0h0) wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_103.bits, _WIRE_102.bits connect _WIRE_103.valid, _WIRE_102.valid connect _WIRE_103.ready, _WIRE_102.ready connect _WIRE_103.ready, UInt<1>(0h1) wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_104.bits.corrupt, UInt<1>(0h0) connect _WIRE_104.bits.data, UInt<64>(0h0) connect _WIRE_104.bits.address, UInt<32>(0h0) connect _WIRE_104.bits.source, UInt<7>(0h0) connect _WIRE_104.bits.size, UInt<4>(0h0) connect _WIRE_104.bits.param, UInt<3>(0h0) connect _WIRE_104.bits.opcode, UInt<3>(0h0) connect _WIRE_104.valid, UInt<1>(0h0) connect _WIRE_104.ready, UInt<1>(0h0) wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_105.bits, _WIRE_104.bits connect _WIRE_105.valid, _WIRE_104.valid connect _WIRE_105.ready, _WIRE_104.ready invalidate _WIRE_105.bits.corrupt invalidate _WIRE_105.bits.data invalidate _WIRE_105.bits.address invalidate _WIRE_105.bits.source invalidate _WIRE_105.bits.size invalidate _WIRE_105.bits.param invalidate _WIRE_105.bits.opcode invalidate _WIRE_105.valid invalidate _WIRE_105.ready wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_106.bits.corrupt, UInt<1>(0h0) connect _WIRE_106.bits.data, UInt<64>(0h0) connect _WIRE_106.bits.address, UInt<28>(0h0) connect _WIRE_106.bits.source, UInt<7>(0h0) connect _WIRE_106.bits.size, UInt<3>(0h0) connect _WIRE_106.bits.param, UInt<3>(0h0) connect _WIRE_106.bits.opcode, UInt<3>(0h0) connect _WIRE_106.valid, UInt<1>(0h0) connect _WIRE_106.ready, UInt<1>(0h0) wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_107.bits, _WIRE_106.bits connect _WIRE_107.valid, _WIRE_106.valid connect _WIRE_107.ready, _WIRE_106.ready invalidate _WIRE_107.bits.corrupt invalidate _WIRE_107.bits.data invalidate _WIRE_107.bits.address invalidate _WIRE_107.bits.source invalidate _WIRE_107.bits.size invalidate _WIRE_107.bits.param invalidate _WIRE_107.bits.opcode invalidate _WIRE_107.valid invalidate _WIRE_107.ready wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_108.bits.corrupt, UInt<1>(0h0) connect _WIRE_108.bits.data, UInt<64>(0h0) connect _WIRE_108.bits.address, UInt<32>(0h0) connect _WIRE_108.bits.source, UInt<7>(0h0) connect _WIRE_108.bits.size, UInt<4>(0h0) connect _WIRE_108.bits.param, UInt<3>(0h0) connect _WIRE_108.bits.opcode, UInt<3>(0h0) connect _WIRE_108.valid, UInt<1>(0h0) connect _WIRE_108.ready, UInt<1>(0h0) wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_109.bits, _WIRE_108.bits connect _WIRE_109.valid, _WIRE_108.valid connect _WIRE_109.ready, _WIRE_108.ready connect _WIRE_109.ready, UInt<1>(0h1) wire _WIRE_110 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_110.bits.corrupt, UInt<1>(0h0) connect _WIRE_110.bits.data, UInt<64>(0h0) connect _WIRE_110.bits.address, UInt<28>(0h0) connect _WIRE_110.bits.source, UInt<7>(0h0) connect _WIRE_110.bits.size, UInt<3>(0h0) connect _WIRE_110.bits.param, UInt<3>(0h0) connect _WIRE_110.bits.opcode, UInt<3>(0h0) connect _WIRE_110.valid, UInt<1>(0h0) connect _WIRE_110.ready, UInt<1>(0h0) wire _WIRE_111 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_111.bits, _WIRE_110.bits connect _WIRE_111.valid, _WIRE_110.valid connect _WIRE_111.ready, _WIRE_110.ready connect _WIRE_111.valid, UInt<1>(0h0) connect out[3].d.bits.corrupt, x1_anonOut_2.d.bits.corrupt connect out[3].d.bits.data, x1_anonOut_2.d.bits.data connect out[3].d.bits.denied, x1_anonOut_2.d.bits.denied connect out[3].d.bits.sink, x1_anonOut_2.d.bits.sink connect out[3].d.bits.source, x1_anonOut_2.d.bits.source connect out[3].d.bits.size, x1_anonOut_2.d.bits.size connect out[3].d.bits.param, x1_anonOut_2.d.bits.param connect out[3].d.bits.opcode, x1_anonOut_2.d.bits.opcode connect out[3].d.valid, x1_anonOut_2.d.valid connect x1_anonOut_2.d.ready, out[3].d.ready node _out_3_d_bits_sink_T = or(x1_anonOut_2.d.bits.sink, UInt<1>(0h0)) connect out[3].d.bits.sink, _out_3_d_bits_sink_T wire _WIRE_112 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_112.bits.sink, UInt<1>(0h0) connect _WIRE_112.valid, UInt<1>(0h0) connect _WIRE_112.ready, UInt<1>(0h0) wire _WIRE_113 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_113.bits, _WIRE_112.bits connect _WIRE_113.valid, _WIRE_112.valid connect _WIRE_113.ready, _WIRE_112.ready invalidate _WIRE_113.bits.sink invalidate _WIRE_113.valid invalidate _WIRE_113.ready wire _WIRE_114 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_114.bits.sink, UInt<1>(0h0) connect _WIRE_114.valid, UInt<1>(0h0) connect _WIRE_114.ready, UInt<1>(0h0) wire _WIRE_115 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_115.bits, _WIRE_114.bits connect _WIRE_115.valid, _WIRE_114.valid connect _WIRE_115.ready, _WIRE_114.ready invalidate _WIRE_115.bits.sink invalidate _WIRE_115.valid invalidate _WIRE_115.ready wire _WIRE_116 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_116.bits.sink, UInt<1>(0h0) connect _WIRE_116.valid, UInt<1>(0h0) connect _WIRE_116.ready, UInt<1>(0h0) wire _WIRE_117 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_117.bits, _WIRE_116.bits connect _WIRE_117.valid, _WIRE_116.valid connect _WIRE_117.ready, _WIRE_116.ready connect _WIRE_117.ready, UInt<1>(0h1) wire _WIRE_118 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_118.bits.sink, UInt<1>(0h0) connect _WIRE_118.valid, UInt<1>(0h0) connect _WIRE_118.ready, UInt<1>(0h0) wire _WIRE_119 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_119.bits, _WIRE_118.bits connect _WIRE_119.valid, _WIRE_118.valid connect _WIRE_119.ready, _WIRE_118.ready connect _WIRE_119.valid, UInt<1>(0h0) connect x1_anonOut_3.a.bits.corrupt, out[4].a.bits.corrupt connect x1_anonOut_3.a.bits.data, out[4].a.bits.data connect x1_anonOut_3.a.bits.mask, out[4].a.bits.mask connect x1_anonOut_3.a.bits.address, out[4].a.bits.address connect x1_anonOut_3.a.bits.source, out[4].a.bits.source connect x1_anonOut_3.a.bits.size, out[4].a.bits.size connect x1_anonOut_3.a.bits.param, out[4].a.bits.param connect x1_anonOut_3.a.bits.opcode, out[4].a.bits.opcode connect x1_anonOut_3.a.valid, out[4].a.valid connect out[4].a.ready, x1_anonOut_3.a.ready wire _WIRE_120 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_120.bits.corrupt, UInt<1>(0h0) connect _WIRE_120.bits.data, UInt<64>(0h0) connect _WIRE_120.bits.mask, UInt<8>(0h0) connect _WIRE_120.bits.address, UInt<32>(0h0) connect _WIRE_120.bits.source, UInt<7>(0h0) connect _WIRE_120.bits.size, UInt<4>(0h0) connect _WIRE_120.bits.param, UInt<2>(0h0) connect _WIRE_120.bits.opcode, UInt<3>(0h0) connect _WIRE_120.valid, UInt<1>(0h0) connect _WIRE_120.ready, UInt<1>(0h0) wire _WIRE_121 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_121.bits, _WIRE_120.bits connect _WIRE_121.valid, _WIRE_120.valid connect _WIRE_121.ready, _WIRE_120.ready invalidate _WIRE_121.bits.corrupt invalidate _WIRE_121.bits.data invalidate _WIRE_121.bits.mask invalidate _WIRE_121.bits.address invalidate _WIRE_121.bits.source invalidate _WIRE_121.bits.size invalidate _WIRE_121.bits.param invalidate _WIRE_121.bits.opcode invalidate _WIRE_121.valid invalidate _WIRE_121.ready wire _WIRE_122 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_122.bits.corrupt, UInt<1>(0h0) connect _WIRE_122.bits.data, UInt<64>(0h0) connect _WIRE_122.bits.mask, UInt<8>(0h0) connect _WIRE_122.bits.address, UInt<12>(0h0) connect _WIRE_122.bits.source, UInt<7>(0h0) connect _WIRE_122.bits.size, UInt<3>(0h0) connect _WIRE_122.bits.param, UInt<2>(0h0) connect _WIRE_122.bits.opcode, UInt<3>(0h0) connect _WIRE_122.valid, UInt<1>(0h0) connect _WIRE_122.ready, UInt<1>(0h0) wire _WIRE_123 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_123.bits, _WIRE_122.bits connect _WIRE_123.valid, _WIRE_122.valid connect _WIRE_123.ready, _WIRE_122.ready invalidate _WIRE_123.bits.corrupt invalidate _WIRE_123.bits.data invalidate _WIRE_123.bits.mask invalidate _WIRE_123.bits.address invalidate _WIRE_123.bits.source invalidate _WIRE_123.bits.size invalidate _WIRE_123.bits.param invalidate _WIRE_123.bits.opcode invalidate _WIRE_123.valid invalidate _WIRE_123.ready wire _WIRE_124 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_124.bits.corrupt, UInt<1>(0h0) connect _WIRE_124.bits.data, UInt<64>(0h0) connect _WIRE_124.bits.mask, UInt<8>(0h0) connect _WIRE_124.bits.address, UInt<32>(0h0) connect _WIRE_124.bits.source, UInt<7>(0h0) connect _WIRE_124.bits.size, UInt<4>(0h0) connect _WIRE_124.bits.param, UInt<2>(0h0) connect _WIRE_124.bits.opcode, UInt<3>(0h0) connect _WIRE_124.valid, UInt<1>(0h0) connect _WIRE_124.ready, UInt<1>(0h0) wire _WIRE_125 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_125.bits, _WIRE_124.bits connect _WIRE_125.valid, _WIRE_124.valid connect _WIRE_125.ready, _WIRE_124.ready connect _WIRE_125.valid, UInt<1>(0h0) wire _WIRE_126 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_126.bits.corrupt, UInt<1>(0h0) connect _WIRE_126.bits.data, UInt<64>(0h0) connect _WIRE_126.bits.mask, UInt<8>(0h0) connect _WIRE_126.bits.address, UInt<12>(0h0) connect _WIRE_126.bits.source, UInt<7>(0h0) connect _WIRE_126.bits.size, UInt<3>(0h0) connect _WIRE_126.bits.param, UInt<2>(0h0) connect _WIRE_126.bits.opcode, UInt<3>(0h0) connect _WIRE_126.valid, UInt<1>(0h0) connect _WIRE_126.ready, UInt<1>(0h0) wire _WIRE_127 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_127.bits, _WIRE_126.bits connect _WIRE_127.valid, _WIRE_126.valid connect _WIRE_127.ready, _WIRE_126.ready connect _WIRE_127.ready, UInt<1>(0h1) wire _WIRE_128 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_128.bits.corrupt, UInt<1>(0h0) connect _WIRE_128.bits.data, UInt<64>(0h0) connect _WIRE_128.bits.address, UInt<32>(0h0) connect _WIRE_128.bits.source, UInt<7>(0h0) connect _WIRE_128.bits.size, UInt<4>(0h0) connect _WIRE_128.bits.param, UInt<3>(0h0) connect _WIRE_128.bits.opcode, UInt<3>(0h0) connect _WIRE_128.valid, UInt<1>(0h0) connect _WIRE_128.ready, UInt<1>(0h0) wire _WIRE_129 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_129.bits, _WIRE_128.bits connect _WIRE_129.valid, _WIRE_128.valid connect _WIRE_129.ready, _WIRE_128.ready invalidate _WIRE_129.bits.corrupt invalidate _WIRE_129.bits.data invalidate _WIRE_129.bits.address invalidate _WIRE_129.bits.source invalidate _WIRE_129.bits.size invalidate _WIRE_129.bits.param invalidate _WIRE_129.bits.opcode invalidate _WIRE_129.valid invalidate _WIRE_129.ready wire _WIRE_130 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_130.bits.corrupt, UInt<1>(0h0) connect _WIRE_130.bits.data, UInt<64>(0h0) connect _WIRE_130.bits.address, UInt<12>(0h0) connect _WIRE_130.bits.source, UInt<7>(0h0) connect _WIRE_130.bits.size, UInt<3>(0h0) connect _WIRE_130.bits.param, UInt<3>(0h0) connect _WIRE_130.bits.opcode, UInt<3>(0h0) connect _WIRE_130.valid, UInt<1>(0h0) connect _WIRE_130.ready, UInt<1>(0h0) wire _WIRE_131 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_131.bits, _WIRE_130.bits connect _WIRE_131.valid, _WIRE_130.valid connect _WIRE_131.ready, _WIRE_130.ready invalidate _WIRE_131.bits.corrupt invalidate _WIRE_131.bits.data invalidate _WIRE_131.bits.address invalidate _WIRE_131.bits.source invalidate _WIRE_131.bits.size invalidate _WIRE_131.bits.param invalidate _WIRE_131.bits.opcode invalidate _WIRE_131.valid invalidate _WIRE_131.ready wire _WIRE_132 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_132.bits.corrupt, UInt<1>(0h0) connect _WIRE_132.bits.data, UInt<64>(0h0) connect _WIRE_132.bits.address, UInt<32>(0h0) connect _WIRE_132.bits.source, UInt<7>(0h0) connect _WIRE_132.bits.size, UInt<4>(0h0) connect _WIRE_132.bits.param, UInt<3>(0h0) connect _WIRE_132.bits.opcode, UInt<3>(0h0) connect _WIRE_132.valid, UInt<1>(0h0) connect _WIRE_132.ready, UInt<1>(0h0) wire _WIRE_133 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_133.bits, _WIRE_132.bits connect _WIRE_133.valid, _WIRE_132.valid connect _WIRE_133.ready, _WIRE_132.ready connect _WIRE_133.ready, UInt<1>(0h1) wire _WIRE_134 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_134.bits.corrupt, UInt<1>(0h0) connect _WIRE_134.bits.data, UInt<64>(0h0) connect _WIRE_134.bits.address, UInt<12>(0h0) connect _WIRE_134.bits.source, UInt<7>(0h0) connect _WIRE_134.bits.size, UInt<3>(0h0) connect _WIRE_134.bits.param, UInt<3>(0h0) connect _WIRE_134.bits.opcode, UInt<3>(0h0) connect _WIRE_134.valid, UInt<1>(0h0) connect _WIRE_134.ready, UInt<1>(0h0) wire _WIRE_135 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_135.bits, _WIRE_134.bits connect _WIRE_135.valid, _WIRE_134.valid connect _WIRE_135.ready, _WIRE_134.ready connect _WIRE_135.valid, UInt<1>(0h0) connect out[4].d.bits.corrupt, x1_anonOut_3.d.bits.corrupt connect out[4].d.bits.data, x1_anonOut_3.d.bits.data connect out[4].d.bits.denied, x1_anonOut_3.d.bits.denied connect out[4].d.bits.sink, x1_anonOut_3.d.bits.sink connect out[4].d.bits.source, x1_anonOut_3.d.bits.source connect out[4].d.bits.size, x1_anonOut_3.d.bits.size connect out[4].d.bits.param, x1_anonOut_3.d.bits.param connect out[4].d.bits.opcode, x1_anonOut_3.d.bits.opcode connect out[4].d.valid, x1_anonOut_3.d.valid connect x1_anonOut_3.d.ready, out[4].d.ready node _out_4_d_bits_sink_T = or(x1_anonOut_3.d.bits.sink, UInt<1>(0h0)) connect out[4].d.bits.sink, _out_4_d_bits_sink_T wire _WIRE_136 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_136.bits.sink, UInt<1>(0h0) connect _WIRE_136.valid, UInt<1>(0h0) connect _WIRE_136.ready, UInt<1>(0h0) wire _WIRE_137 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_137.bits, _WIRE_136.bits connect _WIRE_137.valid, _WIRE_136.valid connect _WIRE_137.ready, _WIRE_136.ready invalidate _WIRE_137.bits.sink invalidate _WIRE_137.valid invalidate _WIRE_137.ready wire _WIRE_138 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_138.bits.sink, UInt<1>(0h0) connect _WIRE_138.valid, UInt<1>(0h0) connect _WIRE_138.ready, UInt<1>(0h0) wire _WIRE_139 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_139.bits, _WIRE_138.bits connect _WIRE_139.valid, _WIRE_138.valid connect _WIRE_139.ready, _WIRE_138.ready invalidate _WIRE_139.bits.sink invalidate _WIRE_139.valid invalidate _WIRE_139.ready wire _WIRE_140 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_140.bits.sink, UInt<1>(0h0) connect _WIRE_140.valid, UInt<1>(0h0) connect _WIRE_140.ready, UInt<1>(0h0) wire _WIRE_141 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_141.bits, _WIRE_140.bits connect _WIRE_141.valid, _WIRE_140.valid connect _WIRE_141.ready, _WIRE_140.ready connect _WIRE_141.ready, UInt<1>(0h1) wire _WIRE_142 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_142.bits.sink, UInt<1>(0h0) connect _WIRE_142.valid, UInt<1>(0h0) connect _WIRE_142.ready, UInt<1>(0h0) wire _WIRE_143 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_143.bits, _WIRE_142.bits connect _WIRE_143.valid, _WIRE_142.valid connect _WIRE_143.ready, _WIRE_142.ready connect _WIRE_143.valid, UInt<1>(0h0) connect x1_anonOut_4.a.bits.corrupt, out[5].a.bits.corrupt connect x1_anonOut_4.a.bits.data, out[5].a.bits.data connect x1_anonOut_4.a.bits.mask, out[5].a.bits.mask connect x1_anonOut_4.a.bits.address, out[5].a.bits.address connect x1_anonOut_4.a.bits.source, out[5].a.bits.source connect x1_anonOut_4.a.bits.size, out[5].a.bits.size connect x1_anonOut_4.a.bits.param, out[5].a.bits.param connect x1_anonOut_4.a.bits.opcode, out[5].a.bits.opcode connect x1_anonOut_4.a.valid, out[5].a.valid connect out[5].a.ready, x1_anonOut_4.a.ready wire _WIRE_144 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_144.bits.corrupt, UInt<1>(0h0) connect _WIRE_144.bits.data, UInt<64>(0h0) connect _WIRE_144.bits.mask, UInt<8>(0h0) connect _WIRE_144.bits.address, UInt<32>(0h0) connect _WIRE_144.bits.source, UInt<7>(0h0) connect _WIRE_144.bits.size, UInt<4>(0h0) connect _WIRE_144.bits.param, UInt<2>(0h0) connect _WIRE_144.bits.opcode, UInt<3>(0h0) connect _WIRE_144.valid, UInt<1>(0h0) connect _WIRE_144.ready, UInt<1>(0h0) wire _WIRE_145 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_145.bits, _WIRE_144.bits connect _WIRE_145.valid, _WIRE_144.valid connect _WIRE_145.ready, _WIRE_144.ready invalidate _WIRE_145.bits.corrupt invalidate _WIRE_145.bits.data invalidate _WIRE_145.bits.mask invalidate _WIRE_145.bits.address invalidate _WIRE_145.bits.source invalidate _WIRE_145.bits.size invalidate _WIRE_145.bits.param invalidate _WIRE_145.bits.opcode invalidate _WIRE_145.valid invalidate _WIRE_145.ready wire _WIRE_146 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_146.bits.corrupt, UInt<1>(0h0) connect _WIRE_146.bits.data, UInt<64>(0h0) connect _WIRE_146.bits.mask, UInt<8>(0h0) connect _WIRE_146.bits.address, UInt<32>(0h0) connect _WIRE_146.bits.source, UInt<7>(0h0) connect _WIRE_146.bits.size, UInt<3>(0h0) connect _WIRE_146.bits.param, UInt<2>(0h0) connect _WIRE_146.bits.opcode, UInt<3>(0h0) connect _WIRE_146.valid, UInt<1>(0h0) connect _WIRE_146.ready, UInt<1>(0h0) wire _WIRE_147 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_147.bits, _WIRE_146.bits connect _WIRE_147.valid, _WIRE_146.valid connect _WIRE_147.ready, _WIRE_146.ready invalidate _WIRE_147.bits.corrupt invalidate _WIRE_147.bits.data invalidate _WIRE_147.bits.mask invalidate _WIRE_147.bits.address invalidate _WIRE_147.bits.source invalidate _WIRE_147.bits.size invalidate _WIRE_147.bits.param invalidate _WIRE_147.bits.opcode invalidate _WIRE_147.valid invalidate _WIRE_147.ready wire _WIRE_148 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_148.bits.corrupt, UInt<1>(0h0) connect _WIRE_148.bits.data, UInt<64>(0h0) connect _WIRE_148.bits.mask, UInt<8>(0h0) connect _WIRE_148.bits.address, UInt<32>(0h0) connect _WIRE_148.bits.source, UInt<7>(0h0) connect _WIRE_148.bits.size, UInt<4>(0h0) connect _WIRE_148.bits.param, UInt<2>(0h0) connect _WIRE_148.bits.opcode, UInt<3>(0h0) connect _WIRE_148.valid, UInt<1>(0h0) connect _WIRE_148.ready, UInt<1>(0h0) wire _WIRE_149 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_149.bits, _WIRE_148.bits connect _WIRE_149.valid, _WIRE_148.valid connect _WIRE_149.ready, _WIRE_148.ready connect _WIRE_149.valid, UInt<1>(0h0) wire _WIRE_150 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_150.bits.corrupt, UInt<1>(0h0) connect _WIRE_150.bits.data, UInt<64>(0h0) connect _WIRE_150.bits.mask, UInt<8>(0h0) connect _WIRE_150.bits.address, UInt<32>(0h0) connect _WIRE_150.bits.source, UInt<7>(0h0) connect _WIRE_150.bits.size, UInt<3>(0h0) connect _WIRE_150.bits.param, UInt<2>(0h0) connect _WIRE_150.bits.opcode, UInt<3>(0h0) connect _WIRE_150.valid, UInt<1>(0h0) connect _WIRE_150.ready, UInt<1>(0h0) wire _WIRE_151 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_151.bits, _WIRE_150.bits connect _WIRE_151.valid, _WIRE_150.valid connect _WIRE_151.ready, _WIRE_150.ready connect _WIRE_151.ready, UInt<1>(0h1) wire _WIRE_152 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_152.bits.corrupt, UInt<1>(0h0) connect _WIRE_152.bits.data, UInt<64>(0h0) connect _WIRE_152.bits.address, UInt<32>(0h0) connect _WIRE_152.bits.source, UInt<7>(0h0) connect _WIRE_152.bits.size, UInt<4>(0h0) connect _WIRE_152.bits.param, UInt<3>(0h0) connect _WIRE_152.bits.opcode, UInt<3>(0h0) connect _WIRE_152.valid, UInt<1>(0h0) connect _WIRE_152.ready, UInt<1>(0h0) wire _WIRE_153 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_153.bits, _WIRE_152.bits connect _WIRE_153.valid, _WIRE_152.valid connect _WIRE_153.ready, _WIRE_152.ready invalidate _WIRE_153.bits.corrupt invalidate _WIRE_153.bits.data invalidate _WIRE_153.bits.address invalidate _WIRE_153.bits.source invalidate _WIRE_153.bits.size invalidate _WIRE_153.bits.param invalidate _WIRE_153.bits.opcode invalidate _WIRE_153.valid invalidate _WIRE_153.ready wire _WIRE_154 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_154.bits.corrupt, UInt<1>(0h0) connect _WIRE_154.bits.data, UInt<64>(0h0) connect _WIRE_154.bits.address, UInt<32>(0h0) connect _WIRE_154.bits.source, UInt<7>(0h0) connect _WIRE_154.bits.size, UInt<3>(0h0) connect _WIRE_154.bits.param, UInt<3>(0h0) connect _WIRE_154.bits.opcode, UInt<3>(0h0) connect _WIRE_154.valid, UInt<1>(0h0) connect _WIRE_154.ready, UInt<1>(0h0) wire _WIRE_155 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_155.bits, _WIRE_154.bits connect _WIRE_155.valid, _WIRE_154.valid connect _WIRE_155.ready, _WIRE_154.ready invalidate _WIRE_155.bits.corrupt invalidate _WIRE_155.bits.data invalidate _WIRE_155.bits.address invalidate _WIRE_155.bits.source invalidate _WIRE_155.bits.size invalidate _WIRE_155.bits.param invalidate _WIRE_155.bits.opcode invalidate _WIRE_155.valid invalidate _WIRE_155.ready wire _WIRE_156 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_156.bits.corrupt, UInt<1>(0h0) connect _WIRE_156.bits.data, UInt<64>(0h0) connect _WIRE_156.bits.address, UInt<32>(0h0) connect _WIRE_156.bits.source, UInt<7>(0h0) connect _WIRE_156.bits.size, UInt<4>(0h0) connect _WIRE_156.bits.param, UInt<3>(0h0) connect _WIRE_156.bits.opcode, UInt<3>(0h0) connect _WIRE_156.valid, UInt<1>(0h0) connect _WIRE_156.ready, UInt<1>(0h0) wire _WIRE_157 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_157.bits, _WIRE_156.bits connect _WIRE_157.valid, _WIRE_156.valid connect _WIRE_157.ready, _WIRE_156.ready connect _WIRE_157.ready, UInt<1>(0h1) wire _WIRE_158 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_158.bits.corrupt, UInt<1>(0h0) connect _WIRE_158.bits.data, UInt<64>(0h0) connect _WIRE_158.bits.address, UInt<32>(0h0) connect _WIRE_158.bits.source, UInt<7>(0h0) connect _WIRE_158.bits.size, UInt<3>(0h0) connect _WIRE_158.bits.param, UInt<3>(0h0) connect _WIRE_158.bits.opcode, UInt<3>(0h0) connect _WIRE_158.valid, UInt<1>(0h0) connect _WIRE_158.ready, UInt<1>(0h0) wire _WIRE_159 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_159.bits, _WIRE_158.bits connect _WIRE_159.valid, _WIRE_158.valid connect _WIRE_159.ready, _WIRE_158.ready connect _WIRE_159.valid, UInt<1>(0h0) connect out[5].d.bits.corrupt, x1_anonOut_4.d.bits.corrupt connect out[5].d.bits.data, x1_anonOut_4.d.bits.data connect out[5].d.bits.denied, x1_anonOut_4.d.bits.denied connect out[5].d.bits.sink, x1_anonOut_4.d.bits.sink connect out[5].d.bits.source, x1_anonOut_4.d.bits.source connect out[5].d.bits.size, x1_anonOut_4.d.bits.size connect out[5].d.bits.param, x1_anonOut_4.d.bits.param connect out[5].d.bits.opcode, x1_anonOut_4.d.bits.opcode connect out[5].d.valid, x1_anonOut_4.d.valid connect x1_anonOut_4.d.ready, out[5].d.ready node _out_5_d_bits_sink_T = or(x1_anonOut_4.d.bits.sink, UInt<1>(0h0)) connect out[5].d.bits.sink, _out_5_d_bits_sink_T wire _WIRE_160 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_160.bits.sink, UInt<1>(0h0) connect _WIRE_160.valid, UInt<1>(0h0) connect _WIRE_160.ready, UInt<1>(0h0) wire _WIRE_161 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_161.bits, _WIRE_160.bits connect _WIRE_161.valid, _WIRE_160.valid connect _WIRE_161.ready, _WIRE_160.ready invalidate _WIRE_161.bits.sink invalidate _WIRE_161.valid invalidate _WIRE_161.ready wire _WIRE_162 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_162.bits.sink, UInt<1>(0h0) connect _WIRE_162.valid, UInt<1>(0h0) connect _WIRE_162.ready, UInt<1>(0h0) wire _WIRE_163 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_163.bits, _WIRE_162.bits connect _WIRE_163.valid, _WIRE_162.valid connect _WIRE_163.ready, _WIRE_162.ready invalidate _WIRE_163.bits.sink invalidate _WIRE_163.valid invalidate _WIRE_163.ready wire _WIRE_164 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_164.bits.sink, UInt<1>(0h0) connect _WIRE_164.valid, UInt<1>(0h0) connect _WIRE_164.ready, UInt<1>(0h0) wire _WIRE_165 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_165.bits, _WIRE_164.bits connect _WIRE_165.valid, _WIRE_164.valid connect _WIRE_165.ready, _WIRE_164.ready connect _WIRE_165.ready, UInt<1>(0h1) wire _WIRE_166 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_166.bits.sink, UInt<1>(0h0) connect _WIRE_166.valid, UInt<1>(0h0) connect _WIRE_166.ready, UInt<1>(0h0) wire _WIRE_167 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_167.bits, _WIRE_166.bits connect _WIRE_167.valid, _WIRE_166.valid connect _WIRE_167.ready, _WIRE_166.ready connect _WIRE_167.valid, UInt<1>(0h0) connect x1_anonOut_5.a.bits.corrupt, out[6].a.bits.corrupt connect x1_anonOut_5.a.bits.data, out[6].a.bits.data connect x1_anonOut_5.a.bits.mask, out[6].a.bits.mask connect x1_anonOut_5.a.bits.address, out[6].a.bits.address connect x1_anonOut_5.a.bits.source, out[6].a.bits.source connect x1_anonOut_5.a.bits.size, out[6].a.bits.size connect x1_anonOut_5.a.bits.param, out[6].a.bits.param connect x1_anonOut_5.a.bits.opcode, out[6].a.bits.opcode connect x1_anonOut_5.a.valid, out[6].a.valid connect out[6].a.ready, x1_anonOut_5.a.ready wire _WIRE_168 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_168.bits.corrupt, UInt<1>(0h0) connect _WIRE_168.bits.data, UInt<64>(0h0) connect _WIRE_168.bits.mask, UInt<8>(0h0) connect _WIRE_168.bits.address, UInt<32>(0h0) connect _WIRE_168.bits.source, UInt<7>(0h0) connect _WIRE_168.bits.size, UInt<4>(0h0) connect _WIRE_168.bits.param, UInt<2>(0h0) connect _WIRE_168.bits.opcode, UInt<3>(0h0) connect _WIRE_168.valid, UInt<1>(0h0) connect _WIRE_168.ready, UInt<1>(0h0) wire _WIRE_169 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_169.bits, _WIRE_168.bits connect _WIRE_169.valid, _WIRE_168.valid connect _WIRE_169.ready, _WIRE_168.ready invalidate _WIRE_169.bits.corrupt invalidate _WIRE_169.bits.data invalidate _WIRE_169.bits.mask invalidate _WIRE_169.bits.address invalidate _WIRE_169.bits.source invalidate _WIRE_169.bits.size invalidate _WIRE_169.bits.param invalidate _WIRE_169.bits.opcode invalidate _WIRE_169.valid invalidate _WIRE_169.ready wire _WIRE_170 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_170.bits.corrupt, UInt<1>(0h0) connect _WIRE_170.bits.data, UInt<64>(0h0) connect _WIRE_170.bits.mask, UInt<8>(0h0) connect _WIRE_170.bits.address, UInt<17>(0h0) connect _WIRE_170.bits.source, UInt<7>(0h0) connect _WIRE_170.bits.size, UInt<3>(0h0) connect _WIRE_170.bits.param, UInt<2>(0h0) connect _WIRE_170.bits.opcode, UInt<3>(0h0) connect _WIRE_170.valid, UInt<1>(0h0) connect _WIRE_170.ready, UInt<1>(0h0) wire _WIRE_171 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_171.bits, _WIRE_170.bits connect _WIRE_171.valid, _WIRE_170.valid connect _WIRE_171.ready, _WIRE_170.ready invalidate _WIRE_171.bits.corrupt invalidate _WIRE_171.bits.data invalidate _WIRE_171.bits.mask invalidate _WIRE_171.bits.address invalidate _WIRE_171.bits.source invalidate _WIRE_171.bits.size invalidate _WIRE_171.bits.param invalidate _WIRE_171.bits.opcode invalidate _WIRE_171.valid invalidate _WIRE_171.ready wire _WIRE_172 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_172.bits.corrupt, UInt<1>(0h0) connect _WIRE_172.bits.data, UInt<64>(0h0) connect _WIRE_172.bits.mask, UInt<8>(0h0) connect _WIRE_172.bits.address, UInt<32>(0h0) connect _WIRE_172.bits.source, UInt<7>(0h0) connect _WIRE_172.bits.size, UInt<4>(0h0) connect _WIRE_172.bits.param, UInt<2>(0h0) connect _WIRE_172.bits.opcode, UInt<3>(0h0) connect _WIRE_172.valid, UInt<1>(0h0) connect _WIRE_172.ready, UInt<1>(0h0) wire _WIRE_173 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_173.bits, _WIRE_172.bits connect _WIRE_173.valid, _WIRE_172.valid connect _WIRE_173.ready, _WIRE_172.ready connect _WIRE_173.valid, UInt<1>(0h0) wire _WIRE_174 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_174.bits.corrupt, UInt<1>(0h0) connect _WIRE_174.bits.data, UInt<64>(0h0) connect _WIRE_174.bits.mask, UInt<8>(0h0) connect _WIRE_174.bits.address, UInt<17>(0h0) connect _WIRE_174.bits.source, UInt<7>(0h0) connect _WIRE_174.bits.size, UInt<3>(0h0) connect _WIRE_174.bits.param, UInt<2>(0h0) connect _WIRE_174.bits.opcode, UInt<3>(0h0) connect _WIRE_174.valid, UInt<1>(0h0) connect _WIRE_174.ready, UInt<1>(0h0) wire _WIRE_175 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_175.bits, _WIRE_174.bits connect _WIRE_175.valid, _WIRE_174.valid connect _WIRE_175.ready, _WIRE_174.ready connect _WIRE_175.ready, UInt<1>(0h1) wire _WIRE_176 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_176.bits.corrupt, UInt<1>(0h0) connect _WIRE_176.bits.data, UInt<64>(0h0) connect _WIRE_176.bits.address, UInt<32>(0h0) connect _WIRE_176.bits.source, UInt<7>(0h0) connect _WIRE_176.bits.size, UInt<4>(0h0) connect _WIRE_176.bits.param, UInt<3>(0h0) connect _WIRE_176.bits.opcode, UInt<3>(0h0) connect _WIRE_176.valid, UInt<1>(0h0) connect _WIRE_176.ready, UInt<1>(0h0) wire _WIRE_177 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_177.bits, _WIRE_176.bits connect _WIRE_177.valid, _WIRE_176.valid connect _WIRE_177.ready, _WIRE_176.ready invalidate _WIRE_177.bits.corrupt invalidate _WIRE_177.bits.data invalidate _WIRE_177.bits.address invalidate _WIRE_177.bits.source invalidate _WIRE_177.bits.size invalidate _WIRE_177.bits.param invalidate _WIRE_177.bits.opcode invalidate _WIRE_177.valid invalidate _WIRE_177.ready wire _WIRE_178 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_178.bits.corrupt, UInt<1>(0h0) connect _WIRE_178.bits.data, UInt<64>(0h0) connect _WIRE_178.bits.address, UInt<17>(0h0) connect _WIRE_178.bits.source, UInt<7>(0h0) connect _WIRE_178.bits.size, UInt<3>(0h0) connect _WIRE_178.bits.param, UInt<3>(0h0) connect _WIRE_178.bits.opcode, UInt<3>(0h0) connect _WIRE_178.valid, UInt<1>(0h0) connect _WIRE_178.ready, UInt<1>(0h0) wire _WIRE_179 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_179.bits, _WIRE_178.bits connect _WIRE_179.valid, _WIRE_178.valid connect _WIRE_179.ready, _WIRE_178.ready invalidate _WIRE_179.bits.corrupt invalidate _WIRE_179.bits.data invalidate _WIRE_179.bits.address invalidate _WIRE_179.bits.source invalidate _WIRE_179.bits.size invalidate _WIRE_179.bits.param invalidate _WIRE_179.bits.opcode invalidate _WIRE_179.valid invalidate _WIRE_179.ready wire _WIRE_180 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_180.bits.corrupt, UInt<1>(0h0) connect _WIRE_180.bits.data, UInt<64>(0h0) connect _WIRE_180.bits.address, UInt<32>(0h0) connect _WIRE_180.bits.source, UInt<7>(0h0) connect _WIRE_180.bits.size, UInt<4>(0h0) connect _WIRE_180.bits.param, UInt<3>(0h0) connect _WIRE_180.bits.opcode, UInt<3>(0h0) connect _WIRE_180.valid, UInt<1>(0h0) connect _WIRE_180.ready, UInt<1>(0h0) wire _WIRE_181 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_181.bits, _WIRE_180.bits connect _WIRE_181.valid, _WIRE_180.valid connect _WIRE_181.ready, _WIRE_180.ready connect _WIRE_181.ready, UInt<1>(0h1) wire _WIRE_182 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_182.bits.corrupt, UInt<1>(0h0) connect _WIRE_182.bits.data, UInt<64>(0h0) connect _WIRE_182.bits.address, UInt<17>(0h0) connect _WIRE_182.bits.source, UInt<7>(0h0) connect _WIRE_182.bits.size, UInt<3>(0h0) connect _WIRE_182.bits.param, UInt<3>(0h0) connect _WIRE_182.bits.opcode, UInt<3>(0h0) connect _WIRE_182.valid, UInt<1>(0h0) connect _WIRE_182.ready, UInt<1>(0h0) wire _WIRE_183 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_183.bits, _WIRE_182.bits connect _WIRE_183.valid, _WIRE_182.valid connect _WIRE_183.ready, _WIRE_182.ready connect _WIRE_183.valid, UInt<1>(0h0) connect out[6].d.bits.corrupt, x1_anonOut_5.d.bits.corrupt connect out[6].d.bits.data, x1_anonOut_5.d.bits.data connect out[6].d.bits.denied, x1_anonOut_5.d.bits.denied connect out[6].d.bits.sink, x1_anonOut_5.d.bits.sink connect out[6].d.bits.source, x1_anonOut_5.d.bits.source connect out[6].d.bits.size, x1_anonOut_5.d.bits.size connect out[6].d.bits.param, x1_anonOut_5.d.bits.param connect out[6].d.bits.opcode, x1_anonOut_5.d.bits.opcode connect out[6].d.valid, x1_anonOut_5.d.valid connect x1_anonOut_5.d.ready, out[6].d.ready node _out_6_d_bits_sink_T = or(x1_anonOut_5.d.bits.sink, UInt<1>(0h0)) connect out[6].d.bits.sink, _out_6_d_bits_sink_T wire _WIRE_184 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_184.bits.sink, UInt<1>(0h0) connect _WIRE_184.valid, UInt<1>(0h0) connect _WIRE_184.ready, UInt<1>(0h0) wire _WIRE_185 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_185.bits, _WIRE_184.bits connect _WIRE_185.valid, _WIRE_184.valid connect _WIRE_185.ready, _WIRE_184.ready invalidate _WIRE_185.bits.sink invalidate _WIRE_185.valid invalidate _WIRE_185.ready wire _WIRE_186 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_186.bits.sink, UInt<1>(0h0) connect _WIRE_186.valid, UInt<1>(0h0) connect _WIRE_186.ready, UInt<1>(0h0) wire _WIRE_187 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_187.bits, _WIRE_186.bits connect _WIRE_187.valid, _WIRE_186.valid connect _WIRE_187.ready, _WIRE_186.ready invalidate _WIRE_187.bits.sink invalidate _WIRE_187.valid invalidate _WIRE_187.ready wire _WIRE_188 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_188.bits.sink, UInt<1>(0h0) connect _WIRE_188.valid, UInt<1>(0h0) connect _WIRE_188.ready, UInt<1>(0h0) wire _WIRE_189 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_189.bits, _WIRE_188.bits connect _WIRE_189.valid, _WIRE_188.valid connect _WIRE_189.ready, _WIRE_188.ready connect _WIRE_189.ready, UInt<1>(0h1) wire _WIRE_190 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_190.bits.sink, UInt<1>(0h0) connect _WIRE_190.valid, UInt<1>(0h0) connect _WIRE_190.ready, UInt<1>(0h0) wire _WIRE_191 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_191.bits, _WIRE_190.bits connect _WIRE_191.valid, _WIRE_190.valid connect _WIRE_191.ready, _WIRE_190.ready connect _WIRE_191.valid, UInt<1>(0h0) connect x1_anonOut_6.a.bits.corrupt, out[7].a.bits.corrupt connect x1_anonOut_6.a.bits.data, out[7].a.bits.data connect x1_anonOut_6.a.bits.mask, out[7].a.bits.mask connect x1_anonOut_6.a.bits.address, out[7].a.bits.address connect x1_anonOut_6.a.bits.source, out[7].a.bits.source connect x1_anonOut_6.a.bits.size, out[7].a.bits.size connect x1_anonOut_6.a.bits.param, out[7].a.bits.param connect x1_anonOut_6.a.bits.opcode, out[7].a.bits.opcode connect x1_anonOut_6.a.valid, out[7].a.valid connect out[7].a.ready, x1_anonOut_6.a.ready wire _WIRE_192 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_192.bits.corrupt, UInt<1>(0h0) connect _WIRE_192.bits.data, UInt<64>(0h0) connect _WIRE_192.bits.mask, UInt<8>(0h0) connect _WIRE_192.bits.address, UInt<32>(0h0) connect _WIRE_192.bits.source, UInt<7>(0h0) connect _WIRE_192.bits.size, UInt<4>(0h0) connect _WIRE_192.bits.param, UInt<2>(0h0) connect _WIRE_192.bits.opcode, UInt<3>(0h0) connect _WIRE_192.valid, UInt<1>(0h0) connect _WIRE_192.ready, UInt<1>(0h0) wire _WIRE_193 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_193.bits, _WIRE_192.bits connect _WIRE_193.valid, _WIRE_192.valid connect _WIRE_193.ready, _WIRE_192.ready invalidate _WIRE_193.bits.corrupt invalidate _WIRE_193.bits.data invalidate _WIRE_193.bits.mask invalidate _WIRE_193.bits.address invalidate _WIRE_193.bits.source invalidate _WIRE_193.bits.size invalidate _WIRE_193.bits.param invalidate _WIRE_193.bits.opcode invalidate _WIRE_193.valid invalidate _WIRE_193.ready wire _WIRE_194 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_194.bits.corrupt, UInt<1>(0h0) connect _WIRE_194.bits.data, UInt<64>(0h0) connect _WIRE_194.bits.mask, UInt<8>(0h0) connect _WIRE_194.bits.address, UInt<21>(0h0) connect _WIRE_194.bits.source, UInt<7>(0h0) connect _WIRE_194.bits.size, UInt<3>(0h0) connect _WIRE_194.bits.param, UInt<2>(0h0) connect _WIRE_194.bits.opcode, UInt<3>(0h0) connect _WIRE_194.valid, UInt<1>(0h0) connect _WIRE_194.ready, UInt<1>(0h0) wire _WIRE_195 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_195.bits, _WIRE_194.bits connect _WIRE_195.valid, _WIRE_194.valid connect _WIRE_195.ready, _WIRE_194.ready invalidate _WIRE_195.bits.corrupt invalidate _WIRE_195.bits.data invalidate _WIRE_195.bits.mask invalidate _WIRE_195.bits.address invalidate _WIRE_195.bits.source invalidate _WIRE_195.bits.size invalidate _WIRE_195.bits.param invalidate _WIRE_195.bits.opcode invalidate _WIRE_195.valid invalidate _WIRE_195.ready wire _WIRE_196 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_196.bits.corrupt, UInt<1>(0h0) connect _WIRE_196.bits.data, UInt<64>(0h0) connect _WIRE_196.bits.mask, UInt<8>(0h0) connect _WIRE_196.bits.address, UInt<32>(0h0) connect _WIRE_196.bits.source, UInt<7>(0h0) connect _WIRE_196.bits.size, UInt<4>(0h0) connect _WIRE_196.bits.param, UInt<2>(0h0) connect _WIRE_196.bits.opcode, UInt<3>(0h0) connect _WIRE_196.valid, UInt<1>(0h0) connect _WIRE_196.ready, UInt<1>(0h0) wire _WIRE_197 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_197.bits, _WIRE_196.bits connect _WIRE_197.valid, _WIRE_196.valid connect _WIRE_197.ready, _WIRE_196.ready connect _WIRE_197.valid, UInt<1>(0h0) wire _WIRE_198 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_198.bits.corrupt, UInt<1>(0h0) connect _WIRE_198.bits.data, UInt<64>(0h0) connect _WIRE_198.bits.mask, UInt<8>(0h0) connect _WIRE_198.bits.address, UInt<21>(0h0) connect _WIRE_198.bits.source, UInt<7>(0h0) connect _WIRE_198.bits.size, UInt<3>(0h0) connect _WIRE_198.bits.param, UInt<2>(0h0) connect _WIRE_198.bits.opcode, UInt<3>(0h0) connect _WIRE_198.valid, UInt<1>(0h0) connect _WIRE_198.ready, UInt<1>(0h0) wire _WIRE_199 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_199.bits, _WIRE_198.bits connect _WIRE_199.valid, _WIRE_198.valid connect _WIRE_199.ready, _WIRE_198.ready connect _WIRE_199.ready, UInt<1>(0h1) wire _WIRE_200 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_200.bits.corrupt, UInt<1>(0h0) connect _WIRE_200.bits.data, UInt<64>(0h0) connect _WIRE_200.bits.address, UInt<32>(0h0) connect _WIRE_200.bits.source, UInt<7>(0h0) connect _WIRE_200.bits.size, UInt<4>(0h0) connect _WIRE_200.bits.param, UInt<3>(0h0) connect _WIRE_200.bits.opcode, UInt<3>(0h0) connect _WIRE_200.valid, UInt<1>(0h0) connect _WIRE_200.ready, UInt<1>(0h0) wire _WIRE_201 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_201.bits, _WIRE_200.bits connect _WIRE_201.valid, _WIRE_200.valid connect _WIRE_201.ready, _WIRE_200.ready invalidate _WIRE_201.bits.corrupt invalidate _WIRE_201.bits.data invalidate _WIRE_201.bits.address invalidate _WIRE_201.bits.source invalidate _WIRE_201.bits.size invalidate _WIRE_201.bits.param invalidate _WIRE_201.bits.opcode invalidate _WIRE_201.valid invalidate _WIRE_201.ready wire _WIRE_202 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_202.bits.corrupt, UInt<1>(0h0) connect _WIRE_202.bits.data, UInt<64>(0h0) connect _WIRE_202.bits.address, UInt<21>(0h0) connect _WIRE_202.bits.source, UInt<7>(0h0) connect _WIRE_202.bits.size, UInt<3>(0h0) connect _WIRE_202.bits.param, UInt<3>(0h0) connect _WIRE_202.bits.opcode, UInt<3>(0h0) connect _WIRE_202.valid, UInt<1>(0h0) connect _WIRE_202.ready, UInt<1>(0h0) wire _WIRE_203 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_203.bits, _WIRE_202.bits connect _WIRE_203.valid, _WIRE_202.valid connect _WIRE_203.ready, _WIRE_202.ready invalidate _WIRE_203.bits.corrupt invalidate _WIRE_203.bits.data invalidate _WIRE_203.bits.address invalidate _WIRE_203.bits.source invalidate _WIRE_203.bits.size invalidate _WIRE_203.bits.param invalidate _WIRE_203.bits.opcode invalidate _WIRE_203.valid invalidate _WIRE_203.ready wire _WIRE_204 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_204.bits.corrupt, UInt<1>(0h0) connect _WIRE_204.bits.data, UInt<64>(0h0) connect _WIRE_204.bits.address, UInt<32>(0h0) connect _WIRE_204.bits.source, UInt<7>(0h0) connect _WIRE_204.bits.size, UInt<4>(0h0) connect _WIRE_204.bits.param, UInt<3>(0h0) connect _WIRE_204.bits.opcode, UInt<3>(0h0) connect _WIRE_204.valid, UInt<1>(0h0) connect _WIRE_204.ready, UInt<1>(0h0) wire _WIRE_205 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_205.bits, _WIRE_204.bits connect _WIRE_205.valid, _WIRE_204.valid connect _WIRE_205.ready, _WIRE_204.ready connect _WIRE_205.ready, UInt<1>(0h1) wire _WIRE_206 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_206.bits.corrupt, UInt<1>(0h0) connect _WIRE_206.bits.data, UInt<64>(0h0) connect _WIRE_206.bits.address, UInt<21>(0h0) connect _WIRE_206.bits.source, UInt<7>(0h0) connect _WIRE_206.bits.size, UInt<3>(0h0) connect _WIRE_206.bits.param, UInt<3>(0h0) connect _WIRE_206.bits.opcode, UInt<3>(0h0) connect _WIRE_206.valid, UInt<1>(0h0) connect _WIRE_206.ready, UInt<1>(0h0) wire _WIRE_207 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_207.bits, _WIRE_206.bits connect _WIRE_207.valid, _WIRE_206.valid connect _WIRE_207.ready, _WIRE_206.ready connect _WIRE_207.valid, UInt<1>(0h0) connect out[7].d.bits.corrupt, x1_anonOut_6.d.bits.corrupt connect out[7].d.bits.data, x1_anonOut_6.d.bits.data connect out[7].d.bits.denied, x1_anonOut_6.d.bits.denied connect out[7].d.bits.sink, x1_anonOut_6.d.bits.sink connect out[7].d.bits.source, x1_anonOut_6.d.bits.source connect out[7].d.bits.size, x1_anonOut_6.d.bits.size connect out[7].d.bits.param, x1_anonOut_6.d.bits.param connect out[7].d.bits.opcode, x1_anonOut_6.d.bits.opcode connect out[7].d.valid, x1_anonOut_6.d.valid connect x1_anonOut_6.d.ready, out[7].d.ready node _out_7_d_bits_sink_T = or(x1_anonOut_6.d.bits.sink, UInt<1>(0h0)) connect out[7].d.bits.sink, _out_7_d_bits_sink_T wire _WIRE_208 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_208.bits.sink, UInt<1>(0h0) connect _WIRE_208.valid, UInt<1>(0h0) connect _WIRE_208.ready, UInt<1>(0h0) wire _WIRE_209 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_209.bits, _WIRE_208.bits connect _WIRE_209.valid, _WIRE_208.valid connect _WIRE_209.ready, _WIRE_208.ready invalidate _WIRE_209.bits.sink invalidate _WIRE_209.valid invalidate _WIRE_209.ready wire _WIRE_210 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_210.bits.sink, UInt<1>(0h0) connect _WIRE_210.valid, UInt<1>(0h0) connect _WIRE_210.ready, UInt<1>(0h0) wire _WIRE_211 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_211.bits, _WIRE_210.bits connect _WIRE_211.valid, _WIRE_210.valid connect _WIRE_211.ready, _WIRE_210.ready invalidate _WIRE_211.bits.sink invalidate _WIRE_211.valid invalidate _WIRE_211.ready wire _WIRE_212 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_212.bits.sink, UInt<1>(0h0) connect _WIRE_212.valid, UInt<1>(0h0) connect _WIRE_212.ready, UInt<1>(0h0) wire _WIRE_213 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_213.bits, _WIRE_212.bits connect _WIRE_213.valid, _WIRE_212.valid connect _WIRE_213.ready, _WIRE_212.ready connect _WIRE_213.ready, UInt<1>(0h1) wire _WIRE_214 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_214.bits.sink, UInt<1>(0h0) connect _WIRE_214.valid, UInt<1>(0h0) connect _WIRE_214.ready, UInt<1>(0h0) wire _WIRE_215 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_215.bits, _WIRE_214.bits connect _WIRE_215.valid, _WIRE_214.valid connect _WIRE_215.ready, _WIRE_214.ready connect _WIRE_215.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<7>(0h0) connect _addressC_WIRE.bits.size, UInt<4>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<14>(0h3000)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h9a113000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<13>(0h1000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h9a113000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<29>(0h10000000)) node _requestAIO_T_11 = cvt(_requestAIO_T_10) node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h9a113000))) node _requestAIO_T_13 = asSInt(_requestAIO_T_12) node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) node _requestAIO_T_15 = or(_requestAIO_T_9, _requestAIO_T_14) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_15) node _requestAIO_T_16 = xor(in[0].a.bits.address, UInt<26>(0h2000000)) node _requestAIO_T_17 = cvt(_requestAIO_T_16) node _requestAIO_T_18 = and(_requestAIO_T_17, asSInt(UInt<33>(0h9a110000))) node _requestAIO_T_19 = asSInt(_requestAIO_T_18) node _requestAIO_T_20 = eq(_requestAIO_T_19, asSInt(UInt<1>(0h0))) node requestAIO_0_2 = or(UInt<1>(0h0), _requestAIO_T_20) node _requestAIO_T_21 = xor(in[0].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_22 = cvt(_requestAIO_T_21) node _requestAIO_T_23 = and(_requestAIO_T_22, asSInt(UInt<33>(0h98000000))) node _requestAIO_T_24 = asSInt(_requestAIO_T_23) node _requestAIO_T_25 = eq(_requestAIO_T_24, asSInt(UInt<1>(0h0))) node requestAIO_0_3 = or(UInt<1>(0h0), _requestAIO_T_25) node _requestAIO_T_26 = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_27 = cvt(_requestAIO_T_26) node _requestAIO_T_28 = and(_requestAIO_T_27, asSInt(UInt<33>(0h9a113000))) node _requestAIO_T_29 = asSInt(_requestAIO_T_28) node _requestAIO_T_30 = eq(_requestAIO_T_29, asSInt(UInt<1>(0h0))) node requestAIO_0_4 = or(UInt<1>(0h0), _requestAIO_T_30) node _requestAIO_T_31 = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_32 = cvt(_requestAIO_T_31) node _requestAIO_T_33 = and(_requestAIO_T_32, asSInt(UInt<33>(0h9a110000))) node _requestAIO_T_34 = asSInt(_requestAIO_T_33) node _requestAIO_T_35 = eq(_requestAIO_T_34, asSInt(UInt<1>(0h0))) node requestAIO_0_5 = or(UInt<1>(0h0), _requestAIO_T_35) node _requestAIO_T_36 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_37 = cvt(_requestAIO_T_36) node _requestAIO_T_38 = and(_requestAIO_T_37, asSInt(UInt<33>(0h9a110000))) node _requestAIO_T_39 = asSInt(_requestAIO_T_38) node _requestAIO_T_40 = eq(_requestAIO_T_39, asSInt(UInt<1>(0h0))) node requestAIO_0_6 = or(UInt<1>(0h0), _requestAIO_T_40) node _requestAIO_T_41 = xor(in[0].a.bits.address, UInt<21>(0h100000)) node _requestAIO_T_42 = cvt(_requestAIO_T_41) node _requestAIO_T_43 = and(_requestAIO_T_42, asSInt(UInt<33>(0h9a103000))) node _requestAIO_T_44 = asSInt(_requestAIO_T_43) node _requestAIO_T_45 = eq(_requestAIO_T_44, asSInt(UInt<1>(0h0))) node requestAIO_0_7 = or(UInt<1>(0h0), _requestAIO_T_45) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestCIO_T_10 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_11 = cvt(_requestCIO_T_10) node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) node _requestCIO_T_13 = asSInt(_requestCIO_T_12) node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) node requestCIO_0_2 = or(UInt<1>(0h1), _requestCIO_T_14) node _requestCIO_T_15 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_16 = cvt(_requestCIO_T_15) node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) node _requestCIO_T_18 = asSInt(_requestCIO_T_17) node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) node requestCIO_0_3 = or(UInt<1>(0h1), _requestCIO_T_19) node _requestCIO_T_20 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_21 = cvt(_requestCIO_T_20) node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0))) node _requestCIO_T_23 = asSInt(_requestCIO_T_22) node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0))) node requestCIO_0_4 = or(UInt<1>(0h1), _requestCIO_T_24) node _requestCIO_T_25 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_26 = cvt(_requestCIO_T_25) node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0))) node _requestCIO_T_28 = asSInt(_requestCIO_T_27) node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0))) node requestCIO_0_5 = or(UInt<1>(0h1), _requestCIO_T_29) node _requestCIO_T_30 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_31 = cvt(_requestCIO_T_30) node _requestCIO_T_32 = and(_requestCIO_T_31, asSInt(UInt<1>(0h0))) node _requestCIO_T_33 = asSInt(_requestCIO_T_32) node _requestCIO_T_34 = eq(_requestCIO_T_33, asSInt(UInt<1>(0h0))) node requestCIO_0_6 = or(UInt<1>(0h1), _requestCIO_T_34) node _requestCIO_T_35 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_36 = cvt(_requestCIO_T_35) node _requestCIO_T_37 = and(_requestCIO_T_36, asSInt(UInt<1>(0h0))) node _requestCIO_T_38 = asSInt(_requestCIO_T_37) node _requestCIO_T_39 = eq(_requestCIO_T_38, asSInt(UInt<1>(0h0))) node requestCIO_0_7 = or(UInt<1>(0h1), _requestCIO_T_39) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 6, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 7) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<7>(0h7f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 6, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 7) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<7>(0h7f)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_4.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_4.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_4.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_4.valid, UInt<1>(0h0) connect _requestBOI_WIRE_4.ready, UInt<1>(0h0) wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 6, 0) node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 7) node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0)) node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<7>(0h7f)) node requestBOI_2_0 = and(_requestBOI_T_13, _requestBOI_T_14) wire _requestBOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_6.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_6.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_6.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_6.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_6.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_6.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_6.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_6.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_6.valid, UInt<1>(0h0) connect _requestBOI_WIRE_6.ready, UInt<1>(0h0) wire _requestBOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_7.bits, _requestBOI_WIRE_6.bits connect _requestBOI_WIRE_7.valid, _requestBOI_WIRE_6.valid connect _requestBOI_WIRE_7.ready, _requestBOI_WIRE_6.ready node _requestBOI_uncommonBits_T_3 = or(_requestBOI_WIRE_7.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 6, 0) node _requestBOI_T_15 = shr(_requestBOI_WIRE_7.bits.source, 7) node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<1>(0h0)) node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<7>(0h7f)) node requestBOI_3_0 = and(_requestBOI_T_18, _requestBOI_T_19) wire _requestBOI_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_8.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_8.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_8.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_8.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_8.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_8.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_8.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_8.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_8.valid, UInt<1>(0h0) connect _requestBOI_WIRE_8.ready, UInt<1>(0h0) wire _requestBOI_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_9.bits, _requestBOI_WIRE_8.bits connect _requestBOI_WIRE_9.valid, _requestBOI_WIRE_8.valid connect _requestBOI_WIRE_9.ready, _requestBOI_WIRE_8.ready node _requestBOI_uncommonBits_T_4 = or(_requestBOI_WIRE_9.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 6, 0) node _requestBOI_T_20 = shr(_requestBOI_WIRE_9.bits.source, 7) node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<1>(0h0)) node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4) node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22) node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<7>(0h7f)) node requestBOI_4_0 = and(_requestBOI_T_23, _requestBOI_T_24) wire _requestBOI_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_10.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_10.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_10.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_10.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_10.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_10.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_10.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_10.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_10.valid, UInt<1>(0h0) connect _requestBOI_WIRE_10.ready, UInt<1>(0h0) wire _requestBOI_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_11.bits, _requestBOI_WIRE_10.bits connect _requestBOI_WIRE_11.valid, _requestBOI_WIRE_10.valid connect _requestBOI_WIRE_11.ready, _requestBOI_WIRE_10.ready node _requestBOI_uncommonBits_T_5 = or(_requestBOI_WIRE_11.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 6, 0) node _requestBOI_T_25 = shr(_requestBOI_WIRE_11.bits.source, 7) node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<1>(0h0)) node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5) node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27) node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<7>(0h7f)) node requestBOI_5_0 = and(_requestBOI_T_28, _requestBOI_T_29) wire _requestBOI_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_12.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_12.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_12.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_12.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_12.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_12.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_12.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_12.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_12.valid, UInt<1>(0h0) connect _requestBOI_WIRE_12.ready, UInt<1>(0h0) wire _requestBOI_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_13.bits, _requestBOI_WIRE_12.bits connect _requestBOI_WIRE_13.valid, _requestBOI_WIRE_12.valid connect _requestBOI_WIRE_13.ready, _requestBOI_WIRE_12.ready node _requestBOI_uncommonBits_T_6 = or(_requestBOI_WIRE_13.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_6 = bits(_requestBOI_uncommonBits_T_6, 6, 0) node _requestBOI_T_30 = shr(_requestBOI_WIRE_13.bits.source, 7) node _requestBOI_T_31 = eq(_requestBOI_T_30, UInt<1>(0h0)) node _requestBOI_T_32 = leq(UInt<1>(0h0), requestBOI_uncommonBits_6) node _requestBOI_T_33 = and(_requestBOI_T_31, _requestBOI_T_32) node _requestBOI_T_34 = leq(requestBOI_uncommonBits_6, UInt<7>(0h7f)) node requestBOI_6_0 = and(_requestBOI_T_33, _requestBOI_T_34) wire _requestBOI_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_14.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_14.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_14.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_14.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_14.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_14.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_14.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_14.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_14.valid, UInt<1>(0h0) connect _requestBOI_WIRE_14.ready, UInt<1>(0h0) wire _requestBOI_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_15.bits, _requestBOI_WIRE_14.bits connect _requestBOI_WIRE_15.valid, _requestBOI_WIRE_14.valid connect _requestBOI_WIRE_15.ready, _requestBOI_WIRE_14.ready node _requestBOI_uncommonBits_T_7 = or(_requestBOI_WIRE_15.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_7 = bits(_requestBOI_uncommonBits_T_7, 6, 0) node _requestBOI_T_35 = shr(_requestBOI_WIRE_15.bits.source, 7) node _requestBOI_T_36 = eq(_requestBOI_T_35, UInt<1>(0h0)) node _requestBOI_T_37 = leq(UInt<1>(0h0), requestBOI_uncommonBits_7) node _requestBOI_T_38 = and(_requestBOI_T_36, _requestBOI_T_37) node _requestBOI_T_39 = leq(requestBOI_uncommonBits_7, UInt<7>(0h7f)) node requestBOI_7_0 = and(_requestBOI_T_38, _requestBOI_T_39) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 6, 0) node _requestDOI_T = shr(out[0].d.bits.source, 7) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<7>(0h7f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 6, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 7) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<7>(0h7f)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) node _requestDOI_uncommonBits_T_2 = or(out[2].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 6, 0) node _requestDOI_T_10 = shr(out[2].d.bits.source, 7) node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0)) node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<7>(0h7f)) node requestDOI_2_0 = and(_requestDOI_T_13, _requestDOI_T_14) node _requestDOI_uncommonBits_T_3 = or(out[3].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 6, 0) node _requestDOI_T_15 = shr(out[3].d.bits.source, 7) node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<1>(0h0)) node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<7>(0h7f)) node requestDOI_3_0 = and(_requestDOI_T_18, _requestDOI_T_19) node _requestDOI_uncommonBits_T_4 = or(out[4].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 6, 0) node _requestDOI_T_20 = shr(out[4].d.bits.source, 7) node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<1>(0h0)) node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4) node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22) node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<7>(0h7f)) node requestDOI_4_0 = and(_requestDOI_T_23, _requestDOI_T_24) node _requestDOI_uncommonBits_T_5 = or(out[5].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 6, 0) node _requestDOI_T_25 = shr(out[5].d.bits.source, 7) node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<1>(0h0)) node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5) node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27) node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<7>(0h7f)) node requestDOI_5_0 = and(_requestDOI_T_28, _requestDOI_T_29) node _requestDOI_uncommonBits_T_6 = or(out[6].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_6 = bits(_requestDOI_uncommonBits_T_6, 6, 0) node _requestDOI_T_30 = shr(out[6].d.bits.source, 7) node _requestDOI_T_31 = eq(_requestDOI_T_30, UInt<1>(0h0)) node _requestDOI_T_32 = leq(UInt<1>(0h0), requestDOI_uncommonBits_6) node _requestDOI_T_33 = and(_requestDOI_T_31, _requestDOI_T_32) node _requestDOI_T_34 = leq(requestDOI_uncommonBits_6, UInt<7>(0h7f)) node requestDOI_6_0 = and(_requestDOI_T_33, _requestDOI_T_34) node _requestDOI_uncommonBits_T_7 = or(out[7].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_7 = bits(_requestDOI_uncommonBits_T_7, 6, 0) node _requestDOI_T_35 = shr(out[7].d.bits.source, 7) node _requestDOI_T_36 = eq(_requestDOI_T_35, UInt<1>(0h0)) node _requestDOI_T_37 = leq(UInt<1>(0h0), requestDOI_uncommonBits_7) node _requestDOI_T_38 = and(_requestDOI_T_36, _requestDOI_T_37) node _requestDOI_T_39 = leq(requestDOI_uncommonBits_7, UInt<7>(0h7f)) node requestDOI_7_0 = and(_requestDOI_T_38, _requestDOI_T_39) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_4.valid, UInt<1>(0h0) connect _requestEIO_WIRE_4.ready, UInt<1>(0h0) wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready wire _requestEIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_6.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_6.valid, UInt<1>(0h0) connect _requestEIO_WIRE_6.ready, UInt<1>(0h0) wire _requestEIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_7.bits, _requestEIO_WIRE_6.bits connect _requestEIO_WIRE_7.valid, _requestEIO_WIRE_6.valid connect _requestEIO_WIRE_7.ready, _requestEIO_WIRE_6.ready wire _requestEIO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_8.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_8.valid, UInt<1>(0h0) connect _requestEIO_WIRE_8.ready, UInt<1>(0h0) wire _requestEIO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_9.bits, _requestEIO_WIRE_8.bits connect _requestEIO_WIRE_9.valid, _requestEIO_WIRE_8.valid connect _requestEIO_WIRE_9.ready, _requestEIO_WIRE_8.ready wire _requestEIO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_10.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_10.valid, UInt<1>(0h0) connect _requestEIO_WIRE_10.ready, UInt<1>(0h0) wire _requestEIO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_11.bits, _requestEIO_WIRE_10.bits connect _requestEIO_WIRE_11.valid, _requestEIO_WIRE_10.valid connect _requestEIO_WIRE_11.ready, _requestEIO_WIRE_10.ready wire _requestEIO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_12.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_12.valid, UInt<1>(0h0) connect _requestEIO_WIRE_12.ready, UInt<1>(0h0) wire _requestEIO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_13.bits, _requestEIO_WIRE_12.bits connect _requestEIO_WIRE_13.valid, _requestEIO_WIRE_12.valid connect _requestEIO_WIRE_13.ready, _requestEIO_WIRE_12.ready wire _requestEIO_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_14.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_14.valid, UInt<1>(0h0) connect _requestEIO_WIRE_14.ready, UInt<1>(0h0) wire _requestEIO_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_15.bits, _requestEIO_WIRE_14.bits connect _requestEIO_WIRE_15.valid, _requestEIO_WIRE_14.valid connect _requestEIO_WIRE_15.ready, _requestEIO_WIRE_14.ready node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsBO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_4.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_4.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_4.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_4.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_4.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_4.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_4.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_4.valid, UInt<1>(0h0) connect _beatsBO_WIRE_4.ready, UInt<1>(0h0) wire _beatsBO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_5.bits, _beatsBO_WIRE_4.bits connect _beatsBO_WIRE_5.valid, _beatsBO_WIRE_4.valid connect _beatsBO_WIRE_5.ready, _beatsBO_WIRE_4.ready node _beatsBO_decode_T_6 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_5.bits.size) node _beatsBO_decode_T_7 = bits(_beatsBO_decode_T_6, 5, 0) node _beatsBO_decode_T_8 = not(_beatsBO_decode_T_7) node beatsBO_decode_2 = shr(_beatsBO_decode_T_8, 3) node _beatsBO_opdata_T_2 = bits(_beatsBO_WIRE_5.bits.opcode, 2, 2) node beatsBO_opdata_2 = eq(_beatsBO_opdata_T_2, UInt<1>(0h0)) node beatsBO_2 = mux(UInt<1>(0h0), beatsBO_decode_2, UInt<1>(0h0)) wire _beatsBO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_6.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_6.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_6.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_6.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_6.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_6.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_6.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_6.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_6.valid, UInt<1>(0h0) connect _beatsBO_WIRE_6.ready, UInt<1>(0h0) wire _beatsBO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_7.bits, _beatsBO_WIRE_6.bits connect _beatsBO_WIRE_7.valid, _beatsBO_WIRE_6.valid connect _beatsBO_WIRE_7.ready, _beatsBO_WIRE_6.ready node _beatsBO_decode_T_9 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_7.bits.size) node _beatsBO_decode_T_10 = bits(_beatsBO_decode_T_9, 5, 0) node _beatsBO_decode_T_11 = not(_beatsBO_decode_T_10) node beatsBO_decode_3 = shr(_beatsBO_decode_T_11, 3) node _beatsBO_opdata_T_3 = bits(_beatsBO_WIRE_7.bits.opcode, 2, 2) node beatsBO_opdata_3 = eq(_beatsBO_opdata_T_3, UInt<1>(0h0)) node beatsBO_3 = mux(UInt<1>(0h0), beatsBO_decode_3, UInt<1>(0h0)) wire _beatsBO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_8.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_8.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_8.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_8.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_8.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_8.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_8.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_8.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_8.valid, UInt<1>(0h0) connect _beatsBO_WIRE_8.ready, UInt<1>(0h0) wire _beatsBO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_9.bits, _beatsBO_WIRE_8.bits connect _beatsBO_WIRE_9.valid, _beatsBO_WIRE_8.valid connect _beatsBO_WIRE_9.ready, _beatsBO_WIRE_8.ready node _beatsBO_decode_T_12 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_9.bits.size) node _beatsBO_decode_T_13 = bits(_beatsBO_decode_T_12, 5, 0) node _beatsBO_decode_T_14 = not(_beatsBO_decode_T_13) node beatsBO_decode_4 = shr(_beatsBO_decode_T_14, 3) node _beatsBO_opdata_T_4 = bits(_beatsBO_WIRE_9.bits.opcode, 2, 2) node beatsBO_opdata_4 = eq(_beatsBO_opdata_T_4, UInt<1>(0h0)) node beatsBO_4 = mux(UInt<1>(0h0), beatsBO_decode_4, UInt<1>(0h0)) wire _beatsBO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_10.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_10.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_10.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_10.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_10.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_10.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_10.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_10.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_10.valid, UInt<1>(0h0) connect _beatsBO_WIRE_10.ready, UInt<1>(0h0) wire _beatsBO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_11.bits, _beatsBO_WIRE_10.bits connect _beatsBO_WIRE_11.valid, _beatsBO_WIRE_10.valid connect _beatsBO_WIRE_11.ready, _beatsBO_WIRE_10.ready node _beatsBO_decode_T_15 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_11.bits.size) node _beatsBO_decode_T_16 = bits(_beatsBO_decode_T_15, 5, 0) node _beatsBO_decode_T_17 = not(_beatsBO_decode_T_16) node beatsBO_decode_5 = shr(_beatsBO_decode_T_17, 3) node _beatsBO_opdata_T_5 = bits(_beatsBO_WIRE_11.bits.opcode, 2, 2) node beatsBO_opdata_5 = eq(_beatsBO_opdata_T_5, UInt<1>(0h0)) node beatsBO_5 = mux(UInt<1>(0h0), beatsBO_decode_5, UInt<1>(0h0)) wire _beatsBO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_12.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_12.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_12.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_12.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_12.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_12.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_12.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_12.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_12.valid, UInt<1>(0h0) connect _beatsBO_WIRE_12.ready, UInt<1>(0h0) wire _beatsBO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_13.bits, _beatsBO_WIRE_12.bits connect _beatsBO_WIRE_13.valid, _beatsBO_WIRE_12.valid connect _beatsBO_WIRE_13.ready, _beatsBO_WIRE_12.ready node _beatsBO_decode_T_18 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_13.bits.size) node _beatsBO_decode_T_19 = bits(_beatsBO_decode_T_18, 5, 0) node _beatsBO_decode_T_20 = not(_beatsBO_decode_T_19) node beatsBO_decode_6 = shr(_beatsBO_decode_T_20, 3) node _beatsBO_opdata_T_6 = bits(_beatsBO_WIRE_13.bits.opcode, 2, 2) node beatsBO_opdata_6 = eq(_beatsBO_opdata_T_6, UInt<1>(0h0)) node beatsBO_6 = mux(UInt<1>(0h0), beatsBO_decode_6, UInt<1>(0h0)) wire _beatsBO_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_14.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_14.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_14.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_14.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_14.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_14.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_14.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_14.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_14.valid, UInt<1>(0h0) connect _beatsBO_WIRE_14.ready, UInt<1>(0h0) wire _beatsBO_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_15.bits, _beatsBO_WIRE_14.bits connect _beatsBO_WIRE_15.valid, _beatsBO_WIRE_14.valid connect _beatsBO_WIRE_15.ready, _beatsBO_WIRE_14.ready node _beatsBO_decode_T_21 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_15.bits.size) node _beatsBO_decode_T_22 = bits(_beatsBO_decode_T_21, 5, 0) node _beatsBO_decode_T_23 = not(_beatsBO_decode_T_22) node beatsBO_decode_7 = shr(_beatsBO_decode_T_23, 3) node _beatsBO_opdata_T_7 = bits(_beatsBO_WIRE_15.bits.opcode, 2, 2) node beatsBO_opdata_7 = eq(_beatsBO_opdata_T_7, UInt<1>(0h0)) node beatsBO_7 = mux(UInt<1>(0h0), beatsBO_decode_7, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<7>(0h0) connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T_6 = dshl(UInt<6>(0h3f), out[2].d.bits.size) node _beatsDO_decode_T_7 = bits(_beatsDO_decode_T_6, 5, 0) node _beatsDO_decode_T_8 = not(_beatsDO_decode_T_7) node beatsDO_decode_2 = shr(_beatsDO_decode_T_8, 3) node beatsDO_opdata_2 = bits(out[2].d.bits.opcode, 0, 0) node beatsDO_2 = mux(beatsDO_opdata_2, beatsDO_decode_2, UInt<1>(0h0)) node _beatsDO_decode_T_9 = dshl(UInt<6>(0h3f), out[3].d.bits.size) node _beatsDO_decode_T_10 = bits(_beatsDO_decode_T_9, 5, 0) node _beatsDO_decode_T_11 = not(_beatsDO_decode_T_10) node beatsDO_decode_3 = shr(_beatsDO_decode_T_11, 3) node beatsDO_opdata_3 = bits(out[3].d.bits.opcode, 0, 0) node beatsDO_3 = mux(beatsDO_opdata_3, beatsDO_decode_3, UInt<1>(0h0)) node _beatsDO_decode_T_12 = dshl(UInt<6>(0h3f), out[4].d.bits.size) node _beatsDO_decode_T_13 = bits(_beatsDO_decode_T_12, 5, 0) node _beatsDO_decode_T_14 = not(_beatsDO_decode_T_13) node beatsDO_decode_4 = shr(_beatsDO_decode_T_14, 3) node beatsDO_opdata_4 = bits(out[4].d.bits.opcode, 0, 0) node beatsDO_4 = mux(beatsDO_opdata_4, beatsDO_decode_4, UInt<1>(0h0)) node _beatsDO_decode_T_15 = dshl(UInt<6>(0h3f), out[5].d.bits.size) node _beatsDO_decode_T_16 = bits(_beatsDO_decode_T_15, 5, 0) node _beatsDO_decode_T_17 = not(_beatsDO_decode_T_16) node beatsDO_decode_5 = shr(_beatsDO_decode_T_17, 3) node beatsDO_opdata_5 = bits(out[5].d.bits.opcode, 0, 0) node beatsDO_5 = mux(beatsDO_opdata_5, beatsDO_decode_5, UInt<1>(0h0)) node _beatsDO_decode_T_18 = dshl(UInt<6>(0h3f), out[6].d.bits.size) node _beatsDO_decode_T_19 = bits(_beatsDO_decode_T_18, 5, 0) node _beatsDO_decode_T_20 = not(_beatsDO_decode_T_19) node beatsDO_decode_6 = shr(_beatsDO_decode_T_20, 3) node beatsDO_opdata_6 = bits(out[6].d.bits.opcode, 0, 0) node beatsDO_6 = mux(UInt<1>(0h1), beatsDO_decode_6, UInt<1>(0h0)) node _beatsDO_decode_T_21 = dshl(UInt<6>(0h3f), out[7].d.bits.size) node _beatsDO_decode_T_22 = bits(_beatsDO_decode_T_21, 5, 0) node _beatsDO_decode_T_23 = not(_beatsDO_decode_T_22) node beatsDO_decode_7 = shr(_beatsDO_decode_T_23, 3) node beatsDO_opdata_7 = bits(out[7].d.bits.opcode, 0, 0) node beatsDO_7 = mux(beatsDO_opdata_7, beatsDO_decode_7, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[8] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 connect portsAOI_filtered[2].bits, in[0].a.bits node _portsAOI_filtered_2_valid_T = or(requestAIO_0_2, UInt<1>(0h0)) node _portsAOI_filtered_2_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_2_valid_T) connect portsAOI_filtered[2].valid, _portsAOI_filtered_2_valid_T_1 connect portsAOI_filtered[3].bits, in[0].a.bits node _portsAOI_filtered_3_valid_T = or(requestAIO_0_3, UInt<1>(0h0)) node _portsAOI_filtered_3_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_3_valid_T) connect portsAOI_filtered[3].valid, _portsAOI_filtered_3_valid_T_1 connect portsAOI_filtered[4].bits, in[0].a.bits node _portsAOI_filtered_4_valid_T = or(requestAIO_0_4, UInt<1>(0h0)) node _portsAOI_filtered_4_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_4_valid_T) connect portsAOI_filtered[4].valid, _portsAOI_filtered_4_valid_T_1 connect portsAOI_filtered[5].bits, in[0].a.bits node _portsAOI_filtered_5_valid_T = or(requestAIO_0_5, UInt<1>(0h0)) node _portsAOI_filtered_5_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_5_valid_T) connect portsAOI_filtered[5].valid, _portsAOI_filtered_5_valid_T_1 connect portsAOI_filtered[6].bits, in[0].a.bits node _portsAOI_filtered_6_valid_T = or(requestAIO_0_6, UInt<1>(0h0)) node _portsAOI_filtered_6_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_6_valid_T) connect portsAOI_filtered[6].valid, _portsAOI_filtered_6_valid_T_1 connect portsAOI_filtered[7].bits, in[0].a.bits node _portsAOI_filtered_7_valid_T = or(requestAIO_0_7, UInt<1>(0h0)) node _portsAOI_filtered_7_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_7_valid_T) connect portsAOI_filtered[7].valid, _portsAOI_filtered_7_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = mux(requestAIO_0_2, portsAOI_filtered[2].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_3 = mux(requestAIO_0_3, portsAOI_filtered[3].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_4 = mux(requestAIO_0_4, portsAOI_filtered[4].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_5 = mux(requestAIO_0_5, portsAOI_filtered[5].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_6 = mux(requestAIO_0_6, portsAOI_filtered[6].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_7 = mux(requestAIO_0_7, portsAOI_filtered[7].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_8 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) node _portsAOI_in_0_a_ready_T_9 = or(_portsAOI_in_0_a_ready_T_8, _portsAOI_in_0_a_ready_T_2) node _portsAOI_in_0_a_ready_T_10 = or(_portsAOI_in_0_a_ready_T_9, _portsAOI_in_0_a_ready_T_3) node _portsAOI_in_0_a_ready_T_11 = or(_portsAOI_in_0_a_ready_T_10, _portsAOI_in_0_a_ready_T_4) node _portsAOI_in_0_a_ready_T_12 = or(_portsAOI_in_0_a_ready_T_11, _portsAOI_in_0_a_ready_T_5) node _portsAOI_in_0_a_ready_T_13 = or(_portsAOI_in_0_a_ready_T_12, _portsAOI_in_0_a_ready_T_6) node _portsAOI_in_0_a_ready_T_14 = or(_portsAOI_in_0_a_ready_T_13, _portsAOI_in_0_a_ready_T_7) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_14 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_4.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_4.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_4.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_4.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_4.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_4.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_4.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_4.valid, UInt<1>(0h0) connect _portsBIO_WIRE_4.ready, UInt<1>(0h0) wire _portsBIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_5.bits, _portsBIO_WIRE_4.bits connect _portsBIO_WIRE_5.valid, _portsBIO_WIRE_4.valid connect _portsBIO_WIRE_5.ready, _portsBIO_WIRE_4.ready wire portsBIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_2[0].bits, _portsBIO_WIRE_5.bits node _portsBIO_filtered_0_valid_T_4 = or(requestBOI_2_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_5 = and(_portsBIO_WIRE_5.valid, _portsBIO_filtered_0_valid_T_4) connect portsBIO_filtered_2[0].valid, _portsBIO_filtered_0_valid_T_5 connect _portsBIO_WIRE_5.ready, portsBIO_filtered_2[0].ready wire _portsBIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_6.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_6.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_6.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_6.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_6.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_6.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_6.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_6.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_6.valid, UInt<1>(0h0) connect _portsBIO_WIRE_6.ready, UInt<1>(0h0) wire _portsBIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_7.bits, _portsBIO_WIRE_6.bits connect _portsBIO_WIRE_7.valid, _portsBIO_WIRE_6.valid connect _portsBIO_WIRE_7.ready, _portsBIO_WIRE_6.ready wire portsBIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_3[0].bits, _portsBIO_WIRE_7.bits node _portsBIO_filtered_0_valid_T_6 = or(requestBOI_3_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_7 = and(_portsBIO_WIRE_7.valid, _portsBIO_filtered_0_valid_T_6) connect portsBIO_filtered_3[0].valid, _portsBIO_filtered_0_valid_T_7 connect _portsBIO_WIRE_7.ready, portsBIO_filtered_3[0].ready wire _portsBIO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_8.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_8.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_8.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_8.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_8.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_8.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_8.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_8.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_8.valid, UInt<1>(0h0) connect _portsBIO_WIRE_8.ready, UInt<1>(0h0) wire _portsBIO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_9.bits, _portsBIO_WIRE_8.bits connect _portsBIO_WIRE_9.valid, _portsBIO_WIRE_8.valid connect _portsBIO_WIRE_9.ready, _portsBIO_WIRE_8.ready wire portsBIO_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_4[0].bits, _portsBIO_WIRE_9.bits node _portsBIO_filtered_0_valid_T_8 = or(requestBOI_4_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_9 = and(_portsBIO_WIRE_9.valid, _portsBIO_filtered_0_valid_T_8) connect portsBIO_filtered_4[0].valid, _portsBIO_filtered_0_valid_T_9 connect _portsBIO_WIRE_9.ready, portsBIO_filtered_4[0].ready wire _portsBIO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_10.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_10.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_10.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_10.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_10.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_10.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_10.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_10.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_10.valid, UInt<1>(0h0) connect _portsBIO_WIRE_10.ready, UInt<1>(0h0) wire _portsBIO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_11.bits, _portsBIO_WIRE_10.bits connect _portsBIO_WIRE_11.valid, _portsBIO_WIRE_10.valid connect _portsBIO_WIRE_11.ready, _portsBIO_WIRE_10.ready wire portsBIO_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_5[0].bits, _portsBIO_WIRE_11.bits node _portsBIO_filtered_0_valid_T_10 = or(requestBOI_5_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_11 = and(_portsBIO_WIRE_11.valid, _portsBIO_filtered_0_valid_T_10) connect portsBIO_filtered_5[0].valid, _portsBIO_filtered_0_valid_T_11 connect _portsBIO_WIRE_11.ready, portsBIO_filtered_5[0].ready wire _portsBIO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_12.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_12.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_12.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_12.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_12.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_12.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_12.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_12.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_12.valid, UInt<1>(0h0) connect _portsBIO_WIRE_12.ready, UInt<1>(0h0) wire _portsBIO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_13.bits, _portsBIO_WIRE_12.bits connect _portsBIO_WIRE_13.valid, _portsBIO_WIRE_12.valid connect _portsBIO_WIRE_13.ready, _portsBIO_WIRE_12.ready wire portsBIO_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_6[0].bits, _portsBIO_WIRE_13.bits node _portsBIO_filtered_0_valid_T_12 = or(requestBOI_6_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_13 = and(_portsBIO_WIRE_13.valid, _portsBIO_filtered_0_valid_T_12) connect portsBIO_filtered_6[0].valid, _portsBIO_filtered_0_valid_T_13 connect _portsBIO_WIRE_13.ready, portsBIO_filtered_6[0].ready wire _portsBIO_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_14.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_14.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_14.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_14.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_14.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_14.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_14.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_14.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_14.valid, UInt<1>(0h0) connect _portsBIO_WIRE_14.ready, UInt<1>(0h0) wire _portsBIO_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_15.bits, _portsBIO_WIRE_14.bits connect _portsBIO_WIRE_15.valid, _portsBIO_WIRE_14.valid connect _portsBIO_WIRE_15.ready, _portsBIO_WIRE_14.ready wire portsBIO_filtered_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_7[0].bits, _portsBIO_WIRE_15.bits node _portsBIO_filtered_0_valid_T_14 = or(requestBOI_7_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_15 = and(_portsBIO_WIRE_15.valid, _portsBIO_filtered_0_valid_T_14) connect portsBIO_filtered_7[0].valid, _portsBIO_filtered_0_valid_T_15 connect _portsBIO_WIRE_15.ready, portsBIO_filtered_7[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<7>(0h0) connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[8] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 connect portsCOI_filtered[2].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_2_valid_T = or(requestCIO_0_2, UInt<1>(0h0)) node _portsCOI_filtered_2_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_2_valid_T) connect portsCOI_filtered[2].valid, _portsCOI_filtered_2_valid_T_1 connect portsCOI_filtered[3].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_3_valid_T = or(requestCIO_0_3, UInt<1>(0h0)) node _portsCOI_filtered_3_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_3_valid_T) connect portsCOI_filtered[3].valid, _portsCOI_filtered_3_valid_T_1 connect portsCOI_filtered[4].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_4_valid_T = or(requestCIO_0_4, UInt<1>(0h0)) node _portsCOI_filtered_4_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_4_valid_T) connect portsCOI_filtered[4].valid, _portsCOI_filtered_4_valid_T_1 connect portsCOI_filtered[5].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_5_valid_T = or(requestCIO_0_5, UInt<1>(0h0)) node _portsCOI_filtered_5_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_5_valid_T) connect portsCOI_filtered[5].valid, _portsCOI_filtered_5_valid_T_1 connect portsCOI_filtered[6].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_6_valid_T = or(requestCIO_0_6, UInt<1>(0h0)) node _portsCOI_filtered_6_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_6_valid_T) connect portsCOI_filtered[6].valid, _portsCOI_filtered_6_valid_T_1 connect portsCOI_filtered[7].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_7_valid_T = or(requestCIO_0_7, UInt<1>(0h0)) node _portsCOI_filtered_7_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_7_valid_T) connect portsCOI_filtered[7].valid, _portsCOI_filtered_7_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = mux(requestCIO_0_2, portsCOI_filtered[2].ready, UInt<1>(0h0)) node _portsCOI_T_3 = mux(requestCIO_0_3, portsCOI_filtered[3].ready, UInt<1>(0h0)) node _portsCOI_T_4 = mux(requestCIO_0_4, portsCOI_filtered[4].ready, UInt<1>(0h0)) node _portsCOI_T_5 = mux(requestCIO_0_5, portsCOI_filtered[5].ready, UInt<1>(0h0)) node _portsCOI_T_6 = mux(requestCIO_0_6, portsCOI_filtered[6].ready, UInt<1>(0h0)) node _portsCOI_T_7 = mux(requestCIO_0_7, portsCOI_filtered[7].ready, UInt<1>(0h0)) node _portsCOI_T_8 = or(_portsCOI_T, _portsCOI_T_1) node _portsCOI_T_9 = or(_portsCOI_T_8, _portsCOI_T_2) node _portsCOI_T_10 = or(_portsCOI_T_9, _portsCOI_T_3) node _portsCOI_T_11 = or(_portsCOI_T_10, _portsCOI_T_4) node _portsCOI_T_12 = or(_portsCOI_T_11, _portsCOI_T_5) node _portsCOI_T_13 = or(_portsCOI_T_12, _portsCOI_T_6) node _portsCOI_T_14 = or(_portsCOI_T_13, _portsCOI_T_7) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_14 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire portsDIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_2[0].bits.corrupt, out[2].d.bits.corrupt connect portsDIO_filtered_2[0].bits.data, out[2].d.bits.data connect portsDIO_filtered_2[0].bits.denied, out[2].d.bits.denied connect portsDIO_filtered_2[0].bits.sink, out[2].d.bits.sink connect portsDIO_filtered_2[0].bits.source, out[2].d.bits.source connect portsDIO_filtered_2[0].bits.size, out[2].d.bits.size connect portsDIO_filtered_2[0].bits.param, out[2].d.bits.param connect portsDIO_filtered_2[0].bits.opcode, out[2].d.bits.opcode node _portsDIO_filtered_0_valid_T_4 = or(requestDOI_2_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_5 = and(out[2].d.valid, _portsDIO_filtered_0_valid_T_4) connect portsDIO_filtered_2[0].valid, _portsDIO_filtered_0_valid_T_5 connect out[2].d.ready, portsDIO_filtered_2[0].ready wire portsDIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_3[0].bits.corrupt, out[3].d.bits.corrupt connect portsDIO_filtered_3[0].bits.data, out[3].d.bits.data connect portsDIO_filtered_3[0].bits.denied, out[3].d.bits.denied connect portsDIO_filtered_3[0].bits.sink, out[3].d.bits.sink connect portsDIO_filtered_3[0].bits.source, out[3].d.bits.source connect portsDIO_filtered_3[0].bits.size, out[3].d.bits.size connect portsDIO_filtered_3[0].bits.param, out[3].d.bits.param connect portsDIO_filtered_3[0].bits.opcode, out[3].d.bits.opcode node _portsDIO_filtered_0_valid_T_6 = or(requestDOI_3_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_7 = and(out[3].d.valid, _portsDIO_filtered_0_valid_T_6) connect portsDIO_filtered_3[0].valid, _portsDIO_filtered_0_valid_T_7 connect out[3].d.ready, portsDIO_filtered_3[0].ready wire portsDIO_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_4[0].bits.corrupt, out[4].d.bits.corrupt connect portsDIO_filtered_4[0].bits.data, out[4].d.bits.data connect portsDIO_filtered_4[0].bits.denied, out[4].d.bits.denied connect portsDIO_filtered_4[0].bits.sink, out[4].d.bits.sink connect portsDIO_filtered_4[0].bits.source, out[4].d.bits.source connect portsDIO_filtered_4[0].bits.size, out[4].d.bits.size connect portsDIO_filtered_4[0].bits.param, out[4].d.bits.param connect portsDIO_filtered_4[0].bits.opcode, out[4].d.bits.opcode node _portsDIO_filtered_0_valid_T_8 = or(requestDOI_4_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_9 = and(out[4].d.valid, _portsDIO_filtered_0_valid_T_8) connect portsDIO_filtered_4[0].valid, _portsDIO_filtered_0_valid_T_9 connect out[4].d.ready, portsDIO_filtered_4[0].ready wire portsDIO_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_5[0].bits.corrupt, out[5].d.bits.corrupt connect portsDIO_filtered_5[0].bits.data, out[5].d.bits.data connect portsDIO_filtered_5[0].bits.denied, out[5].d.bits.denied connect portsDIO_filtered_5[0].bits.sink, out[5].d.bits.sink connect portsDIO_filtered_5[0].bits.source, out[5].d.bits.source connect portsDIO_filtered_5[0].bits.size, out[5].d.bits.size connect portsDIO_filtered_5[0].bits.param, out[5].d.bits.param connect portsDIO_filtered_5[0].bits.opcode, out[5].d.bits.opcode node _portsDIO_filtered_0_valid_T_10 = or(requestDOI_5_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_11 = and(out[5].d.valid, _portsDIO_filtered_0_valid_T_10) connect portsDIO_filtered_5[0].valid, _portsDIO_filtered_0_valid_T_11 connect out[5].d.ready, portsDIO_filtered_5[0].ready wire portsDIO_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_6[0].bits.corrupt, out[6].d.bits.corrupt connect portsDIO_filtered_6[0].bits.data, out[6].d.bits.data connect portsDIO_filtered_6[0].bits.denied, out[6].d.bits.denied connect portsDIO_filtered_6[0].bits.sink, out[6].d.bits.sink connect portsDIO_filtered_6[0].bits.source, out[6].d.bits.source connect portsDIO_filtered_6[0].bits.size, out[6].d.bits.size connect portsDIO_filtered_6[0].bits.param, out[6].d.bits.param connect portsDIO_filtered_6[0].bits.opcode, out[6].d.bits.opcode node _portsDIO_filtered_0_valid_T_12 = or(requestDOI_6_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_13 = and(out[6].d.valid, _portsDIO_filtered_0_valid_T_12) connect portsDIO_filtered_6[0].valid, _portsDIO_filtered_0_valid_T_13 connect out[6].d.ready, portsDIO_filtered_6[0].ready wire portsDIO_filtered_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_7[0].bits.corrupt, out[7].d.bits.corrupt connect portsDIO_filtered_7[0].bits.data, out[7].d.bits.data connect portsDIO_filtered_7[0].bits.denied, out[7].d.bits.denied connect portsDIO_filtered_7[0].bits.sink, out[7].d.bits.sink connect portsDIO_filtered_7[0].bits.source, out[7].d.bits.source connect portsDIO_filtered_7[0].bits.size, out[7].d.bits.size connect portsDIO_filtered_7[0].bits.param, out[7].d.bits.param connect portsDIO_filtered_7[0].bits.opcode, out[7].d.bits.opcode node _portsDIO_filtered_0_valid_T_14 = or(requestDOI_7_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_15 = and(out[7].d.valid, _portsDIO_filtered_0_valid_T_14) connect portsDIO_filtered_7[0].valid, _portsDIO_filtered_0_valid_T_15 connect out[7].d.ready, portsDIO_filtered_7[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[8] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 connect portsEOI_filtered[2].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_2_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_2_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_2_valid_T) connect portsEOI_filtered[2].valid, _portsEOI_filtered_2_valid_T_1 connect portsEOI_filtered[3].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_3_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_3_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_3_valid_T) connect portsEOI_filtered[3].valid, _portsEOI_filtered_3_valid_T_1 connect portsEOI_filtered[4].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_4_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_4_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_4_valid_T) connect portsEOI_filtered[4].valid, _portsEOI_filtered_4_valid_T_1 connect portsEOI_filtered[5].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_5_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_5_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_5_valid_T) connect portsEOI_filtered[5].valid, _portsEOI_filtered_5_valid_T_1 connect portsEOI_filtered[6].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_6_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_6_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_6_valid_T) connect portsEOI_filtered[6].valid, _portsEOI_filtered_6_valid_T_1 connect portsEOI_filtered[7].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_7_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_7_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_7_valid_T) connect portsEOI_filtered[7].valid, _portsEOI_filtered_7_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = mux(UInt<1>(0h0), portsEOI_filtered[2].ready, UInt<1>(0h0)) node _portsEOI_T_3 = mux(UInt<1>(0h0), portsEOI_filtered[3].ready, UInt<1>(0h0)) node _portsEOI_T_4 = mux(UInt<1>(0h0), portsEOI_filtered[4].ready, UInt<1>(0h0)) node _portsEOI_T_5 = mux(UInt<1>(0h0), portsEOI_filtered[5].ready, UInt<1>(0h0)) node _portsEOI_T_6 = mux(UInt<1>(0h0), portsEOI_filtered[6].ready, UInt<1>(0h0)) node _portsEOI_T_7 = mux(UInt<1>(0h0), portsEOI_filtered[7].ready, UInt<1>(0h0)) node _portsEOI_T_8 = or(_portsEOI_T, _portsEOI_T_1) node _portsEOI_T_9 = or(_portsEOI_T_8, _portsEOI_T_2) node _portsEOI_T_10 = or(_portsEOI_T_9, _portsEOI_T_3) node _portsEOI_T_11 = or(_portsEOI_T_10, _portsEOI_T_4) node _portsEOI_T_12 = or(_portsEOI_T_11, _portsEOI_T_5) node _portsEOI_T_13 = or(_portsEOI_T_12, _portsEOI_T_6) node _portsEOI_T_14 = or(_portsEOI_T_13, _portsEOI_T_7) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_14 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_216 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_216.bits.corrupt, UInt<1>(0h0) connect _WIRE_216.bits.data, UInt<64>(0h0) connect _WIRE_216.bits.address, UInt<32>(0h0) connect _WIRE_216.bits.source, UInt<7>(0h0) connect _WIRE_216.bits.size, UInt<4>(0h0) connect _WIRE_216.bits.param, UInt<3>(0h0) connect _WIRE_216.bits.opcode, UInt<3>(0h0) connect _WIRE_216.valid, UInt<1>(0h0) connect _WIRE_216.ready, UInt<1>(0h0) wire _WIRE_217 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_217.bits, _WIRE_216.bits connect _WIRE_217.valid, _WIRE_216.valid connect _WIRE_217.ready, _WIRE_216.ready invalidate _WIRE_217.bits.corrupt invalidate _WIRE_217.bits.data invalidate _WIRE_217.bits.address invalidate _WIRE_217.bits.source invalidate _WIRE_217.bits.size invalidate _WIRE_217.bits.param invalidate _WIRE_217.bits.opcode wire _WIRE_218 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_218.bits.sink, UInt<1>(0h0) connect _WIRE_218.valid, UInt<1>(0h0) connect _WIRE_218.ready, UInt<1>(0h0) wire _WIRE_219 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_219.bits, _WIRE_218.bits connect _WIRE_219.valid, _WIRE_218.valid connect _WIRE_219.ready, _WIRE_218.ready invalidate _WIRE_219.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_220 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_220.bits.corrupt, UInt<1>(0h0) connect _WIRE_220.bits.data, UInt<64>(0h0) connect _WIRE_220.bits.address, UInt<32>(0h0) connect _WIRE_220.bits.source, UInt<7>(0h0) connect _WIRE_220.bits.size, UInt<4>(0h0) connect _WIRE_220.bits.param, UInt<3>(0h0) connect _WIRE_220.bits.opcode, UInt<3>(0h0) connect _WIRE_220.valid, UInt<1>(0h0) connect _WIRE_220.ready, UInt<1>(0h0) wire _WIRE_221 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_221.bits, _WIRE_220.bits connect _WIRE_221.valid, _WIRE_220.valid connect _WIRE_221.ready, _WIRE_220.ready invalidate _WIRE_221.bits.corrupt invalidate _WIRE_221.bits.data invalidate _WIRE_221.bits.address invalidate _WIRE_221.bits.source invalidate _WIRE_221.bits.size invalidate _WIRE_221.bits.param invalidate _WIRE_221.bits.opcode wire _WIRE_222 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_222.bits.sink, UInt<1>(0h0) connect _WIRE_222.valid, UInt<1>(0h0) connect _WIRE_222.ready, UInt<1>(0h0) wire _WIRE_223 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_223.bits, _WIRE_222.bits connect _WIRE_223.valid, _WIRE_222.valid connect _WIRE_223.ready, _WIRE_222.ready invalidate _WIRE_223.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) connect out[2].a, portsAOI_filtered[2] wire _WIRE_224 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_224.bits.corrupt, UInt<1>(0h0) connect _WIRE_224.bits.data, UInt<64>(0h0) connect _WIRE_224.bits.address, UInt<32>(0h0) connect _WIRE_224.bits.source, UInt<7>(0h0) connect _WIRE_224.bits.size, UInt<4>(0h0) connect _WIRE_224.bits.param, UInt<3>(0h0) connect _WIRE_224.bits.opcode, UInt<3>(0h0) connect _WIRE_224.valid, UInt<1>(0h0) connect _WIRE_224.ready, UInt<1>(0h0) wire _WIRE_225 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_225.bits, _WIRE_224.bits connect _WIRE_225.valid, _WIRE_224.valid connect _WIRE_225.ready, _WIRE_224.ready invalidate _WIRE_225.bits.corrupt invalidate _WIRE_225.bits.data invalidate _WIRE_225.bits.address invalidate _WIRE_225.bits.source invalidate _WIRE_225.bits.size invalidate _WIRE_225.bits.param invalidate _WIRE_225.bits.opcode wire _WIRE_226 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_226.bits.sink, UInt<1>(0h0) connect _WIRE_226.valid, UInt<1>(0h0) connect _WIRE_226.ready, UInt<1>(0h0) wire _WIRE_227 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_227.bits, _WIRE_226.bits connect _WIRE_227.valid, _WIRE_226.valid connect _WIRE_227.ready, _WIRE_226.ready invalidate _WIRE_227.bits.sink connect portsCOI_filtered[2].ready, UInt<1>(0h0) connect portsEOI_filtered[2].ready, UInt<1>(0h0) connect out[3].a, portsAOI_filtered[3] wire _WIRE_228 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_228.bits.corrupt, UInt<1>(0h0) connect _WIRE_228.bits.data, UInt<64>(0h0) connect _WIRE_228.bits.address, UInt<32>(0h0) connect _WIRE_228.bits.source, UInt<7>(0h0) connect _WIRE_228.bits.size, UInt<4>(0h0) connect _WIRE_228.bits.param, UInt<3>(0h0) connect _WIRE_228.bits.opcode, UInt<3>(0h0) connect _WIRE_228.valid, UInt<1>(0h0) connect _WIRE_228.ready, UInt<1>(0h0) wire _WIRE_229 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_229.bits, _WIRE_228.bits connect _WIRE_229.valid, _WIRE_228.valid connect _WIRE_229.ready, _WIRE_228.ready invalidate _WIRE_229.bits.corrupt invalidate _WIRE_229.bits.data invalidate _WIRE_229.bits.address invalidate _WIRE_229.bits.source invalidate _WIRE_229.bits.size invalidate _WIRE_229.bits.param invalidate _WIRE_229.bits.opcode wire _WIRE_230 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_230.bits.sink, UInt<1>(0h0) connect _WIRE_230.valid, UInt<1>(0h0) connect _WIRE_230.ready, UInt<1>(0h0) wire _WIRE_231 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_231.bits, _WIRE_230.bits connect _WIRE_231.valid, _WIRE_230.valid connect _WIRE_231.ready, _WIRE_230.ready invalidate _WIRE_231.bits.sink connect portsCOI_filtered[3].ready, UInt<1>(0h0) connect portsEOI_filtered[3].ready, UInt<1>(0h0) connect out[4].a, portsAOI_filtered[4] wire _WIRE_232 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_232.bits.corrupt, UInt<1>(0h0) connect _WIRE_232.bits.data, UInt<64>(0h0) connect _WIRE_232.bits.address, UInt<32>(0h0) connect _WIRE_232.bits.source, UInt<7>(0h0) connect _WIRE_232.bits.size, UInt<4>(0h0) connect _WIRE_232.bits.param, UInt<3>(0h0) connect _WIRE_232.bits.opcode, UInt<3>(0h0) connect _WIRE_232.valid, UInt<1>(0h0) connect _WIRE_232.ready, UInt<1>(0h0) wire _WIRE_233 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_233.bits, _WIRE_232.bits connect _WIRE_233.valid, _WIRE_232.valid connect _WIRE_233.ready, _WIRE_232.ready invalidate _WIRE_233.bits.corrupt invalidate _WIRE_233.bits.data invalidate _WIRE_233.bits.address invalidate _WIRE_233.bits.source invalidate _WIRE_233.bits.size invalidate _WIRE_233.bits.param invalidate _WIRE_233.bits.opcode wire _WIRE_234 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_234.bits.sink, UInt<1>(0h0) connect _WIRE_234.valid, UInt<1>(0h0) connect _WIRE_234.ready, UInt<1>(0h0) wire _WIRE_235 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_235.bits, _WIRE_234.bits connect _WIRE_235.valid, _WIRE_234.valid connect _WIRE_235.ready, _WIRE_234.ready invalidate _WIRE_235.bits.sink connect portsCOI_filtered[4].ready, UInt<1>(0h0) connect portsEOI_filtered[4].ready, UInt<1>(0h0) connect out[5].a, portsAOI_filtered[5] wire _WIRE_236 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_236.bits.corrupt, UInt<1>(0h0) connect _WIRE_236.bits.data, UInt<64>(0h0) connect _WIRE_236.bits.address, UInt<32>(0h0) connect _WIRE_236.bits.source, UInt<7>(0h0) connect _WIRE_236.bits.size, UInt<4>(0h0) connect _WIRE_236.bits.param, UInt<3>(0h0) connect _WIRE_236.bits.opcode, UInt<3>(0h0) connect _WIRE_236.valid, UInt<1>(0h0) connect _WIRE_236.ready, UInt<1>(0h0) wire _WIRE_237 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_237.bits, _WIRE_236.bits connect _WIRE_237.valid, _WIRE_236.valid connect _WIRE_237.ready, _WIRE_236.ready invalidate _WIRE_237.bits.corrupt invalidate _WIRE_237.bits.data invalidate _WIRE_237.bits.address invalidate _WIRE_237.bits.source invalidate _WIRE_237.bits.size invalidate _WIRE_237.bits.param invalidate _WIRE_237.bits.opcode wire _WIRE_238 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_238.bits.sink, UInt<1>(0h0) connect _WIRE_238.valid, UInt<1>(0h0) connect _WIRE_238.ready, UInt<1>(0h0) wire _WIRE_239 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_239.bits, _WIRE_238.bits connect _WIRE_239.valid, _WIRE_238.valid connect _WIRE_239.ready, _WIRE_238.ready invalidate _WIRE_239.bits.sink connect portsCOI_filtered[5].ready, UInt<1>(0h0) connect portsEOI_filtered[5].ready, UInt<1>(0h0) connect out[6].a, portsAOI_filtered[6] wire _WIRE_240 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_240.bits.corrupt, UInt<1>(0h0) connect _WIRE_240.bits.data, UInt<64>(0h0) connect _WIRE_240.bits.address, UInt<32>(0h0) connect _WIRE_240.bits.source, UInt<7>(0h0) connect _WIRE_240.bits.size, UInt<4>(0h0) connect _WIRE_240.bits.param, UInt<3>(0h0) connect _WIRE_240.bits.opcode, UInt<3>(0h0) connect _WIRE_240.valid, UInt<1>(0h0) connect _WIRE_240.ready, UInt<1>(0h0) wire _WIRE_241 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_241.bits, _WIRE_240.bits connect _WIRE_241.valid, _WIRE_240.valid connect _WIRE_241.ready, _WIRE_240.ready invalidate _WIRE_241.bits.corrupt invalidate _WIRE_241.bits.data invalidate _WIRE_241.bits.address invalidate _WIRE_241.bits.source invalidate _WIRE_241.bits.size invalidate _WIRE_241.bits.param invalidate _WIRE_241.bits.opcode wire _WIRE_242 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_242.bits.sink, UInt<1>(0h0) connect _WIRE_242.valid, UInt<1>(0h0) connect _WIRE_242.ready, UInt<1>(0h0) wire _WIRE_243 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_243.bits, _WIRE_242.bits connect _WIRE_243.valid, _WIRE_242.valid connect _WIRE_243.ready, _WIRE_242.ready invalidate _WIRE_243.bits.sink connect portsCOI_filtered[6].ready, UInt<1>(0h0) connect portsEOI_filtered[6].ready, UInt<1>(0h0) connect out[7].a, portsAOI_filtered[7] wire _WIRE_244 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_244.bits.corrupt, UInt<1>(0h0) connect _WIRE_244.bits.data, UInt<64>(0h0) connect _WIRE_244.bits.address, UInt<32>(0h0) connect _WIRE_244.bits.source, UInt<7>(0h0) connect _WIRE_244.bits.size, UInt<4>(0h0) connect _WIRE_244.bits.param, UInt<3>(0h0) connect _WIRE_244.bits.opcode, UInt<3>(0h0) connect _WIRE_244.valid, UInt<1>(0h0) connect _WIRE_244.ready, UInt<1>(0h0) wire _WIRE_245 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_245.bits, _WIRE_244.bits connect _WIRE_245.valid, _WIRE_244.valid connect _WIRE_245.ready, _WIRE_244.ready invalidate _WIRE_245.bits.corrupt invalidate _WIRE_245.bits.data invalidate _WIRE_245.bits.address invalidate _WIRE_245.bits.source invalidate _WIRE_245.bits.size invalidate _WIRE_245.bits.param invalidate _WIRE_245.bits.opcode wire _WIRE_246 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_246.bits.sink, UInt<1>(0h0) connect _WIRE_246.valid, UInt<1>(0h0) connect _WIRE_246.ready, UInt<1>(0h0) wire _WIRE_247 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_247.bits, _WIRE_246.bits connect _WIRE_247.valid, _WIRE_246.valid connect _WIRE_247.ready, _WIRE_246.ready invalidate _WIRE_247.bits.sink connect portsCOI_filtered[7].ready, UInt<1>(0h0) connect portsEOI_filtered[7].ready, UInt<1>(0h0) wire _WIRE_248 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_248.bits.corrupt, UInt<1>(0h0) connect _WIRE_248.bits.data, UInt<64>(0h0) connect _WIRE_248.bits.mask, UInt<8>(0h0) connect _WIRE_248.bits.address, UInt<32>(0h0) connect _WIRE_248.bits.source, UInt<7>(0h0) connect _WIRE_248.bits.size, UInt<4>(0h0) connect _WIRE_248.bits.param, UInt<2>(0h0) connect _WIRE_248.bits.opcode, UInt<3>(0h0) connect _WIRE_248.valid, UInt<1>(0h0) connect _WIRE_248.ready, UInt<1>(0h0) wire _WIRE_249 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_249.bits, _WIRE_248.bits connect _WIRE_249.valid, _WIRE_248.valid connect _WIRE_249.ready, _WIRE_248.ready invalidate _WIRE_249.bits.corrupt invalidate _WIRE_249.bits.data invalidate _WIRE_249.bits.mask invalidate _WIRE_249.bits.address invalidate _WIRE_249.bits.source invalidate _WIRE_249.bits.size invalidate _WIRE_249.bits.param invalidate _WIRE_249.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node readys_lo_lo = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_lo_hi = cat(portsDIO_filtered_3[0].valid, portsDIO_filtered_2[0].valid) node readys_lo = cat(readys_lo_hi, readys_lo_lo) node readys_hi_lo = cat(portsDIO_filtered_5[0].valid, portsDIO_filtered_4[0].valid) node readys_hi_hi = cat(portsDIO_filtered_7[0].valid, portsDIO_filtered_6[0].valid) node readys_hi = cat(readys_hi_hi, readys_hi_lo) node _readys_T = cat(readys_hi, readys_lo) node readys_valid = bits(_readys_T, 7, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<8>, clock, reset, UInt<8>(0hff) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = shr(_readys_unready_T_1, 2) node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2) node _readys_unready_T_4 = shr(_readys_unready_T_3, 4) node _readys_unready_T_5 = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_unready_T_6 = bits(_readys_unready_T_5, 15, 0) node _readys_unready_T_7 = shr(_readys_unready_T_6, 1) node _readys_unready_T_8 = shl(readys_mask, 8) node readys_unready = or(_readys_unready_T_7, _readys_unready_T_8) node _readys_readys_T = shr(readys_unready, 8) node _readys_readys_T_1 = bits(readys_unready, 7, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 7, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = shl(_readys_mask_T_3, 2) node _readys_mask_T_5 = bits(_readys_mask_T_4, 7, 0) node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5) node _readys_mask_T_7 = shl(_readys_mask_T_6, 4) node _readys_mask_T_8 = bits(_readys_mask_T_7, 7, 0) node _readys_mask_T_9 = or(_readys_mask_T_6, _readys_mask_T_8) node _readys_mask_T_10 = bits(_readys_mask_T_9, 7, 0) connect readys_mask, _readys_mask_T_10 node _readys_T_7 = bits(readys_readys, 7, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) node _readys_T_10 = bits(_readys_T_7, 2, 2) node _readys_T_11 = bits(_readys_T_7, 3, 3) node _readys_T_12 = bits(_readys_T_7, 4, 4) node _readys_T_13 = bits(_readys_T_7, 5, 5) node _readys_T_14 = bits(_readys_T_7, 6, 6) node _readys_T_15 = bits(_readys_T_7, 7, 7) wire readys : UInt<1>[8] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 connect readys[2], _readys_T_10 connect readys[3], _readys_T_11 connect readys[4], _readys_T_12 connect readys[5], _readys_T_13 connect readys[6], _readys_T_14 connect readys[7], _readys_T_15 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) node _winner_T_2 = and(readys[2], portsDIO_filtered_2[0].valid) node _winner_T_3 = and(readys[3], portsDIO_filtered_3[0].valid) node _winner_T_4 = and(readys[4], portsDIO_filtered_4[0].valid) node _winner_T_5 = and(readys[5], portsDIO_filtered_5[0].valid) node _winner_T_6 = and(readys[6], portsDIO_filtered_6[0].valid) node _winner_T_7 = and(readys[7], portsDIO_filtered_7[0].valid) wire winner : UInt<1>[8] connect winner[0], _winner_T connect winner[1], _winner_T_1 connect winner[2], _winner_T_2 connect winner[3], _winner_T_3 connect winner[4], _winner_T_4 connect winner[5], _winner_T_5 connect winner[6], _winner_T_6 connect winner[7], _winner_T_7 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node prefixOR_2 = or(prefixOR_1, winner[1]) node prefixOR_3 = or(prefixOR_2, winner[2]) node prefixOR_4 = or(prefixOR_3, winner[3]) node prefixOR_5 = or(prefixOR_4, winner[4]) node prefixOR_6 = or(prefixOR_5, winner[5]) node prefixOR_7 = or(prefixOR_6, winner[6]) node _prefixOR_T = or(prefixOR_7, winner[7]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(prefixOR_2, UInt<1>(0h0)) node _T_7 = eq(winner[2], UInt<1>(0h0)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(prefixOR_3, UInt<1>(0h0)) node _T_10 = eq(winner[3], UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = eq(prefixOR_4, UInt<1>(0h0)) node _T_13 = eq(winner[4], UInt<1>(0h0)) node _T_14 = or(_T_12, _T_13) node _T_15 = eq(prefixOR_5, UInt<1>(0h0)) node _T_16 = eq(winner[5], UInt<1>(0h0)) node _T_17 = or(_T_15, _T_16) node _T_18 = eq(prefixOR_6, UInt<1>(0h0)) node _T_19 = eq(winner[6], UInt<1>(0h0)) node _T_20 = or(_T_18, _T_19) node _T_21 = eq(prefixOR_7, UInt<1>(0h0)) node _T_22 = eq(winner[7], UInt<1>(0h0)) node _T_23 = or(_T_21, _T_22) node _T_24 = and(_T_2, _T_5) node _T_25 = and(_T_24, _T_8) node _T_26 = and(_T_25, _T_11) node _T_27 = and(_T_26, _T_14) node _T_28 = and(_T_27, _T_17) node _T_29 = and(_T_28, _T_20) node _T_30 = and(_T_29, _T_23) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_30, UInt<1>(0h1), "") : assert node _T_34 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_35 = or(_T_34, portsDIO_filtered_2[0].valid) node _T_36 = or(_T_35, portsDIO_filtered_3[0].valid) node _T_37 = or(_T_36, portsDIO_filtered_4[0].valid) node _T_38 = or(_T_37, portsDIO_filtered_5[0].valid) node _T_39 = or(_T_38, portsDIO_filtered_6[0].valid) node _T_40 = or(_T_39, portsDIO_filtered_7[0].valid) node _T_41 = eq(_T_40, UInt<1>(0h0)) node _T_42 = or(winner[0], winner[1]) node _T_43 = or(_T_42, winner[2]) node _T_44 = or(_T_43, winner[3]) node _T_45 = or(_T_44, winner[4]) node _T_46 = or(_T_45, winner[5]) node _T_47 = or(_T_46, winner[6]) node _T_48 = or(_T_47, winner[7]) node _T_49 = or(_T_41, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_49, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node maskedBeats_2 = mux(winner[2], beatsDO_2, UInt<1>(0h0)) node maskedBeats_3 = mux(winner[3], beatsDO_3, UInt<1>(0h0)) node maskedBeats_4 = mux(winner[4], beatsDO_4, UInt<1>(0h0)) node maskedBeats_5 = mux(winner[5], beatsDO_5, UInt<1>(0h0)) node maskedBeats_6 = mux(winner[6], beatsDO_6, UInt<1>(0h0)) node maskedBeats_7 = mux(winner[7], beatsDO_7, UInt<1>(0h0)) node _initBeats_T = or(maskedBeats_0, maskedBeats_1) node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2) node _initBeats_T_2 = or(_initBeats_T_1, maskedBeats_3) node _initBeats_T_3 = or(_initBeats_T_2, maskedBeats_4) node _initBeats_T_4 = or(_initBeats_T_3, maskedBeats_5) node _initBeats_T_5 = or(_initBeats_T_4, maskedBeats_6) node initBeats = or(_initBeats_T_5, maskedBeats_7) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[8] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) connect _state_WIRE[2], UInt<1>(0h0) connect _state_WIRE[3], UInt<1>(0h0) connect _state_WIRE[4], UInt<1>(0h0) connect _state_WIRE[5], UInt<1>(0h0) connect _state_WIRE[6], UInt<1>(0h0) connect _state_WIRE[7], UInt<1>(0h0) regreset state : UInt<1>[8], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed[2]) connect portsDIO_filtered_2[0].ready, _filtered_0_ready_T_2 node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed[3]) connect portsDIO_filtered_3[0].ready, _filtered_0_ready_T_3 node _filtered_0_ready_T_4 = and(in[0].d.ready, allowed[4]) connect portsDIO_filtered_4[0].ready, _filtered_0_ready_T_4 node _filtered_0_ready_T_5 = and(in[0].d.ready, allowed[5]) connect portsDIO_filtered_5[0].ready, _filtered_0_ready_T_5 node _filtered_0_ready_T_6 = and(in[0].d.ready, allowed[6]) connect portsDIO_filtered_6[0].ready, _filtered_0_ready_T_6 node _filtered_0_ready_T_7 = and(in[0].d.ready, allowed[7]) connect portsDIO_filtered_7[0].ready, _filtered_0_ready_T_7 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = or(_in_0_d_valid_T, portsDIO_filtered_2[0].valid) node _in_0_d_valid_T_2 = or(_in_0_d_valid_T_1, portsDIO_filtered_3[0].valid) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_2, portsDIO_filtered_4[0].valid) node _in_0_d_valid_T_4 = or(_in_0_d_valid_T_3, portsDIO_filtered_5[0].valid) node _in_0_d_valid_T_5 = or(_in_0_d_valid_T_4, portsDIO_filtered_6[0].valid) node _in_0_d_valid_T_6 = or(_in_0_d_valid_T_5, portsDIO_filtered_7[0].valid) node _in_0_d_valid_T_7 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_8 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_9 = mux(state[2], portsDIO_filtered_2[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_10 = mux(state[3], portsDIO_filtered_3[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_11 = mux(state[4], portsDIO_filtered_4[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_12 = mux(state[5], portsDIO_filtered_5[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_13 = mux(state[6], portsDIO_filtered_6[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_14 = mux(state[7], portsDIO_filtered_7[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_15 = or(_in_0_d_valid_T_7, _in_0_d_valid_T_8) node _in_0_d_valid_T_16 = or(_in_0_d_valid_T_15, _in_0_d_valid_T_9) node _in_0_d_valid_T_17 = or(_in_0_d_valid_T_16, _in_0_d_valid_T_10) node _in_0_d_valid_T_18 = or(_in_0_d_valid_T_17, _in_0_d_valid_T_11) node _in_0_d_valid_T_19 = or(_in_0_d_valid_T_18, _in_0_d_valid_T_12) node _in_0_d_valid_T_20 = or(_in_0_d_valid_T_19, _in_0_d_valid_T_13) node _in_0_d_valid_T_21 = or(_in_0_d_valid_T_20, _in_0_d_valid_T_14) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_21 node _in_0_d_valid_T_22 = mux(idle, _in_0_d_valid_T_6, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_22 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = mux(muxState[2], portsDIO_filtered_2[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_3 = mux(muxState[3], portsDIO_filtered_3[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[4], portsDIO_filtered_4[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_5 = mux(muxState[5], portsDIO_filtered_5[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_6 = mux(muxState[6], portsDIO_filtered_6[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[7], portsDIO_filtered_7[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) node _in_0_d_bits_T_9 = or(_in_0_d_bits_T_8, _in_0_d_bits_T_2) node _in_0_d_bits_T_10 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_3) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_10, _in_0_d_bits_T_4) node _in_0_d_bits_T_12 = or(_in_0_d_bits_T_11, _in_0_d_bits_T_5) node _in_0_d_bits_T_13 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_6) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_13, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_17 = mux(muxState[2], portsDIO_filtered_2[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_18 = mux(muxState[3], portsDIO_filtered_3[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[4], portsDIO_filtered_4[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_20 = mux(muxState[5], portsDIO_filtered_5[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_21 = mux(muxState[6], portsDIO_filtered_6[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[7], portsDIO_filtered_7[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) node _in_0_d_bits_T_24 = or(_in_0_d_bits_T_23, _in_0_d_bits_T_17) node _in_0_d_bits_T_25 = or(_in_0_d_bits_T_24, _in_0_d_bits_T_18) node _in_0_d_bits_T_26 = or(_in_0_d_bits_T_25, _in_0_d_bits_T_19) node _in_0_d_bits_T_27 = or(_in_0_d_bits_T_26, _in_0_d_bits_T_20) node _in_0_d_bits_T_28 = or(_in_0_d_bits_T_27, _in_0_d_bits_T_21) node _in_0_d_bits_T_29 = or(_in_0_d_bits_T_28, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_29 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_30 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_31 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_32 = mux(muxState[2], portsDIO_filtered_2[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_33 = mux(muxState[3], portsDIO_filtered_3[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_34 = mux(muxState[4], portsDIO_filtered_4[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_35 = mux(muxState[5], portsDIO_filtered_5[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_36 = mux(muxState[6], portsDIO_filtered_6[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_37 = mux(muxState[7], portsDIO_filtered_7[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_38 = or(_in_0_d_bits_T_30, _in_0_d_bits_T_31) node _in_0_d_bits_T_39 = or(_in_0_d_bits_T_38, _in_0_d_bits_T_32) node _in_0_d_bits_T_40 = or(_in_0_d_bits_T_39, _in_0_d_bits_T_33) node _in_0_d_bits_T_41 = or(_in_0_d_bits_T_40, _in_0_d_bits_T_34) node _in_0_d_bits_T_42 = or(_in_0_d_bits_T_41, _in_0_d_bits_T_35) node _in_0_d_bits_T_43 = or(_in_0_d_bits_T_42, _in_0_d_bits_T_36) node _in_0_d_bits_T_44 = or(_in_0_d_bits_T_43, _in_0_d_bits_T_37) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_44 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_45 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_46 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_47 = mux(muxState[2], portsDIO_filtered_2[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_48 = mux(muxState[3], portsDIO_filtered_3[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_49 = mux(muxState[4], portsDIO_filtered_4[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_50 = mux(muxState[5], portsDIO_filtered_5[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_51 = mux(muxState[6], portsDIO_filtered_6[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_52 = mux(muxState[7], portsDIO_filtered_7[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_53 = or(_in_0_d_bits_T_45, _in_0_d_bits_T_46) node _in_0_d_bits_T_54 = or(_in_0_d_bits_T_53, _in_0_d_bits_T_47) node _in_0_d_bits_T_55 = or(_in_0_d_bits_T_54, _in_0_d_bits_T_48) node _in_0_d_bits_T_56 = or(_in_0_d_bits_T_55, _in_0_d_bits_T_49) node _in_0_d_bits_T_57 = or(_in_0_d_bits_T_56, _in_0_d_bits_T_50) node _in_0_d_bits_T_58 = or(_in_0_d_bits_T_57, _in_0_d_bits_T_51) node _in_0_d_bits_T_59 = or(_in_0_d_bits_T_58, _in_0_d_bits_T_52) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_59 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_60 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_61 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_62 = mux(muxState[2], portsDIO_filtered_2[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_63 = mux(muxState[3], portsDIO_filtered_3[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_64 = mux(muxState[4], portsDIO_filtered_4[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_65 = mux(muxState[5], portsDIO_filtered_5[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_66 = mux(muxState[6], portsDIO_filtered_6[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_67 = mux(muxState[7], portsDIO_filtered_7[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_68 = or(_in_0_d_bits_T_60, _in_0_d_bits_T_61) node _in_0_d_bits_T_69 = or(_in_0_d_bits_T_68, _in_0_d_bits_T_62) node _in_0_d_bits_T_70 = or(_in_0_d_bits_T_69, _in_0_d_bits_T_63) node _in_0_d_bits_T_71 = or(_in_0_d_bits_T_70, _in_0_d_bits_T_64) node _in_0_d_bits_T_72 = or(_in_0_d_bits_T_71, _in_0_d_bits_T_65) node _in_0_d_bits_T_73 = or(_in_0_d_bits_T_72, _in_0_d_bits_T_66) node _in_0_d_bits_T_74 = or(_in_0_d_bits_T_73, _in_0_d_bits_T_67) wire _in_0_d_bits_WIRE_7 : UInt<7> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_74 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_75 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_76 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_77 = mux(muxState[2], portsDIO_filtered_2[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_78 = mux(muxState[3], portsDIO_filtered_3[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_79 = mux(muxState[4], portsDIO_filtered_4[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_80 = mux(muxState[5], portsDIO_filtered_5[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_81 = mux(muxState[6], portsDIO_filtered_6[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_82 = mux(muxState[7], portsDIO_filtered_7[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_83 = or(_in_0_d_bits_T_75, _in_0_d_bits_T_76) node _in_0_d_bits_T_84 = or(_in_0_d_bits_T_83, _in_0_d_bits_T_77) node _in_0_d_bits_T_85 = or(_in_0_d_bits_T_84, _in_0_d_bits_T_78) node _in_0_d_bits_T_86 = or(_in_0_d_bits_T_85, _in_0_d_bits_T_79) node _in_0_d_bits_T_87 = or(_in_0_d_bits_T_86, _in_0_d_bits_T_80) node _in_0_d_bits_T_88 = or(_in_0_d_bits_T_87, _in_0_d_bits_T_81) node _in_0_d_bits_T_89 = or(_in_0_d_bits_T_88, _in_0_d_bits_T_82) wire _in_0_d_bits_WIRE_8 : UInt<4> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_89 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_90 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_91 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_92 = mux(muxState[2], portsDIO_filtered_2[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_93 = mux(muxState[3], portsDIO_filtered_3[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_94 = mux(muxState[4], portsDIO_filtered_4[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_95 = mux(muxState[5], portsDIO_filtered_5[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_96 = mux(muxState[6], portsDIO_filtered_6[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_97 = mux(muxState[7], portsDIO_filtered_7[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_98 = or(_in_0_d_bits_T_90, _in_0_d_bits_T_91) node _in_0_d_bits_T_99 = or(_in_0_d_bits_T_98, _in_0_d_bits_T_92) node _in_0_d_bits_T_100 = or(_in_0_d_bits_T_99, _in_0_d_bits_T_93) node _in_0_d_bits_T_101 = or(_in_0_d_bits_T_100, _in_0_d_bits_T_94) node _in_0_d_bits_T_102 = or(_in_0_d_bits_T_101, _in_0_d_bits_T_95) node _in_0_d_bits_T_103 = or(_in_0_d_bits_T_102, _in_0_d_bits_T_96) node _in_0_d_bits_T_104 = or(_in_0_d_bits_T_103, _in_0_d_bits_T_97) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_104 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_105 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_106 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_107 = mux(muxState[2], portsDIO_filtered_2[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_108 = mux(muxState[3], portsDIO_filtered_3[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_109 = mux(muxState[4], portsDIO_filtered_4[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_110 = mux(muxState[5], portsDIO_filtered_5[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_111 = mux(muxState[6], portsDIO_filtered_6[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_112 = mux(muxState[7], portsDIO_filtered_7[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_113 = or(_in_0_d_bits_T_105, _in_0_d_bits_T_106) node _in_0_d_bits_T_114 = or(_in_0_d_bits_T_113, _in_0_d_bits_T_107) node _in_0_d_bits_T_115 = or(_in_0_d_bits_T_114, _in_0_d_bits_T_108) node _in_0_d_bits_T_116 = or(_in_0_d_bits_T_115, _in_0_d_bits_T_109) node _in_0_d_bits_T_117 = or(_in_0_d_bits_T_116, _in_0_d_bits_T_110) node _in_0_d_bits_T_118 = or(_in_0_d_bits_T_117, _in_0_d_bits_T_111) node _in_0_d_bits_T_119 = or(_in_0_d_bits_T_118, _in_0_d_bits_T_112) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_119 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) connect portsBIO_filtered_2[0].ready, UInt<1>(0h0) connect portsBIO_filtered_3[0].ready, UInt<1>(0h0) connect portsBIO_filtered_4[0].ready, UInt<1>(0h0) connect portsBIO_filtered_5[0].ready, UInt<1>(0h0) connect portsBIO_filtered_6[0].ready, UInt<1>(0h0) connect portsBIO_filtered_7[0].ready, UInt<1>(0h0) extmodule plusarg_reader_34 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_35 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLXbar_cbus_out_i1_o8_a32d64s7k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_anon_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_7_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_7_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_6_d_bits_size; // @[Xbar.scala:216:19] wire out_5_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_5_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_4_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_3_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_2_d_bits_size; // @[Xbar.scala:216:19] wire out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19] wire out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_7_a_ready_0 = auto_anon_out_7_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_7_d_valid_0 = auto_anon_out_7_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_7_d_bits_opcode_0 = auto_anon_out_7_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_7_d_bits_param_0 = auto_anon_out_7_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_7_d_bits_size_0 = auto_anon_out_7_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_7_d_bits_source_0 = auto_anon_out_7_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_7_d_bits_sink_0 = auto_anon_out_7_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_7_d_bits_denied_0 = auto_anon_out_7_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_7_d_bits_data_0 = auto_anon_out_7_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_7_d_bits_corrupt_0 = auto_anon_out_7_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_6_a_ready_0 = auto_anon_out_6_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_6_d_valid_0 = auto_anon_out_6_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_6_d_bits_size_0 = auto_anon_out_6_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_6_d_bits_source_0 = auto_anon_out_6_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_6_d_bits_data_0 = auto_anon_out_6_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_5_a_ready_0 = auto_anon_out_5_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_5_d_valid_0 = auto_anon_out_5_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_5_d_bits_opcode_0 = auto_anon_out_5_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_5_d_bits_param_0 = auto_anon_out_5_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_5_d_bits_size_0 = auto_anon_out_5_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_5_d_bits_source_0 = auto_anon_out_5_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_5_d_bits_sink_0 = auto_anon_out_5_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_5_d_bits_denied_0 = auto_anon_out_5_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_5_d_bits_data_0 = auto_anon_out_5_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_5_d_bits_corrupt_0 = auto_anon_out_5_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_4_a_ready_0 = auto_anon_out_4_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_4_d_valid_0 = auto_anon_out_4_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_4_d_bits_opcode_0 = auto_anon_out_4_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_4_d_bits_size_0 = auto_anon_out_4_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_4_d_bits_source_0 = auto_anon_out_4_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_4_d_bits_data_0 = auto_anon_out_4_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_3_a_ready_0 = auto_anon_out_3_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_3_d_valid_0 = auto_anon_out_3_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_3_d_bits_opcode_0 = auto_anon_out_3_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_3_d_bits_size_0 = auto_anon_out_3_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_3_d_bits_source_0 = auto_anon_out_3_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_3_d_bits_data_0 = auto_anon_out_3_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_2_a_ready_0 = auto_anon_out_2_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_2_d_valid_0 = auto_anon_out_2_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_2_d_bits_opcode_0 = auto_anon_out_2_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_2_d_bits_size_0 = auto_anon_out_2_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_2_d_bits_source_0 = auto_anon_out_2_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_2_d_bits_data_0 = auto_anon_out_2_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_out_6_d_bits_opcode = 3'h1; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_5_d_bits_opcode = 3'h1; // @[MixedNode.scala:542:17] wire [2:0] out_6_d_bits_opcode = 3'h1; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_6_0_bits_opcode = 3'h1; // @[Xbar.scala:352:24] wire [1:0] auto_anon_out_6_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_4_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_3_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_2_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_1_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_2_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_3_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_5_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] out_2_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_3_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_4_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_6_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_8_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_9_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_10_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_11_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_12_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_13_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_14_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_15_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_8_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_9_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_10_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_11_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_12_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_13_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_14_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_15_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_2_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_3_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_8_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_9_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_4_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_10_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_11_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_5_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_12_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_13_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_6_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_14_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_15_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_7_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_2_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_3_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_4_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_6_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_T_92 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_93 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_94 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_96 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_out_6_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_6_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_6_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_4_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_4_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_4_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_3_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_3_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_3_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_2_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_2_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_2_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire x1_anonOut_1_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_1_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_2_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_2_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_2_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_3_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_3_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_3_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_5_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_5_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_5_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire out_2_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_2_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_2_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_3_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_3_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_3_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_4_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_4_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_4_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_6_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_6_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_6_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_2_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_3_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_4_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_6_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_10 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_15 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_8_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_8_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_8_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_9_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_9_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_9_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_20 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_10_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_10_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_10_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_11_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_11_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_11_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_25 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_12_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_12_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_12_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_13_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_13_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_13_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_30 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_14_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_14_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_14_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_15_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_15_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_15_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_35 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_10 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_15 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_20 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_25 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_30 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_35 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_4_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_5_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_5_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_5_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_6_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_6_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_6_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_7_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_7_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_7_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_8_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_8_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_8_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_9_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_9_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_9_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_10_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_10_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_10_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_11_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_11_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_11_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_12_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_12_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_12_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_13_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_13_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_13_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_14_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_14_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_14_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_15_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_15_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_15_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_2 = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_3 = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_8_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_8_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_8_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_9_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_9_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_9_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_4 = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_10_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_10_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_10_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_11_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_11_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_11_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_5 = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_12_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_12_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_12_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_13_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_13_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_13_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_6 = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_14_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_14_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_14_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_15_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_15_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_15_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_7 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_7 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_8_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_8_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_8_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_9_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_9_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_9_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_9 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_10_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_10_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_10_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_11_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_11_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_11_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_5_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_5_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_5_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_11 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_12_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_12_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_12_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_13_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_13_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_13_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_6_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_6_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_6_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_13 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_14_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_14_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_14_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_15_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_15_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_15_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_7_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_7_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_7_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_15 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_3_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_3_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_4_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_4_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_5_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_5_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_5_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_6_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_6_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_6_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_7_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_7_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_7_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_3_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_4_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_5_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_6_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_7_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_6 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_7 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_8 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_9 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_10 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_11 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_12 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_13 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_14 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_2_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_3_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_3_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_3_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_4_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_4_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_4_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_6_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_6_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_6_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_3_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_3_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_3_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_4_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_4_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_4_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_5_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_5_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_5_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_6_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_6_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_6_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_7_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_7_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_7_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_2_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_3_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_3_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_4_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_4_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_5_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_5_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_6_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_6_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_7_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_7_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_6 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_7 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_8 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_9 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_10 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_11 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_12 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_13 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_14 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_5 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_6 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_7 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_3 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_4 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_32 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_33 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_34 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_36 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_47 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_48 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_49 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_51 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_2 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_3 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_24 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_4 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_29 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_5 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_34 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_6 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_39 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_7 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_11 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_13 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_2_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_16 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_18 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_3_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_21 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_23 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_4_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_26 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_28 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_5_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_31 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_33 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_34 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_6_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_36 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_38 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_39 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_7_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_11 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_13 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_2_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_16 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_18 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_3_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_21 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_23 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_4_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_26 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_28 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_5_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_31 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_33 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_34 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_6_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_36 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_38 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_39 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_7_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_2 = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_3 = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_4 = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_5 = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_6 = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_7 = 1'h1; // @[Edges.scala:97:28] wire beatsDO_opdata_6 = 1'h1; // @[Edges.scala:106:36] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_10 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_12 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_14 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_2_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_3_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_4_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_5_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_6_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_7_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_10 = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_12 = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_14 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_6_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_7_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_8_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_9_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_10_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_11_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_12_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_13_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_14_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_15_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_6_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_7_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_8_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_9_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_10_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_11_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_12_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_13_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_14_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_15_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_2_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_6_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_7_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_3_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_8_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_9_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_4_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_10_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_11_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_5_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_12_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_13_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_6_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_14_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_15_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_7_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_2_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_3_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_4_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_5_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_6_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_7_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_10 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_15 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_20 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_25 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_30 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_35 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_6_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_7_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_8_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_9_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_10_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_11_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_12_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_13_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_14_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_15_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_6_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_7_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_8_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_9_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_10_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_11_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_12_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_13_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_14_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_15_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_2_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_6_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_7_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_3_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_8_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_9_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_4_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_10_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_11_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_5_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_12_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_13_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_6_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_14_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_15_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_7_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_2_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_3_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_4_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_5_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_6_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_7_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [6:0] _addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_1 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_1 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_2 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_2 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_6_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_7_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_3 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_3 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_8_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_9_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_4 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_4 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_10_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_11_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_5 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_5 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_12_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_13_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_6 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_6 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_14_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_15_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_7 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_7 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_6_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_7_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_8_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_9_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_10_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_11_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_12_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_13_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_14_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_15_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_1_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_2_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_6_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_7_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_3_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_8_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_9_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_4_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_10_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_11_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_5_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_12_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_13_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_6_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_14_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_15_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_7_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_2_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_3_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_4_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_5_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_6_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_7_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_8_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_9_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_10_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_11_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_12_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_13_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_14_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_15_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_8_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_9_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_10_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_11_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_12_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_13_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_14_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_15_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_2_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_3_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_8_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_9_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_4_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_10_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_11_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_5_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_12_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_13_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_6_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_14_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_15_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_7_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_2_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_3_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_4_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_5_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_6_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_7_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_8_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_9_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_10_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_11_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_12_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_13_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_14_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_15_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_2 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_2 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_3 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_3 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_8_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_9_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_4 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_4 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_10_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_11_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_5 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_5 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_12_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_13_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_6 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_6 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_14_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_15_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_7 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_7 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_2_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_3_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_8_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_9_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_4_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_10_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_11_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_5_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_12_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_13_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_6_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_14_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_15_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_7_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_2_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_2_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_3_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_3_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_4_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_4_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_5_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_5_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_6_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_6_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_7_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_7_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_4_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_5_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_6_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_7_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_8_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_9_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_10_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_11_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_12_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_13_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_14_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_15_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_4_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_5_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_6_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_7_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_8_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_9_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_10_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_11_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_12_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_13_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_14_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_15_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_4_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_5_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_2_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_6_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_7_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_3_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_8_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_9_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_4_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_10_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_11_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_5_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_12_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_13_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_6_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_14_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_15_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_7_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_8 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_11 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_14 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_17 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_20 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_23 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_7 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_10 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_13 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_16 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_19 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_22 = 6'h3F; // @[package.scala:243:76] wire [20:0] _beatsBO_decode_T_3 = 21'h3F; // @[package.scala:243:71] wire [20:0] _beatsBO_decode_T_6 = 21'h3F; // @[package.scala:243:71] wire [20:0] _beatsBO_decode_T_9 = 21'h3F; // @[package.scala:243:71] wire [20:0] _beatsBO_decode_T_12 = 21'h3F; // @[package.scala:243:71] wire [20:0] _beatsBO_decode_T_15 = 21'h3F; // @[package.scala:243:71] wire [20:0] _beatsBO_decode_T_18 = 21'h3F; // @[package.scala:243:71] wire [20:0] _beatsBO_decode_T_21 = 21'h3F; // @[package.scala:243:71] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_11 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_16 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_21 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_22 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_23 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_26 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_27 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_28 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_31 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_32 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_33 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_36 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_38 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_6_a_ready = auto_anon_out_7_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_6_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_6_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_6_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_6_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] x1_anonOut_6_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_6_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_6_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_6_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_6_d_valid = auto_anon_out_7_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_6_d_bits_opcode = auto_anon_out_7_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_6_d_bits_param = auto_anon_out_7_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_6_d_bits_size = auto_anon_out_7_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_6_d_bits_source = auto_anon_out_7_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_6_d_bits_sink = auto_anon_out_7_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_6_d_bits_denied = auto_anon_out_7_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_6_d_bits_data = auto_anon_out_7_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_6_d_bits_corrupt = auto_anon_out_7_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire x1_anonOut_5_a_ready = auto_anon_out_6_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_5_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_5_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_5_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_5_a_bits_source; // @[MixedNode.scala:542:17] wire [16:0] x1_anonOut_5_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_5_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_5_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_5_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_5_d_valid = auto_anon_out_6_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_5_d_bits_size = auto_anon_out_6_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_5_d_bits_source = auto_anon_out_6_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_5_d_bits_data = auto_anon_out_6_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_4_a_ready = auto_anon_out_5_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_4_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_4_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_4_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_4_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_4_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_4_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_4_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_4_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_4_d_valid = auto_anon_out_5_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_4_d_bits_opcode = auto_anon_out_5_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_4_d_bits_param = auto_anon_out_5_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_4_d_bits_size = auto_anon_out_5_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_4_d_bits_source = auto_anon_out_5_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_4_d_bits_sink = auto_anon_out_5_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_4_d_bits_denied = auto_anon_out_5_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_4_d_bits_data = auto_anon_out_5_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_4_d_bits_corrupt = auto_anon_out_5_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire x1_anonOut_3_a_ready = auto_anon_out_4_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_3_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_3_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_3_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_3_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] x1_anonOut_3_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_3_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_3_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_3_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_3_d_valid = auto_anon_out_4_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_3_d_bits_opcode = auto_anon_out_4_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_3_d_bits_size = auto_anon_out_4_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_3_d_bits_source = auto_anon_out_4_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_3_d_bits_data = auto_anon_out_4_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_2_a_ready = auto_anon_out_3_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_2_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_2_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_2_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_2_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_anonOut_2_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_2_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_2_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_2_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_2_d_valid = auto_anon_out_3_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_2_d_bits_opcode = auto_anon_out_3_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_2_d_bits_size = auto_anon_out_3_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_2_d_bits_source = auto_anon_out_3_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_2_d_bits_data = auto_anon_out_3_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_1_a_ready = auto_anon_out_2_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_1_d_valid = auto_anon_out_2_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_1_d_bits_opcode = auto_anon_out_2_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_1_d_bits_size = auto_anon_out_2_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_1_d_bits_source = auto_anon_out_2_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_1_d_bits_data = auto_anon_out_2_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [13:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_7_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_7_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_7_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_7_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_7_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_7_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_7_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_7_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_7_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_7_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_6_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_6_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_6_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_6_a_bits_source_0; // @[Xbar.scala:74:9] wire [16:0] auto_anon_out_6_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_6_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_6_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_6_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_6_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_6_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_5_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_5_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_5_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_5_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_5_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_5_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_5_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_5_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_5_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_5_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_4_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_4_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_4_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_4_a_bits_source_0; // @[Xbar.scala:74:9] wire [11:0] auto_anon_out_4_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_4_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_4_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_4_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_4_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_4_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_3_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_3_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_3_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_3_a_bits_source_0; // @[Xbar.scala:74:9] wire [27:0] auto_anon_out_3_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_3_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_3_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_3_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_3_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_3_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_2_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_2_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_2_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_2_a_bits_source_0; // @[Xbar.scala:74:9] wire [25:0] auto_anon_out_2_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_2_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_2_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_2_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_2_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_2_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [13:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [6:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_2_a_ready = x1_anonOut_1_a_ready; // @[Xbar.scala:216:19] wire out_2_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_2_a_valid_0 = x1_anonOut_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_2_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_2_a_bits_opcode_0 = x1_anonOut_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_2_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_2_a_bits_param_0 = x1_anonOut_1_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_2_a_bits_size_0 = x1_anonOut_1_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_2_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_2_a_bits_source_0 = x1_anonOut_1_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_2_a_bits_address_0 = x1_anonOut_1_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_2_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_2_a_bits_mask_0 = x1_anonOut_1_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_2_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_2_a_bits_data_0 = x1_anonOut_1_a_bits_data; // @[Xbar.scala:74:9] wire out_2_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_2_a_bits_corrupt_0 = x1_anonOut_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_2_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_2_d_ready_0 = x1_anonOut_1_d_ready; // @[Xbar.scala:74:9] wire out_2_d_valid = x1_anonOut_1_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_2_d_bits_opcode = x1_anonOut_1_d_bits_opcode; // @[Xbar.scala:216:19] wire [6:0] out_2_d_bits_source = x1_anonOut_1_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_2_d_bits_data = x1_anonOut_1_d_bits_data; // @[Xbar.scala:216:19] wire out_3_a_ready = x1_anonOut_2_a_ready; // @[Xbar.scala:216:19] wire out_3_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_3_a_valid_0 = x1_anonOut_2_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_3_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_3_a_bits_opcode_0 = x1_anonOut_2_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_3_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_3_a_bits_param_0 = x1_anonOut_2_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_3_a_bits_size_0 = x1_anonOut_2_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_3_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_3_a_bits_source_0 = x1_anonOut_2_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_3_a_bits_address_0 = x1_anonOut_2_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_3_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_3_a_bits_mask_0 = x1_anonOut_2_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_3_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_3_a_bits_data_0 = x1_anonOut_2_a_bits_data; // @[Xbar.scala:74:9] wire out_3_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_3_a_bits_corrupt_0 = x1_anonOut_2_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_3_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_3_d_ready_0 = x1_anonOut_2_d_ready; // @[Xbar.scala:74:9] wire out_3_d_valid = x1_anonOut_2_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_3_d_bits_opcode = x1_anonOut_2_d_bits_opcode; // @[Xbar.scala:216:19] wire [6:0] out_3_d_bits_source = x1_anonOut_2_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_3_d_bits_data = x1_anonOut_2_d_bits_data; // @[Xbar.scala:216:19] wire out_4_a_ready = x1_anonOut_3_a_ready; // @[Xbar.scala:216:19] wire out_4_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_4_a_valid_0 = x1_anonOut_3_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_4_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_4_a_bits_opcode_0 = x1_anonOut_3_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_4_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_4_a_bits_param_0 = x1_anonOut_3_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_4_a_bits_size_0 = x1_anonOut_3_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_4_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_4_a_bits_source_0 = x1_anonOut_3_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_4_a_bits_address_0 = x1_anonOut_3_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_4_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_4_a_bits_mask_0 = x1_anonOut_3_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_4_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_4_a_bits_data_0 = x1_anonOut_3_a_bits_data; // @[Xbar.scala:74:9] wire out_4_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_4_a_bits_corrupt_0 = x1_anonOut_3_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_4_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_4_d_ready_0 = x1_anonOut_3_d_ready; // @[Xbar.scala:74:9] wire out_4_d_valid = x1_anonOut_3_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_4_d_bits_opcode = x1_anonOut_3_d_bits_opcode; // @[Xbar.scala:216:19] wire [6:0] out_4_d_bits_source = x1_anonOut_3_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_4_d_bits_data = x1_anonOut_3_d_bits_data; // @[Xbar.scala:216:19] wire out_5_a_ready = x1_anonOut_4_a_ready; // @[Xbar.scala:216:19] wire out_5_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_valid_0 = x1_anonOut_4_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_5_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_bits_opcode_0 = x1_anonOut_4_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_5_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_bits_param_0 = x1_anonOut_4_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_5_a_bits_size_0 = x1_anonOut_4_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_5_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_bits_source_0 = x1_anonOut_4_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_5_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_bits_address_0 = x1_anonOut_4_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_5_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_bits_mask_0 = x1_anonOut_4_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_5_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_bits_data_0 = x1_anonOut_4_a_bits_data; // @[Xbar.scala:74:9] wire out_5_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_5_a_bits_corrupt_0 = x1_anonOut_4_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_5_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_5_d_ready_0 = x1_anonOut_4_d_ready; // @[Xbar.scala:74:9] wire out_5_d_valid = x1_anonOut_4_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_5_d_bits_opcode = x1_anonOut_4_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_5_d_bits_param = x1_anonOut_4_d_bits_param; // @[Xbar.scala:216:19] wire [6:0] out_5_d_bits_source = x1_anonOut_4_d_bits_source; // @[Xbar.scala:216:19] wire _out_5_d_bits_sink_T = x1_anonOut_4_d_bits_sink; // @[Xbar.scala:251:53] wire out_5_d_bits_denied = x1_anonOut_4_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_5_d_bits_data = x1_anonOut_4_d_bits_data; // @[Xbar.scala:216:19] wire out_5_d_bits_corrupt = x1_anonOut_4_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_6_a_ready = x1_anonOut_5_a_ready; // @[Xbar.scala:216:19] wire out_6_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_6_a_valid_0 = x1_anonOut_5_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_6_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_6_a_bits_opcode_0 = x1_anonOut_5_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_6_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_6_a_bits_param_0 = x1_anonOut_5_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_6_a_bits_size_0 = x1_anonOut_5_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_6_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_6_a_bits_source_0 = x1_anonOut_5_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_6_a_bits_address_0 = x1_anonOut_5_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_6_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_6_a_bits_mask_0 = x1_anonOut_5_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_6_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_6_a_bits_data_0 = x1_anonOut_5_a_bits_data; // @[Xbar.scala:74:9] wire out_6_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_6_a_bits_corrupt_0 = x1_anonOut_5_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_6_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_6_d_ready_0 = x1_anonOut_5_d_ready; // @[Xbar.scala:74:9] wire out_6_d_valid = x1_anonOut_5_d_valid; // @[Xbar.scala:216:19] wire [6:0] out_6_d_bits_source = x1_anonOut_5_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_6_d_bits_data = x1_anonOut_5_d_bits_data; // @[Xbar.scala:216:19] wire out_7_a_ready = x1_anonOut_6_a_ready; // @[Xbar.scala:216:19] wire out_7_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_7_a_valid_0 = x1_anonOut_6_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_7_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_7_a_bits_opcode_0 = x1_anonOut_6_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_7_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_7_a_bits_param_0 = x1_anonOut_6_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_7_a_bits_size_0 = x1_anonOut_6_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_7_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_7_a_bits_source_0 = x1_anonOut_6_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_7_a_bits_address_0 = x1_anonOut_6_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_7_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_7_a_bits_mask_0 = x1_anonOut_6_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_7_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_7_a_bits_data_0 = x1_anonOut_6_a_bits_data; // @[Xbar.scala:74:9] wire out_7_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_7_a_bits_corrupt_0 = x1_anonOut_6_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_7_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_7_d_ready_0 = x1_anonOut_6_d_ready; // @[Xbar.scala:74:9] wire out_7_d_valid = x1_anonOut_6_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_7_d_bits_opcode = x1_anonOut_6_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_7_d_bits_param = x1_anonOut_6_d_bits_param; // @[Xbar.scala:216:19] wire [6:0] out_7_d_bits_source = x1_anonOut_6_d_bits_source; // @[Xbar.scala:216:19] wire _out_7_d_bits_sink_T = x1_anonOut_6_d_bits_sink; // @[Xbar.scala:251:53] wire out_7_d_bits_denied = x1_anonOut_6_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_7_d_bits_data = x1_anonOut_6_d_bits_data; // @[Xbar.scala:216:19] wire out_7_d_bits_corrupt = x1_anonOut_6_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_5_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_6_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_7_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_5_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_6_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_7_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_2_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_3_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_4_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_5_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_6_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_7_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_2_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_3_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_4_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_5_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_6_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_7_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_26 = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_2_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_3_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_4_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_5_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_6_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_7_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_2_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_3_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_4_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_5_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_6_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_7_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_2_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_3_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_4_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_5_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_6_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_7_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_2_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_3_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_4_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_5_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_6_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_7_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_22; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_2_ready = out_2_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_2_valid; // @[Xbar.scala:352:24] assign x1_anonOut_1_a_valid = out_2_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_1_a_bits_opcode = out_2_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_1_a_bits_param = out_2_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_1_a_bits_source = out_2_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_1_a_bits_mask = out_2_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_1_a_bits_data = out_2_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_1_a_bits_corrupt = out_2_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_2_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_1_d_ready = out_2_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_5 = out_2_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_2_0_bits_opcode = out_2_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_2_0_bits_size = out_2_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_2 = out_2_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_2_0_bits_source = out_2_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_2_0_bits_data = out_2_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_3_ready = out_3_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_3_valid; // @[Xbar.scala:352:24] assign x1_anonOut_2_a_valid = out_3_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_2_a_bits_opcode = out_3_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_2_a_bits_param = out_3_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_2_a_bits_source = out_3_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_2_a_bits_mask = out_3_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_2_a_bits_data = out_3_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_2_a_bits_corrupt = out_3_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_3_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_2_d_ready = out_3_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_7 = out_3_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_3_0_bits_opcode = out_3_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_3_0_bits_size = out_3_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_3 = out_3_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_3_0_bits_source = out_3_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_3_0_bits_data = out_3_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_4_ready = out_4_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_4_valid; // @[Xbar.scala:352:24] assign x1_anonOut_3_a_valid = out_4_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_3_a_bits_opcode = out_4_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_3_a_bits_param = out_4_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_3_a_bits_source = out_4_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_3_a_bits_mask = out_4_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_3_a_bits_data = out_4_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_3_a_bits_corrupt = out_4_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_4_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_3_d_ready = out_4_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_9 = out_4_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_4_0_bits_opcode = out_4_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_4_0_bits_size = out_4_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_4 = out_4_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_4_0_bits_source = out_4_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_4_0_bits_data = out_4_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_5_ready = out_5_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_5_valid; // @[Xbar.scala:352:24] assign x1_anonOut_4_a_valid = out_5_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_4_a_bits_opcode = out_5_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_4_a_bits_param = out_5_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_4_a_bits_source = out_5_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_4_a_bits_address = out_5_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_4_a_bits_mask = out_5_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_4_a_bits_data = out_5_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_4_a_bits_corrupt = out_5_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_5_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_4_d_ready = out_5_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_11 = out_5_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_5_0_bits_opcode = out_5_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_5_0_bits_param = out_5_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_5_0_bits_size = out_5_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_5 = out_5_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_5_0_bits_source = out_5_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_5_0_bits_sink = out_5_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_5_0_bits_denied = out_5_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_5_0_bits_data = out_5_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_5_0_bits_corrupt = out_5_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_6_ready = out_6_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_6_valid; // @[Xbar.scala:352:24] assign x1_anonOut_5_a_valid = out_6_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_5_a_bits_opcode = out_6_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_5_a_bits_param = out_6_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_5_a_bits_source = out_6_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_5_a_bits_mask = out_6_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_5_a_bits_data = out_6_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_5_a_bits_corrupt = out_6_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_6_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_5_d_ready = out_6_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_13 = out_6_d_valid; // @[Xbar.scala:216:19, :355:40] wire [3:0] portsDIO_filtered_6_0_bits_size = out_6_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_6 = out_6_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_6_0_bits_source = out_6_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_6_0_bits_data = out_6_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_7_ready = out_7_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_7_valid; // @[Xbar.scala:352:24] assign x1_anonOut_6_a_valid = out_7_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_6_a_bits_opcode = out_7_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_6_a_bits_param = out_7_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_6_a_bits_source = out_7_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_6_a_bits_mask = out_7_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_6_a_bits_data = out_7_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_6_a_bits_corrupt = out_7_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_7_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_6_d_ready = out_7_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_15 = out_7_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_7_0_bits_opcode = out_7_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_7_0_bits_param = out_7_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_7_0_bits_size = out_7_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_7 = out_7_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_7_0_bits_source = out_7_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_7_0_bits_sink = out_7_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_7_0_bits_denied = out_7_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_7_0_bits_data = out_7_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] wire portsDIO_filtered_7_0_bits_corrupt = out_7_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] out_2_a_bits_size; // @[Xbar.scala:216:19] wire [31:0] out_2_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] out_3_a_bits_size; // @[Xbar.scala:216:19] wire [31:0] out_3_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] out_4_a_bits_size; // @[Xbar.scala:216:19] wire [31:0] out_4_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] out_5_a_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_6_a_bits_size; // @[Xbar.scala:216:19] wire [31:0] out_6_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] out_7_a_bits_size; // @[Xbar.scala:216:19] wire [31:0] out_7_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[13:0]; // @[Xbar.scala:216:19, :222:41] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign x1_anonOut_a_bits_address = out_1_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign x1_anonOut_1_a_bits_address = out_2_a_bits_address[25:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_1_a_bits_size = out_2_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_2_d_bits_size = {1'h0, x1_anonOut_1_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign x1_anonOut_2_a_bits_address = out_3_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_2_a_bits_size = out_3_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_3_d_bits_size = {1'h0, x1_anonOut_2_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign x1_anonOut_3_a_bits_address = out_4_a_bits_address[11:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_3_a_bits_size = out_4_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_4_d_bits_size = {1'h0, x1_anonOut_3_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign x1_anonOut_4_a_bits_size = out_5_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_5_d_bits_size = {1'h0, x1_anonOut_4_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_5_d_bits_sink = _out_5_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign x1_anonOut_5_a_bits_address = out_6_a_bits_address[16:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_5_a_bits_size = out_6_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_6_d_bits_size = {1'h0, x1_anonOut_5_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign x1_anonOut_6_a_bits_address = out_7_a_bits_address[20:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_6_a_bits_size = out_7_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_7_d_bits_size = {1'h0, x1_anonOut_6_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_7_d_bits_sink = _out_7_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [31:0] _requestAIO_T = {in_0_a_bits_address[31:14], in_0_a_bits_address[13:0] ^ 14'h3000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:13], in_0_a_bits_address[12:0] ^ 13'h1000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:29], in_0_a_bits_address[28:0] ^ 29'h10000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46] wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_15 = _requestAIO_T_9 | _requestAIO_T_14; // @[Xbar.scala:291:92] wire requestAIO_0_1 = _requestAIO_T_15; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_16 = {in_0_a_bits_address[31:26], in_0_a_bits_address[25:0] ^ 26'h2000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_17 = {1'h0, _requestAIO_T_16}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_18 = _requestAIO_T_17 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_19 = _requestAIO_T_18; // @[Parameters.scala:137:46] wire _requestAIO_T_20 = _requestAIO_T_19 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_2 = _requestAIO_T_20; // @[Xbar.scala:307:107] wire _portsAOI_filtered_2_valid_T = requestAIO_0_2; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_21 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_22 = {1'h0, _requestAIO_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_23 = _requestAIO_T_22 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_24 = _requestAIO_T_23; // @[Parameters.scala:137:46] wire _requestAIO_T_25 = _requestAIO_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_3 = _requestAIO_T_25; // @[Xbar.scala:307:107] wire _portsAOI_filtered_3_valid_T = requestAIO_0_3; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_27 = {1'h0, _requestAIO_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_28 = _requestAIO_T_27 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_29 = _requestAIO_T_28; // @[Parameters.scala:137:46] wire _requestAIO_T_30 = _requestAIO_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_4 = _requestAIO_T_30; // @[Xbar.scala:307:107] wire _portsAOI_filtered_4_valid_T = requestAIO_0_4; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_31 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_32 = {1'h0, _requestAIO_T_31}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_33 = _requestAIO_T_32 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_34 = _requestAIO_T_33; // @[Parameters.scala:137:46] wire _requestAIO_T_35 = _requestAIO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_5 = _requestAIO_T_35; // @[Xbar.scala:307:107] wire _portsAOI_filtered_5_valid_T = requestAIO_0_5; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_36 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_37 = {1'h0, _requestAIO_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_38 = _requestAIO_T_37 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_39 = _requestAIO_T_38; // @[Parameters.scala:137:46] wire _requestAIO_T_40 = _requestAIO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_6 = _requestAIO_T_40; // @[Xbar.scala:307:107] wire _portsAOI_filtered_6_valid_T = requestAIO_0_6; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_41 = {in_0_a_bits_address[31:21], in_0_a_bits_address[20:0] ^ 21'h100000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_42 = {1'h0, _requestAIO_T_41}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_43 = _requestAIO_T_42 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_44 = _requestAIO_T_43; // @[Parameters.scala:137:46] wire _requestAIO_T_45 = _requestAIO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_7 = _requestAIO_T_45; // @[Xbar.scala:307:107] wire _portsAOI_filtered_7_valid_T = requestAIO_0_7; // @[Xbar.scala:307:107, :355:54] wire [6:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [6:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [6:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [6:0] requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [6:0] requestDOI_uncommonBits_4 = _requestDOI_uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [6:0] requestDOI_uncommonBits_5 = _requestDOI_uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [6:0] requestDOI_uncommonBits_6 = _requestDOI_uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [6:0] requestDOI_uncommonBits_7 = _requestDOI_uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_6 = 21'h3F << out_2_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_7 = _beatsDO_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_8 = ~_beatsDO_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_2 = _beatsDO_decode_T_8[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_2 = out_2_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_2 = beatsDO_opdata_2 ? beatsDO_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_9 = 21'h3F << out_3_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_10 = _beatsDO_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_11 = ~_beatsDO_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_3 = _beatsDO_decode_T_11[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_3 = out_3_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_3 = beatsDO_opdata_3 ? beatsDO_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_12 = 21'h3F << out_4_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_13 = _beatsDO_decode_T_12[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_14 = ~_beatsDO_decode_T_13; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_4 = _beatsDO_decode_T_14[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_4 = out_4_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_4 = beatsDO_opdata_4 ? beatsDO_decode_4 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_15 = 21'h3F << out_5_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_16 = _beatsDO_decode_T_15[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_17 = ~_beatsDO_decode_T_16; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_5 = _beatsDO_decode_T_17[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_5 = out_5_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_5 = beatsDO_opdata_5 ? beatsDO_decode_5 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_18 = 21'h3F << out_6_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_19 = _beatsDO_decode_T_18[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_20 = ~_beatsDO_decode_T_19; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_6 = _beatsDO_decode_T_20[5:3]; // @[package.scala:243:46] wire [2:0] beatsDO_6 = beatsDO_decode_6; // @[Edges.scala:220:59, :221:14] wire [20:0] _beatsDO_decode_T_21 = 21'h3F << out_7_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_22 = _beatsDO_decode_T_21[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_23 = ~_beatsDO_decode_T_22; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_7 = _beatsDO_decode_T_23[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_7 = out_7_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_7 = beatsDO_opdata_7 ? beatsDO_decode_7 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_2_valid_T_1; // @[Xbar.scala:355:40] assign out_2_a_valid = portsAOI_filtered_2_valid; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_opcode = portsAOI_filtered_2_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_param = portsAOI_filtered_2_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_size = portsAOI_filtered_2_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_source = portsAOI_filtered_2_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_address = portsAOI_filtered_2_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_mask = portsAOI_filtered_2_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_data = portsAOI_filtered_2_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_2_a_bits_corrupt = portsAOI_filtered_2_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_3_valid_T_1; // @[Xbar.scala:355:40] assign out_3_a_valid = portsAOI_filtered_3_valid; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_opcode = portsAOI_filtered_3_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_param = portsAOI_filtered_3_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_size = portsAOI_filtered_3_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_source = portsAOI_filtered_3_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_address = portsAOI_filtered_3_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_mask = portsAOI_filtered_3_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_data = portsAOI_filtered_3_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_3_a_bits_corrupt = portsAOI_filtered_3_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_4_valid_T_1; // @[Xbar.scala:355:40] assign out_4_a_valid = portsAOI_filtered_4_valid; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_opcode = portsAOI_filtered_4_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_param = portsAOI_filtered_4_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_size = portsAOI_filtered_4_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_source = portsAOI_filtered_4_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_address = portsAOI_filtered_4_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_mask = portsAOI_filtered_4_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_data = portsAOI_filtered_4_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_4_a_bits_corrupt = portsAOI_filtered_4_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_5_valid_T_1; // @[Xbar.scala:355:40] assign out_5_a_valid = portsAOI_filtered_5_valid; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_opcode = portsAOI_filtered_5_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_param = portsAOI_filtered_5_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_size = portsAOI_filtered_5_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_source = portsAOI_filtered_5_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_address = portsAOI_filtered_5_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_mask = portsAOI_filtered_5_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_data = portsAOI_filtered_5_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_5_a_bits_corrupt = portsAOI_filtered_5_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_6_valid_T_1; // @[Xbar.scala:355:40] assign out_6_a_valid = portsAOI_filtered_6_valid; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_opcode = portsAOI_filtered_6_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_param = portsAOI_filtered_6_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_size = portsAOI_filtered_6_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_source = portsAOI_filtered_6_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_address = portsAOI_filtered_6_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_mask = portsAOI_filtered_6_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_data = portsAOI_filtered_6_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_6_a_bits_corrupt = portsAOI_filtered_6_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_7_valid_T_1; // @[Xbar.scala:355:40] assign out_7_a_valid = portsAOI_filtered_7_valid; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_opcode = portsAOI_filtered_7_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_param = portsAOI_filtered_7_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_size = portsAOI_filtered_7_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_source = portsAOI_filtered_7_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_address = portsAOI_filtered_7_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_mask = portsAOI_filtered_7_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_data = portsAOI_filtered_7_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_7_a_bits_corrupt = portsAOI_filtered_7_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_2_valid_T_1 = in_0_a_valid & _portsAOI_filtered_2_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_2_valid = _portsAOI_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_3_valid_T_1 = in_0_a_valid & _portsAOI_filtered_3_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_3_valid = _portsAOI_filtered_3_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_4_valid_T_1 = in_0_a_valid & _portsAOI_filtered_4_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_4_valid = _portsAOI_filtered_4_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_5_valid_T_1 = in_0_a_valid & _portsAOI_filtered_5_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_5_valid = _portsAOI_filtered_5_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_6_valid_T_1 = in_0_a_valid & _portsAOI_filtered_6_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_6_valid = _portsAOI_filtered_6_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_7_valid_T_1 = in_0_a_valid & _portsAOI_filtered_7_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_7_valid = _portsAOI_filtered_7_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = requestAIO_0_2 & portsAOI_filtered_2_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_3 = requestAIO_0_3 & portsAOI_filtered_3_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_4 = requestAIO_0_4 & portsAOI_filtered_4_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_5 = requestAIO_0_5 & portsAOI_filtered_5_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_6 = requestAIO_0_6 & portsAOI_filtered_6_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_7 = requestAIO_0_7 & portsAOI_filtered_7_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_8 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_9 = _portsAOI_in_0_a_ready_T_8 | _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_10 = _portsAOI_in_0_a_ready_T_9 | _portsAOI_in_0_a_ready_T_3; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_11 = _portsAOI_in_0_a_ready_T_10 | _portsAOI_in_0_a_ready_T_4; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_12 = _portsAOI_in_0_a_ready_T_11 | _portsAOI_in_0_a_ready_T_5; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_13 = _portsAOI_in_0_a_ready_T_12 | _portsAOI_in_0_a_ready_T_6; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_14 = _portsAOI_in_0_a_ready_T_13 | _portsAOI_in_0_a_ready_T_7; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_14; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31] assign out_2_d_ready = portsDIO_filtered_2_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_2_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_2_0_valid = _portsDIO_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31] assign out_3_d_ready = portsDIO_filtered_3_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_3_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_3_0_valid = _portsDIO_filtered_0_valid_T_7; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_4; // @[Arbiter.scala:94:31] assign out_4_d_ready = portsDIO_filtered_4_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_4_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_4_0_valid = _portsDIO_filtered_0_valid_T_9; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_5; // @[Arbiter.scala:94:31] assign out_5_d_ready = portsDIO_filtered_5_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_5_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_5_0_valid = _portsDIO_filtered_0_valid_T_11; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_6; // @[Arbiter.scala:94:31] assign out_6_d_ready = portsDIO_filtered_6_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_6_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_6_0_valid = _portsDIO_filtered_0_valid_T_13; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_7; // @[Arbiter.scala:94:31] assign out_7_d_ready = portsDIO_filtered_7_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_7_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_7_0_valid = _portsDIO_filtered_0_valid_T_15; // @[Xbar.scala:352:24, :355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] readys_lo_lo = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_lo_hi = {portsDIO_filtered_3_0_valid, portsDIO_filtered_2_0_valid}; // @[Xbar.scala:352:24] wire [3:0] readys_lo = {readys_lo_hi, readys_lo_lo}; // @[Arbiter.scala:68:51] wire [1:0] readys_hi_lo = {portsDIO_filtered_5_0_valid, portsDIO_filtered_4_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_hi = {portsDIO_filtered_7_0_valid, portsDIO_filtered_6_0_valid}; // @[Xbar.scala:352:24] wire [3:0] readys_hi = {readys_hi_hi, readys_hi_lo}; // @[Arbiter.scala:68:51] wire [7:0] _readys_T = {readys_hi, readys_lo}; // @[Arbiter.scala:68:51] wire [7:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [7:0] readys_mask; // @[Arbiter.scala:23:23] wire [7:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [7:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [15:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [14:0] _readys_unready_T = readys_filter[15:1]; // @[package.scala:262:48] wire [15:0] _readys_unready_T_1 = {readys_filter[15], readys_filter[14:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [13:0] _readys_unready_T_2 = _readys_unready_T_1[15:2]; // @[package.scala:262:{43,48}] wire [15:0] _readys_unready_T_3 = {_readys_unready_T_1[15:14], _readys_unready_T_1[13:0] | _readys_unready_T_2}; // @[package.scala:262:{43,48}] wire [11:0] _readys_unready_T_4 = _readys_unready_T_3[15:4]; // @[package.scala:262:{43,48}] wire [15:0] _readys_unready_T_5 = {_readys_unready_T_3[15:12], _readys_unready_T_3[11:0] | _readys_unready_T_4}; // @[package.scala:262:{43,48}] wire [15:0] _readys_unready_T_6 = _readys_unready_T_5; // @[package.scala:262:43, :263:17] wire [14:0] _readys_unready_T_7 = _readys_unready_T_6[15:1]; // @[package.scala:263:17] wire [15:0] _readys_unready_T_8 = {readys_mask, 8'h0}; // @[Arbiter.scala:23:23, :25:66] wire [15:0] readys_unready = {1'h0, _readys_unready_T_7} | _readys_unready_T_8; // @[Arbiter.scala:25:{52,58,66}] wire [7:0] _readys_readys_T = readys_unready[15:8]; // @[Arbiter.scala:25:58, :26:29] wire [7:0] _readys_readys_T_1 = readys_unready[7:0]; // @[Arbiter.scala:25:58, :26:48] wire [7:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [7:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [7:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [7:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [8:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [7:0] _readys_mask_T_2 = _readys_mask_T_1[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [9:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _readys_mask_T_5 = _readys_mask_T_4[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_5; // @[package.scala:253:{43,53}] wire [11:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _readys_mask_T_8 = _readys_mask_T_7[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_8; // @[package.scala:253:{43,53}] wire [7:0] _readys_mask_T_10 = _readys_mask_T_9; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}] wire _readys_T_11 = _readys_T_7[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_3 = _readys_T_11; // @[Arbiter.scala:68:{27,76}] wire _readys_T_12 = _readys_T_7[4]; // @[Arbiter.scala:30:11, :68:76] wire readys_4 = _readys_T_12; // @[Arbiter.scala:68:{27,76}] wire _readys_T_13 = _readys_T_7[5]; // @[Arbiter.scala:30:11, :68:76] wire readys_5 = _readys_T_13; // @[Arbiter.scala:68:{27,76}] wire _readys_T_14 = _readys_T_7[6]; // @[Arbiter.scala:30:11, :68:76] wire readys_6 = _readys_T_14; // @[Arbiter.scala:68:{27,76}] wire _readys_T_15 = _readys_T_7[7]; // @[Arbiter.scala:30:11, :68:76] wire readys_7 = _readys_T_15; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire _winner_T_2 = readys_2 & portsDIO_filtered_2_0_valid; // @[Xbar.scala:352:24] wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_3 & portsDIO_filtered_3_0_valid; // @[Xbar.scala:352:24] wire winner_3 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_4 & portsDIO_filtered_4_0_valid; // @[Xbar.scala:352:24] wire winner_4 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire _winner_T_5 = readys_5 & portsDIO_filtered_5_0_valid; // @[Xbar.scala:352:24] wire winner_5 = _winner_T_5; // @[Arbiter.scala:71:{27,69}] wire _winner_T_6 = readys_6 & portsDIO_filtered_6_0_valid; // @[Xbar.scala:352:24] wire winner_6 = _winner_T_6; // @[Arbiter.scala:71:{27,69}] wire _winner_T_7 = readys_7 & portsDIO_filtered_7_0_valid; // @[Xbar.scala:352:24] wire winner_7 = _winner_T_7; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3 = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_4 = prefixOR_3 | winner_3; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_5 = prefixOR_4 | winner_4; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_6 = prefixOR_5 | winner_5; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_7 = prefixOR_6 | winner_6; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_7 | winner_7; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_79 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<15>(0h4000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_38, _T_43) node _T_85 = or(_T_84, _T_48) node _T_86 = or(_T_85, _T_53) node _T_87 = or(_T_86, _T_58) node _T_88 = or(_T_87, _T_63) node _T_89 = or(_T_88, _T_68) node _T_90 = or(_T_89, _T_73) node _T_91 = or(_T_90, _T_78) node _T_92 = or(_T_91, _T_83) node _T_93 = and(_T_33, _T_92) node _T_94 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<29>(0h10000000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = or(_T_100, _T_105) node _T_107 = and(_T_95, _T_106) node _T_108 = or(UInt<1>(0h0), _T_93) node _T_109 = or(_T_108, _T_107) node _T_110 = and(_T_32, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_110, UInt<1>(0h1), "") : assert_2 node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_115 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_114 connect _WIRE[1], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = or(_T_117, _T_118) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_119 node _T_120 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_121 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_122 = and(_T_120, _T_121) node _T_123 = or(UInt<1>(0h0), _T_122) node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_125 = cvt(_T_124) node _T_126 = and(_T_125, asSInt(UInt<14>(0h2000))) node _T_127 = asSInt(_T_126) node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0))) node _T_129 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<17>(0h10000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<15>(0h4000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<18>(0h2f000))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<17>(0h10000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<17>(0h10000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<27>(0h4000000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<13>(0h1000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<29>(0h10000000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = or(_T_128, _T_133) node _T_185 = or(_T_184, _T_138) node _T_186 = or(_T_185, _T_143) node _T_187 = or(_T_186, _T_148) node _T_188 = or(_T_187, _T_153) node _T_189 = or(_T_188, _T_158) node _T_190 = or(_T_189, _T_163) node _T_191 = or(_T_190, _T_168) node _T_192 = or(_T_191, _T_173) node _T_193 = or(_T_192, _T_178) node _T_194 = or(_T_193, _T_183) node _T_195 = and(_T_123, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = and(_WIRE_1, _T_196) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_197, UInt<1>(0h1), "") : assert_3 node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(source_ok, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_204 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_204, UInt<1>(0h1), "") : assert_5 node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(is_aligned, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_211 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_211, UInt<1>(0h1), "") : assert_7 node _T_215 = not(io.in.a.bits.mask) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_216, UInt<1>(0h1), "") : assert_8 node _T_220 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_220, UInt<1>(0h1), "") : assert_9 node _T_224 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_224 : node _T_225 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_226 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_229 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_230 = or(_T_228, _T_229) node _T_231 = and(_T_227, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_245 = cvt(_T_244) node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000))) node _T_247 = asSInt(_T_246) node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0))) node _T_249 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<15>(0h4000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<13>(0h1000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<18>(0h2f000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<17>(0h10000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<27>(0h4000000))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<13>(0h1000))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_238, _T_243) node _T_285 = or(_T_284, _T_248) node _T_286 = or(_T_285, _T_253) node _T_287 = or(_T_286, _T_258) node _T_288 = or(_T_287, _T_263) node _T_289 = or(_T_288, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = and(_T_233, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_232, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _T_314 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_314 connect _WIRE_2[1], _T_315 node _T_316 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_317 = mux(_WIRE_2[0], _T_316, UInt<1>(0h0)) node _T_318 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = or(_T_317, _T_318) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_319 node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<14>(0h2000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<13>(0h1000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<15>(0h4000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<18>(0h2f000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = or(_T_328, _T_333) node _T_385 = or(_T_384, _T_338) node _T_386 = or(_T_385, _T_343) node _T_387 = or(_T_386, _T_348) node _T_388 = or(_T_387, _T_353) node _T_389 = or(_T_388, _T_358) node _T_390 = or(_T_389, _T_363) node _T_391 = or(_T_390, _T_368) node _T_392 = or(_T_391, _T_373) node _T_393 = or(_T_392, _T_378) node _T_394 = or(_T_393, _T_383) node _T_395 = and(_T_323, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = and(_WIRE_3, _T_396) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_397, UInt<1>(0h1), "") : assert_11 node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(source_ok, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_404 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_404, UInt<1>(0h1), "") : assert_13 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(is_aligned, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_411 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_411, UInt<1>(0h1), "") : assert_15 node _T_415 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_415, UInt<1>(0h1), "") : assert_16 node _T_419 = not(io.in.a.bits.mask) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_420, UInt<1>(0h1), "") : assert_17 node _T_424 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_424, UInt<1>(0h1), "") : assert_18 node _T_428 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_428 : node _T_429 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_430 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_433 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_434 = or(_T_432, _T_433) node _T_435 = and(_T_431, _T_434) node _T_436 = or(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_436, UInt<1>(0h1), "") : assert_19 node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_442 = and(_T_440, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = and(_T_443, _T_448) node _T_450 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_451 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_452 = and(_T_450, _T_451) node _T_453 = or(UInt<1>(0h0), _T_452) node _T_454 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<14>(0h2000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<18>(0h2f000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<13>(0h1000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_480 = cvt(_T_479) node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000))) node _T_482 = asSInt(_T_481) node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) node _T_484 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_485 = cvt(_T_484) node _T_486 = and(_T_485, asSInt(UInt<27>(0h4000000))) node _T_487 = asSInt(_T_486) node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) node _T_489 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<13>(0h1000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<29>(0h10000000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = or(_T_458, _T_463) node _T_500 = or(_T_499, _T_468) node _T_501 = or(_T_500, _T_473) node _T_502 = or(_T_501, _T_478) node _T_503 = or(_T_502, _T_483) node _T_504 = or(_T_503, _T_488) node _T_505 = or(_T_504, _T_493) node _T_506 = or(_T_505, _T_498) node _T_507 = and(_T_453, _T_506) node _T_508 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_509 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_510 = and(_T_508, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<15>(0h4000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = or(_T_516, _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = or(UInt<1>(0h0), _T_449) node _T_525 = or(_T_524, _T_507) node _T_526 = or(_T_525, _T_523) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_526, UInt<1>(0h1), "") : assert_20 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_536 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_536, UInt<1>(0h1), "") : assert_23 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_540, UInt<1>(0h1), "") : assert_24 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_544, UInt<1>(0h1), "") : assert_25 node _T_548 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_553 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_554 = or(_T_552, _T_553) node _T_555 = and(_T_551, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_558 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = and(_T_560, _T_565) node _T_567 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_568 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_569 = and(_T_567, _T_568) node _T_570 = or(UInt<1>(0h0), _T_569) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<14>(0h2000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<18>(0h2f000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<17>(0h10000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<17>(0h10000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<27>(0h4000000))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_602 = cvt(_T_601) node _T_603 = and(_T_602, asSInt(UInt<13>(0h1000))) node _T_604 = asSInt(_T_603) node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0))) node _T_606 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_607 = cvt(_T_606) node _T_608 = and(_T_607, asSInt(UInt<29>(0h10000000))) node _T_609 = asSInt(_T_608) node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0))) node _T_611 = or(_T_575, _T_580) node _T_612 = or(_T_611, _T_585) node _T_613 = or(_T_612, _T_590) node _T_614 = or(_T_613, _T_595) node _T_615 = or(_T_614, _T_600) node _T_616 = or(_T_615, _T_605) node _T_617 = or(_T_616, _T_610) node _T_618 = and(_T_570, _T_617) node _T_619 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_620 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<15>(0h4000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = or(_T_634, _T_639) node _T_641 = and(_T_629, _T_640) node _T_642 = or(UInt<1>(0h0), _T_566) node _T_643 = or(_T_642, _T_618) node _T_644 = or(_T_643, _T_625) node _T_645 = or(_T_644, _T_641) node _T_646 = and(_T_556, _T_645) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_646, UInt<1>(0h1), "") : assert_26 node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(source_ok, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(is_aligned, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_656 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_657 = asUInt(reset) node _T_658 = eq(_T_657, UInt<1>(0h0)) when _T_658 : node _T_659 = eq(_T_656, UInt<1>(0h0)) when _T_659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_656, UInt<1>(0h1), "") : assert_29 node _T_660 = eq(io.in.a.bits.mask, mask) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_660, UInt<1>(0h1), "") : assert_30 node _T_664 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_664 : node _T_665 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_666 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_667 = and(_T_665, _T_666) node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_669 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_670 = or(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_674 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_675 = and(_T_673, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<13>(0h1000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_685 = and(_T_683, _T_684) node _T_686 = or(UInt<1>(0h0), _T_685) node _T_687 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_688 = cvt(_T_687) node _T_689 = and(_T_688, asSInt(UInt<14>(0h2000))) node _T_690 = asSInt(_T_689) node _T_691 = eq(_T_690, asSInt(UInt<1>(0h0))) node _T_692 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<18>(0h2f000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<17>(0h10000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_703 = cvt(_T_702) node _T_704 = and(_T_703, asSInt(UInt<13>(0h1000))) node _T_705 = asSInt(_T_704) node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0))) node _T_707 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<27>(0h4000000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_718 = cvt(_T_717) node _T_719 = and(_T_718, asSInt(UInt<13>(0h1000))) node _T_720 = asSInt(_T_719) node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0))) node _T_722 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_723 = cvt(_T_722) node _T_724 = and(_T_723, asSInt(UInt<29>(0h10000000))) node _T_725 = asSInt(_T_724) node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0))) node _T_727 = or(_T_691, _T_696) node _T_728 = or(_T_727, _T_701) node _T_729 = or(_T_728, _T_706) node _T_730 = or(_T_729, _T_711) node _T_731 = or(_T_730, _T_716) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_726) node _T_734 = and(_T_686, _T_733) node _T_735 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_736 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = and(_T_735, _T_740) node _T_742 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_743 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_744 = and(_T_742, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_750, _T_755) node _T_757 = and(_T_745, _T_756) node _T_758 = or(UInt<1>(0h0), _T_682) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_757) node _T_762 = and(_T_672, _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_762, UInt<1>(0h1), "") : assert_31 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(source_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(is_aligned, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_772 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_772, UInt<1>(0h1), "") : assert_34 node _T_776 = not(mask) node _T_777 = and(io.in.a.bits.mask, _T_776) node _T_778 = eq(_T_777, UInt<1>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_778, UInt<1>(0h1), "") : assert_35 node _T_782 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_782 : node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_785 = and(_T_783, _T_784) node _T_786 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_787 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_788 = or(_T_786, _T_787) node _T_789 = and(_T_785, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<15>(0h4000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<18>(0h2f000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<29>(0h10000000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = or(_T_799, _T_804) node _T_851 = or(_T_850, _T_809) node _T_852 = or(_T_851, _T_814) node _T_853 = or(_T_852, _T_819) node _T_854 = or(_T_853, _T_824) node _T_855 = or(_T_854, _T_829) node _T_856 = or(_T_855, _T_834) node _T_857 = or(_T_856, _T_839) node _T_858 = or(_T_857, _T_844) node _T_859 = or(_T_858, _T_849) node _T_860 = and(_T_794, _T_859) node _T_861 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_862 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<17>(0h10000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = and(_T_861, _T_866) node _T_868 = or(UInt<1>(0h0), _T_860) node _T_869 = or(_T_868, _T_867) node _T_870 = and(_T_790, _T_869) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_870, UInt<1>(0h1), "") : assert_36 node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(source_ok, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(is_aligned, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_880 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_880, UInt<1>(0h1), "") : assert_39 node _T_884 = eq(io.in.a.bits.mask, mask) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_884, UInt<1>(0h1), "") : assert_40 node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_888 : node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_893 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_894 = or(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<14>(0h2000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<15>(0h4000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<13>(0h1000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<18>(0h2f000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_927 = cvt(_T_926) node _T_928 = and(_T_927, asSInt(UInt<17>(0h10000))) node _T_929 = asSInt(_T_928) node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0))) node _T_931 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_932 = cvt(_T_931) node _T_933 = and(_T_932, asSInt(UInt<13>(0h1000))) node _T_934 = asSInt(_T_933) node _T_935 = eq(_T_934, asSInt(UInt<1>(0h0))) node _T_936 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<17>(0h10000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_942 = cvt(_T_941) node _T_943 = and(_T_942, asSInt(UInt<27>(0h4000000))) node _T_944 = asSInt(_T_943) node _T_945 = eq(_T_944, asSInt(UInt<1>(0h0))) node _T_946 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<13>(0h1000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<29>(0h10000000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = or(_T_905, _T_910) node _T_957 = or(_T_956, _T_915) node _T_958 = or(_T_957, _T_920) node _T_959 = or(_T_958, _T_925) node _T_960 = or(_T_959, _T_930) node _T_961 = or(_T_960, _T_935) node _T_962 = or(_T_961, _T_940) node _T_963 = or(_T_962, _T_945) node _T_964 = or(_T_963, _T_950) node _T_965 = or(_T_964, _T_955) node _T_966 = and(_T_900, _T_965) node _T_967 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_968 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = and(_T_967, _T_972) node _T_974 = or(UInt<1>(0h0), _T_966) node _T_975 = or(_T_974, _T_973) node _T_976 = and(_T_896, _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_976, UInt<1>(0h1), "") : assert_41 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(is_aligned, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_986 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_986, UInt<1>(0h1), "") : assert_44 node _T_990 = eq(io.in.a.bits.mask, mask) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_990, UInt<1>(0h1), "") : assert_45 node _T_994 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_994 : node _T_995 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_996 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_997 = and(_T_995, _T_996) node _T_998 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_999 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_1000 = or(_T_998, _T_999) node _T_1001 = and(_T_997, _T_1000) node _T_1002 = or(UInt<1>(0h0), _T_1001) node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1004 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = and(_T_1006, _T_1011) node _T_1013 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1014 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<14>(0h2000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<17>(0h10000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<15>(0h4000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<13>(0h1000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<18>(0h2f000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<13>(0h1000))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<27>(0h4000000))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1055 = cvt(_T_1054) node _T_1056 = and(_T_1055, asSInt(UInt<13>(0h1000))) node _T_1057 = asSInt(_T_1056) node _T_1058 = eq(_T_1057, asSInt(UInt<1>(0h0))) node _T_1059 = or(_T_1018, _T_1023) node _T_1060 = or(_T_1059, _T_1028) node _T_1061 = or(_T_1060, _T_1033) node _T_1062 = or(_T_1061, _T_1038) node _T_1063 = or(_T_1062, _T_1043) node _T_1064 = or(_T_1063, _T_1048) node _T_1065 = or(_T_1064, _T_1053) node _T_1066 = or(_T_1065, _T_1058) node _T_1067 = and(_T_1013, _T_1066) node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = or(UInt<1>(0h0), _T_1070) node _T_1072 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1073 = cvt(_T_1072) node _T_1074 = and(_T_1073, asSInt(UInt<17>(0h10000))) node _T_1075 = asSInt(_T_1074) node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0))) node _T_1077 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<29>(0h10000000))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = or(_T_1076, _T_1081) node _T_1083 = and(_T_1071, _T_1082) node _T_1084 = or(UInt<1>(0h0), _T_1012) node _T_1085 = or(_T_1084, _T_1067) node _T_1086 = or(_T_1085, _T_1083) node _T_1087 = and(_T_1002, _T_1086) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_46 node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(is_aligned, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1097 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_49 node _T_1101 = eq(io.in.a.bits.mask, mask) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_50 node _T_1105 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1109 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1113 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok_1, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_54 node _T_1121 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_55 node _T_1125 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_56 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_57 node _T_1133 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1133 : node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(source_ok_1, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(sink_ok, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1140 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_60 node _T_1144 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_61 node _T_1148 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_62 node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_63 node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1157 = or(UInt<1>(0h1), _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_64 node _T_1161 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1161 : node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(source_ok_1, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(sink_ok, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1168 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_67 node _T_1172 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_68 node _T_1176 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_69 node _T_1180 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1181 = or(_T_1180, io.in.d.bits.corrupt) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_70 node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1186 = or(UInt<1>(0h1), _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_71 node _T_1190 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1190 : node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(source_ok_1, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1194 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_73 node _T_1198 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_74 node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1203 = or(UInt<1>(0h1), _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_75 node _T_1207 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1207 : node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(source_ok_1, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1211 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_77 node _T_1215 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1216 = or(_T_1215, io.in.d.bits.corrupt) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_78 node _T_1220 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1221 = or(UInt<1>(0h1), _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_79 node _T_1225 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1225 : node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(source_ok_1, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_81 node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_82 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1242 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_84 node _T_1246 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = or(_T_1247, _T_1252) node _T_1254 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) node _T_1256 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1257 = cvt(_T_1256) node _T_1258 = and(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = asSInt(_T_1258) node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = or(_T_1255, _T_1260) node _T_1262 = and(_T_1253, _T_1261) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<18>(0h21000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<18>(0h22000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<13>(0h1000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<18>(0h23000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<13>(0h1000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<13>(0h1000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h10000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<13>(0h1000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_66 = cvt(_address_ok_T_65) node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<17>(0h10000))) node _address_ok_T_68 = asSInt(_address_ok_T_67) node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0))) node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<27>(0h4000000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h10000000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[17] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 connect _address_ok_WIRE[13], _address_ok_T_69 connect _address_ok_WIRE[14], _address_ok_T_74 connect _address_ok_WIRE[15], _address_ok_T_79 connect _address_ok_WIRE[16], _address_ok_T_84 node _address_ok_T_85 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_86 = or(_address_ok_T_85, _address_ok_WIRE[2]) node _address_ok_T_87 = or(_address_ok_T_86, _address_ok_WIRE[3]) node _address_ok_T_88 = or(_address_ok_T_87, _address_ok_WIRE[4]) node _address_ok_T_89 = or(_address_ok_T_88, _address_ok_WIRE[5]) node _address_ok_T_90 = or(_address_ok_T_89, _address_ok_WIRE[6]) node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[7]) node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[8]) node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[9]) node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[10]) node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[11]) node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[12]) node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[13]) node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[14]) node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[15]) node address_ok = or(_address_ok_T_99, _address_ok_WIRE[16]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1266 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1266 : node _T_1267 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1268 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1267 connect _WIRE_4[1], _T_1268 node _T_1269 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1270 = mux(_WIRE_4[0], _T_1269, UInt<1>(0h0)) node _T_1271 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1272 = or(_T_1270, _T_1271) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1272 node _T_1273 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1274 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = or(UInt<1>(0h0), _T_1275) node _T_1277 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1278 = cvt(_T_1277) node _T_1279 = and(_T_1278, asSInt(UInt<14>(0h2000))) node _T_1280 = asSInt(_T_1279) node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0))) node _T_1282 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1288 = cvt(_T_1287) node _T_1289 = and(_T_1288, asSInt(UInt<17>(0h10000))) node _T_1290 = asSInt(_T_1289) node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0))) node _T_1292 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1293 = cvt(_T_1292) node _T_1294 = and(_T_1293, asSInt(UInt<15>(0h4000))) node _T_1295 = asSInt(_T_1294) node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0))) node _T_1297 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<18>(0h2f000))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1308 = cvt(_T_1307) node _T_1309 = and(_T_1308, asSInt(UInt<17>(0h10000))) node _T_1310 = asSInt(_T_1309) node _T_1311 = eq(_T_1310, asSInt(UInt<1>(0h0))) node _T_1312 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1313 = cvt(_T_1312) node _T_1314 = and(_T_1313, asSInt(UInt<13>(0h1000))) node _T_1315 = asSInt(_T_1314) node _T_1316 = eq(_T_1315, asSInt(UInt<1>(0h0))) node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1318 = cvt(_T_1317) node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000))) node _T_1320 = asSInt(_T_1319) node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0))) node _T_1322 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1323 = cvt(_T_1322) node _T_1324 = and(_T_1323, asSInt(UInt<27>(0h4000000))) node _T_1325 = asSInt(_T_1324) node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0))) node _T_1327 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<29>(0h10000000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = or(_T_1281, _T_1286) node _T_1338 = or(_T_1337, _T_1291) node _T_1339 = or(_T_1338, _T_1296) node _T_1340 = or(_T_1339, _T_1301) node _T_1341 = or(_T_1340, _T_1306) node _T_1342 = or(_T_1341, _T_1311) node _T_1343 = or(_T_1342, _T_1316) node _T_1344 = or(_T_1343, _T_1321) node _T_1345 = or(_T_1344, _T_1326) node _T_1346 = or(_T_1345, _T_1331) node _T_1347 = or(_T_1346, _T_1336) node _T_1348 = and(_T_1276, _T_1347) node _T_1349 = or(UInt<1>(0h0), _T_1348) node _T_1350 = and(_WIRE_5, _T_1349) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_86 node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(address_ok, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(legal_source, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1363 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_90 node _T_1367 = eq(io.in.b.bits.mask, mask_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_91 node _T_1371 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_92 node _T_1375 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1375 : node _T_1376 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1377 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = or(UInt<1>(0h0), _T_1378) node _T_1380 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<14>(0h2000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1391 = cvt(_T_1390) node _T_1392 = and(_T_1391, asSInt(UInt<17>(0h10000))) node _T_1393 = asSInt(_T_1392) node _T_1394 = eq(_T_1393, asSInt(UInt<1>(0h0))) node _T_1395 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1396 = cvt(_T_1395) node _T_1397 = and(_T_1396, asSInt(UInt<15>(0h4000))) node _T_1398 = asSInt(_T_1397) node _T_1399 = eq(_T_1398, asSInt(UInt<1>(0h0))) node _T_1400 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1401 = cvt(_T_1400) node _T_1402 = and(_T_1401, asSInt(UInt<13>(0h1000))) node _T_1403 = asSInt(_T_1402) node _T_1404 = eq(_T_1403, asSInt(UInt<1>(0h0))) node _T_1405 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1406 = cvt(_T_1405) node _T_1407 = and(_T_1406, asSInt(UInt<18>(0h2f000))) node _T_1408 = asSInt(_T_1407) node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0))) node _T_1410 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1411 = cvt(_T_1410) node _T_1412 = and(_T_1411, asSInt(UInt<17>(0h10000))) node _T_1413 = asSInt(_T_1412) node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0))) node _T_1415 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1416 = cvt(_T_1415) node _T_1417 = and(_T_1416, asSInt(UInt<13>(0h1000))) node _T_1418 = asSInt(_T_1417) node _T_1419 = eq(_T_1418, asSInt(UInt<1>(0h0))) node _T_1420 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1421 = cvt(_T_1420) node _T_1422 = and(_T_1421, asSInt(UInt<17>(0h10000))) node _T_1423 = asSInt(_T_1422) node _T_1424 = eq(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1426 = cvt(_T_1425) node _T_1427 = and(_T_1426, asSInt(UInt<27>(0h4000000))) node _T_1428 = asSInt(_T_1427) node _T_1429 = eq(_T_1428, asSInt(UInt<1>(0h0))) node _T_1430 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1431 = cvt(_T_1430) node _T_1432 = and(_T_1431, asSInt(UInt<13>(0h1000))) node _T_1433 = asSInt(_T_1432) node _T_1434 = eq(_T_1433, asSInt(UInt<1>(0h0))) node _T_1435 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<29>(0h10000000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1384, _T_1389) node _T_1441 = or(_T_1440, _T_1394) node _T_1442 = or(_T_1441, _T_1399) node _T_1443 = or(_T_1442, _T_1404) node _T_1444 = or(_T_1443, _T_1409) node _T_1445 = or(_T_1444, _T_1414) node _T_1446 = or(_T_1445, _T_1419) node _T_1447 = or(_T_1446, _T_1424) node _T_1448 = or(_T_1447, _T_1429) node _T_1449 = or(_T_1448, _T_1434) node _T_1450 = or(_T_1449, _T_1439) node _T_1451 = and(_T_1379, _T_1450) node _T_1452 = or(UInt<1>(0h0), _T_1451) node _T_1453 = and(UInt<1>(0h0), _T_1452) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_93 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(address_ok, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(legal_source, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1466 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_97 node _T_1470 = eq(io.in.b.bits.mask, mask_1) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_98 node _T_1474 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_99 node _T_1478 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1478 : node _T_1479 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1480 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = or(UInt<1>(0h0), _T_1481) node _T_1483 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1484 = cvt(_T_1483) node _T_1485 = and(_T_1484, asSInt(UInt<14>(0h2000))) node _T_1486 = asSInt(_T_1485) node _T_1487 = eq(_T_1486, asSInt(UInt<1>(0h0))) node _T_1488 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1489 = cvt(_T_1488) node _T_1490 = and(_T_1489, asSInt(UInt<13>(0h1000))) node _T_1491 = asSInt(_T_1490) node _T_1492 = eq(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1494 = cvt(_T_1493) node _T_1495 = and(_T_1494, asSInt(UInt<17>(0h10000))) node _T_1496 = asSInt(_T_1495) node _T_1497 = eq(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<15>(0h4000))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1504 = cvt(_T_1503) node _T_1505 = and(_T_1504, asSInt(UInt<13>(0h1000))) node _T_1506 = asSInt(_T_1505) node _T_1507 = eq(_T_1506, asSInt(UInt<1>(0h0))) node _T_1508 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<18>(0h2f000))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1514 = cvt(_T_1513) node _T_1515 = and(_T_1514, asSInt(UInt<17>(0h10000))) node _T_1516 = asSInt(_T_1515) node _T_1517 = eq(_T_1516, asSInt(UInt<1>(0h0))) node _T_1518 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1519 = cvt(_T_1518) node _T_1520 = and(_T_1519, asSInt(UInt<13>(0h1000))) node _T_1521 = asSInt(_T_1520) node _T_1522 = eq(_T_1521, asSInt(UInt<1>(0h0))) node _T_1523 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1524 = cvt(_T_1523) node _T_1525 = and(_T_1524, asSInt(UInt<17>(0h10000))) node _T_1526 = asSInt(_T_1525) node _T_1527 = eq(_T_1526, asSInt(UInt<1>(0h0))) node _T_1528 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1529 = cvt(_T_1528) node _T_1530 = and(_T_1529, asSInt(UInt<27>(0h4000000))) node _T_1531 = asSInt(_T_1530) node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1534 = cvt(_T_1533) node _T_1535 = and(_T_1534, asSInt(UInt<13>(0h1000))) node _T_1536 = asSInt(_T_1535) node _T_1537 = eq(_T_1536, asSInt(UInt<1>(0h0))) node _T_1538 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<29>(0h10000000))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1487, _T_1492) node _T_1544 = or(_T_1543, _T_1497) node _T_1545 = or(_T_1544, _T_1502) node _T_1546 = or(_T_1545, _T_1507) node _T_1547 = or(_T_1546, _T_1512) node _T_1548 = or(_T_1547, _T_1517) node _T_1549 = or(_T_1548, _T_1522) node _T_1550 = or(_T_1549, _T_1527) node _T_1551 = or(_T_1550, _T_1532) node _T_1552 = or(_T_1551, _T_1537) node _T_1553 = or(_T_1552, _T_1542) node _T_1554 = and(_T_1482, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = and(UInt<1>(0h0), _T_1555) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_100 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(address_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(legal_source, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1569 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_104 node _T_1573 = eq(io.in.b.bits.mask, mask_1) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_105 node _T_1577 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1577 : node _T_1578 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1579 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1580 = and(_T_1578, _T_1579) node _T_1581 = or(UInt<1>(0h0), _T_1580) node _T_1582 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1583 = cvt(_T_1582) node _T_1584 = and(_T_1583, asSInt(UInt<14>(0h2000))) node _T_1585 = asSInt(_T_1584) node _T_1586 = eq(_T_1585, asSInt(UInt<1>(0h0))) node _T_1587 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<13>(0h1000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<17>(0h10000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<15>(0h4000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<18>(0h2f000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<17>(0h10000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<13>(0h1000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<17>(0h10000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<27>(0h4000000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<29>(0h10000000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = or(_T_1586, _T_1591) node _T_1643 = or(_T_1642, _T_1596) node _T_1644 = or(_T_1643, _T_1601) node _T_1645 = or(_T_1644, _T_1606) node _T_1646 = or(_T_1645, _T_1611) node _T_1647 = or(_T_1646, _T_1616) node _T_1648 = or(_T_1647, _T_1621) node _T_1649 = or(_T_1648, _T_1626) node _T_1650 = or(_T_1649, _T_1631) node _T_1651 = or(_T_1650, _T_1636) node _T_1652 = or(_T_1651, _T_1641) node _T_1653 = and(_T_1581, _T_1652) node _T_1654 = or(UInt<1>(0h0), _T_1653) node _T_1655 = and(UInt<1>(0h0), _T_1654) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_106 node _T_1659 = asUInt(reset) node _T_1660 = eq(_T_1659, UInt<1>(0h0)) when _T_1660 : node _T_1661 = eq(address_ok, UInt<1>(0h0)) when _T_1661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(legal_source, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1668 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_110 node _T_1672 = not(mask_1) node _T_1673 = and(io.in.b.bits.mask, _T_1672) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_111 node _T_1678 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1678 : node _T_1679 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1680 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = or(UInt<1>(0h0), _T_1681) node _T_1683 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1684 = cvt(_T_1683) node _T_1685 = and(_T_1684, asSInt(UInt<14>(0h2000))) node _T_1686 = asSInt(_T_1685) node _T_1687 = eq(_T_1686, asSInt(UInt<1>(0h0))) node _T_1688 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1689 = cvt(_T_1688) node _T_1690 = and(_T_1689, asSInt(UInt<13>(0h1000))) node _T_1691 = asSInt(_T_1690) node _T_1692 = eq(_T_1691, asSInt(UInt<1>(0h0))) node _T_1693 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<17>(0h10000))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1699 = cvt(_T_1698) node _T_1700 = and(_T_1699, asSInt(UInt<15>(0h4000))) node _T_1701 = asSInt(_T_1700) node _T_1702 = eq(_T_1701, asSInt(UInt<1>(0h0))) node _T_1703 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1704 = cvt(_T_1703) node _T_1705 = and(_T_1704, asSInt(UInt<13>(0h1000))) node _T_1706 = asSInt(_T_1705) node _T_1707 = eq(_T_1706, asSInt(UInt<1>(0h0))) node _T_1708 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1709 = cvt(_T_1708) node _T_1710 = and(_T_1709, asSInt(UInt<18>(0h2f000))) node _T_1711 = asSInt(_T_1710) node _T_1712 = eq(_T_1711, asSInt(UInt<1>(0h0))) node _T_1713 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1714 = cvt(_T_1713) node _T_1715 = and(_T_1714, asSInt(UInt<17>(0h10000))) node _T_1716 = asSInt(_T_1715) node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0))) node _T_1718 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1719 = cvt(_T_1718) node _T_1720 = and(_T_1719, asSInt(UInt<13>(0h1000))) node _T_1721 = asSInt(_T_1720) node _T_1722 = eq(_T_1721, asSInt(UInt<1>(0h0))) node _T_1723 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1724 = cvt(_T_1723) node _T_1725 = and(_T_1724, asSInt(UInt<17>(0h10000))) node _T_1726 = asSInt(_T_1725) node _T_1727 = eq(_T_1726, asSInt(UInt<1>(0h0))) node _T_1728 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1729 = cvt(_T_1728) node _T_1730 = and(_T_1729, asSInt(UInt<27>(0h4000000))) node _T_1731 = asSInt(_T_1730) node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1734 = cvt(_T_1733) node _T_1735 = and(_T_1734, asSInt(UInt<13>(0h1000))) node _T_1736 = asSInt(_T_1735) node _T_1737 = eq(_T_1736, asSInt(UInt<1>(0h0))) node _T_1738 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<29>(0h10000000))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1687, _T_1692) node _T_1744 = or(_T_1743, _T_1697) node _T_1745 = or(_T_1744, _T_1702) node _T_1746 = or(_T_1745, _T_1707) node _T_1747 = or(_T_1746, _T_1712) node _T_1748 = or(_T_1747, _T_1717) node _T_1749 = or(_T_1748, _T_1722) node _T_1750 = or(_T_1749, _T_1727) node _T_1751 = or(_T_1750, _T_1732) node _T_1752 = or(_T_1751, _T_1737) node _T_1753 = or(_T_1752, _T_1742) node _T_1754 = and(_T_1682, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_112 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_116 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_117 node _T_1777 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<15>(0h4000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<13>(0h1000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1786, _T_1791) node _T_1843 = or(_T_1842, _T_1796) node _T_1844 = or(_T_1843, _T_1801) node _T_1845 = or(_T_1844, _T_1806) node _T_1846 = or(_T_1845, _T_1811) node _T_1847 = or(_T_1846, _T_1816) node _T_1848 = or(_T_1847, _T_1821) node _T_1849 = or(_T_1848, _T_1826) node _T_1850 = or(_T_1849, _T_1831) node _T_1851 = or(_T_1850, _T_1836) node _T_1852 = or(_T_1851, _T_1841) node _T_1853 = and(_T_1781, _T_1852) node _T_1854 = or(UInt<1>(0h0), _T_1853) node _T_1855 = and(UInt<1>(0h0), _T_1854) node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(_T_1855, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1855, UInt<1>(0h1), "") : assert_118 node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(address_ok, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(legal_source, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1868 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_122 node _T_1872 = eq(io.in.b.bits.mask, mask_1) node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(_T_1872, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1872, UInt<1>(0h1), "") : assert_123 node _T_1876 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1876 : node _T_1877 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1878 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1879 = and(_T_1877, _T_1878) node _T_1880 = or(UInt<1>(0h0), _T_1879) node _T_1881 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1882 = cvt(_T_1881) node _T_1883 = and(_T_1882, asSInt(UInt<14>(0h2000))) node _T_1884 = asSInt(_T_1883) node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1887 = cvt(_T_1886) node _T_1888 = and(_T_1887, asSInt(UInt<13>(0h1000))) node _T_1889 = asSInt(_T_1888) node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0))) node _T_1891 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<17>(0h10000))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1897 = cvt(_T_1896) node _T_1898 = and(_T_1897, asSInt(UInt<15>(0h4000))) node _T_1899 = asSInt(_T_1898) node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1907 = cvt(_T_1906) node _T_1908 = and(_T_1907, asSInt(UInt<18>(0h2f000))) node _T_1909 = asSInt(_T_1908) node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0))) node _T_1911 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1912 = cvt(_T_1911) node _T_1913 = and(_T_1912, asSInt(UInt<17>(0h10000))) node _T_1914 = asSInt(_T_1913) node _T_1915 = eq(_T_1914, asSInt(UInt<1>(0h0))) node _T_1916 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1917 = cvt(_T_1916) node _T_1918 = and(_T_1917, asSInt(UInt<13>(0h1000))) node _T_1919 = asSInt(_T_1918) node _T_1920 = eq(_T_1919, asSInt(UInt<1>(0h0))) node _T_1921 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1922 = cvt(_T_1921) node _T_1923 = and(_T_1922, asSInt(UInt<17>(0h10000))) node _T_1924 = asSInt(_T_1923) node _T_1925 = eq(_T_1924, asSInt(UInt<1>(0h0))) node _T_1926 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1927 = cvt(_T_1926) node _T_1928 = and(_T_1927, asSInt(UInt<27>(0h4000000))) node _T_1929 = asSInt(_T_1928) node _T_1930 = eq(_T_1929, asSInt(UInt<1>(0h0))) node _T_1931 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<13>(0h1000))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h10000000))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1885, _T_1890) node _T_1942 = or(_T_1941, _T_1895) node _T_1943 = or(_T_1942, _T_1900) node _T_1944 = or(_T_1943, _T_1905) node _T_1945 = or(_T_1944, _T_1910) node _T_1946 = or(_T_1945, _T_1915) node _T_1947 = or(_T_1946, _T_1920) node _T_1948 = or(_T_1947, _T_1925) node _T_1949 = or(_T_1948, _T_1930) node _T_1950 = or(_T_1949, _T_1935) node _T_1951 = or(_T_1950, _T_1940) node _T_1952 = and(_T_1880, _T_1951) node _T_1953 = or(UInt<1>(0h0), _T_1952) node _T_1954 = and(UInt<1>(0h0), _T_1953) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_124 node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(address_ok, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(legal_source, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1964 = asUInt(reset) node _T_1965 = eq(_T_1964, UInt<1>(0h0)) when _T_1965 : node _T_1966 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1967 = eq(io.in.b.bits.mask, mask_1) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_128 node _T_1971 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1972 = asUInt(reset) node _T_1973 = eq(_T_1972, UInt<1>(0h0)) when _T_1973 : node _T_1974 = eq(_T_1971, UInt<1>(0h0)) when _T_1974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1971, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1975 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<13>(0h1000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<13>(0h1000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<17>(0h10000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<18>(0h21000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<13>(0h1000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) node _address_ok_T_130 = xor(io.in.c.bits.address, UInt<18>(0h22000)) node _address_ok_T_131 = cvt(_address_ok_T_130) node _address_ok_T_132 = and(_address_ok_T_131, asSInt(UInt<13>(0h1000))) node _address_ok_T_133 = asSInt(_address_ok_T_132) node _address_ok_T_134 = eq(_address_ok_T_133, asSInt(UInt<1>(0h0))) node _address_ok_T_135 = xor(io.in.c.bits.address, UInt<18>(0h23000)) node _address_ok_T_136 = cvt(_address_ok_T_135) node _address_ok_T_137 = and(_address_ok_T_136, asSInt(UInt<13>(0h1000))) node _address_ok_T_138 = asSInt(_address_ok_T_137) node _address_ok_T_139 = eq(_address_ok_T_138, asSInt(UInt<1>(0h0))) node _address_ok_T_140 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _address_ok_T_141 = cvt(_address_ok_T_140) node _address_ok_T_142 = and(_address_ok_T_141, asSInt(UInt<13>(0h1000))) node _address_ok_T_143 = asSInt(_address_ok_T_142) node _address_ok_T_144 = eq(_address_ok_T_143, asSInt(UInt<1>(0h0))) node _address_ok_T_145 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_146 = cvt(_address_ok_T_145) node _address_ok_T_147 = and(_address_ok_T_146, asSInt(UInt<13>(0h1000))) node _address_ok_T_148 = asSInt(_address_ok_T_147) node _address_ok_T_149 = eq(_address_ok_T_148, asSInt(UInt<1>(0h0))) node _address_ok_T_150 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_151 = cvt(_address_ok_T_150) node _address_ok_T_152 = and(_address_ok_T_151, asSInt(UInt<13>(0h1000))) node _address_ok_T_153 = asSInt(_address_ok_T_152) node _address_ok_T_154 = eq(_address_ok_T_153, asSInt(UInt<1>(0h0))) node _address_ok_T_155 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_156 = cvt(_address_ok_T_155) node _address_ok_T_157 = and(_address_ok_T_156, asSInt(UInt<17>(0h10000))) node _address_ok_T_158 = asSInt(_address_ok_T_157) node _address_ok_T_159 = eq(_address_ok_T_158, asSInt(UInt<1>(0h0))) node _address_ok_T_160 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_161 = cvt(_address_ok_T_160) node _address_ok_T_162 = and(_address_ok_T_161, asSInt(UInt<13>(0h1000))) node _address_ok_T_163 = asSInt(_address_ok_T_162) node _address_ok_T_164 = eq(_address_ok_T_163, asSInt(UInt<1>(0h0))) node _address_ok_T_165 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_166 = cvt(_address_ok_T_165) node _address_ok_T_167 = and(_address_ok_T_166, asSInt(UInt<17>(0h10000))) node _address_ok_T_168 = asSInt(_address_ok_T_167) node _address_ok_T_169 = eq(_address_ok_T_168, asSInt(UInt<1>(0h0))) node _address_ok_T_170 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_171 = cvt(_address_ok_T_170) node _address_ok_T_172 = and(_address_ok_T_171, asSInt(UInt<27>(0h4000000))) node _address_ok_T_173 = asSInt(_address_ok_T_172) node _address_ok_T_174 = eq(_address_ok_T_173, asSInt(UInt<1>(0h0))) node _address_ok_T_175 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_176 = cvt(_address_ok_T_175) node _address_ok_T_177 = and(_address_ok_T_176, asSInt(UInt<13>(0h1000))) node _address_ok_T_178 = asSInt(_address_ok_T_177) node _address_ok_T_179 = eq(_address_ok_T_178, asSInt(UInt<1>(0h0))) node _address_ok_T_180 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_181 = cvt(_address_ok_T_180) node _address_ok_T_182 = and(_address_ok_T_181, asSInt(UInt<29>(0h10000000))) node _address_ok_T_183 = asSInt(_address_ok_T_182) node _address_ok_T_184 = eq(_address_ok_T_183, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[17] connect _address_ok_WIRE_1[0], _address_ok_T_104 connect _address_ok_WIRE_1[1], _address_ok_T_109 connect _address_ok_WIRE_1[2], _address_ok_T_114 connect _address_ok_WIRE_1[3], _address_ok_T_119 connect _address_ok_WIRE_1[4], _address_ok_T_124 connect _address_ok_WIRE_1[5], _address_ok_T_129 connect _address_ok_WIRE_1[6], _address_ok_T_134 connect _address_ok_WIRE_1[7], _address_ok_T_139 connect _address_ok_WIRE_1[8], _address_ok_T_144 connect _address_ok_WIRE_1[9], _address_ok_T_149 connect _address_ok_WIRE_1[10], _address_ok_T_154 connect _address_ok_WIRE_1[11], _address_ok_T_159 connect _address_ok_WIRE_1[12], _address_ok_T_164 connect _address_ok_WIRE_1[13], _address_ok_T_169 connect _address_ok_WIRE_1[14], _address_ok_T_174 connect _address_ok_WIRE_1[15], _address_ok_T_179 connect _address_ok_WIRE_1[16], _address_ok_T_184 node _address_ok_T_185 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_186 = or(_address_ok_T_185, _address_ok_WIRE_1[2]) node _address_ok_T_187 = or(_address_ok_T_186, _address_ok_WIRE_1[3]) node _address_ok_T_188 = or(_address_ok_T_187, _address_ok_WIRE_1[4]) node _address_ok_T_189 = or(_address_ok_T_188, _address_ok_WIRE_1[5]) node _address_ok_T_190 = or(_address_ok_T_189, _address_ok_WIRE_1[6]) node _address_ok_T_191 = or(_address_ok_T_190, _address_ok_WIRE_1[7]) node _address_ok_T_192 = or(_address_ok_T_191, _address_ok_WIRE_1[8]) node _address_ok_T_193 = or(_address_ok_T_192, _address_ok_WIRE_1[9]) node _address_ok_T_194 = or(_address_ok_T_193, _address_ok_WIRE_1[10]) node _address_ok_T_195 = or(_address_ok_T_194, _address_ok_WIRE_1[11]) node _address_ok_T_196 = or(_address_ok_T_195, _address_ok_WIRE_1[12]) node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[13]) node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[14]) node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[15]) node address_ok_1 = or(_address_ok_T_199, _address_ok_WIRE_1[16]) node _T_1979 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) node _T_1981 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = or(_T_1980, _T_1985) node _T_1987 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) node _T_1989 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<1>(0h0))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = or(_T_1988, _T_1993) node _T_1995 = and(_T_1986, _T_1994) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_131 node _T_1999 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1999 : node _T_2000 = asUInt(reset) node _T_2001 = eq(_T_2000, UInt<1>(0h0)) when _T_2001 : node _T_2002 = eq(address_ok_1, UInt<1>(0h0)) when _T_2002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(source_ok_2, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2006 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_134 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2013 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_136 node _T_2017 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_137 node _T_2021 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2021 : node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(address_ok_1, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(source_ok_2, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2028 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_140 node _T_2032 = asUInt(reset) node _T_2033 = eq(_T_2032, UInt<1>(0h0)) when _T_2033 : node _T_2034 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2035 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2036 = asUInt(reset) node _T_2037 = eq(_T_2036, UInt<1>(0h0)) when _T_2037 : node _T_2038 = eq(_T_2035, UInt<1>(0h0)) when _T_2038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2035, UInt<1>(0h1), "") : assert_142 node _T_2039 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2039 : node _T_2040 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2041 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2044 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2045 = or(_T_2043, _T_2044) node _T_2046 = and(_T_2042, _T_2045) node _T_2047 = or(UInt<1>(0h0), _T_2046) node _T_2048 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<14>(0h2000))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2055 = cvt(_T_2054) node _T_2056 = and(_T_2055, asSInt(UInt<13>(0h1000))) node _T_2057 = asSInt(_T_2056) node _T_2058 = eq(_T_2057, asSInt(UInt<1>(0h0))) node _T_2059 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2060 = cvt(_T_2059) node _T_2061 = and(_T_2060, asSInt(UInt<17>(0h10000))) node _T_2062 = asSInt(_T_2061) node _T_2063 = eq(_T_2062, asSInt(UInt<1>(0h0))) node _T_2064 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2065 = cvt(_T_2064) node _T_2066 = and(_T_2065, asSInt(UInt<15>(0h4000))) node _T_2067 = asSInt(_T_2066) node _T_2068 = eq(_T_2067, asSInt(UInt<1>(0h0))) node _T_2069 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2070 = cvt(_T_2069) node _T_2071 = and(_T_2070, asSInt(UInt<13>(0h1000))) node _T_2072 = asSInt(_T_2071) node _T_2073 = eq(_T_2072, asSInt(UInt<1>(0h0))) node _T_2074 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2075 = cvt(_T_2074) node _T_2076 = and(_T_2075, asSInt(UInt<18>(0h2f000))) node _T_2077 = asSInt(_T_2076) node _T_2078 = eq(_T_2077, asSInt(UInt<1>(0h0))) node _T_2079 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<17>(0h10000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<27>(0h4000000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<13>(0h1000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2053, _T_2058) node _T_2100 = or(_T_2099, _T_2063) node _T_2101 = or(_T_2100, _T_2068) node _T_2102 = or(_T_2101, _T_2073) node _T_2103 = or(_T_2102, _T_2078) node _T_2104 = or(_T_2103, _T_2083) node _T_2105 = or(_T_2104, _T_2088) node _T_2106 = or(_T_2105, _T_2093) node _T_2107 = or(_T_2106, _T_2098) node _T_2108 = and(_T_2048, _T_2107) node _T_2109 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2110 = or(UInt<1>(0h0), _T_2109) node _T_2111 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<17>(0h10000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<29>(0h10000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = or(_T_2115, _T_2120) node _T_2122 = and(_T_2110, _T_2121) node _T_2123 = or(UInt<1>(0h0), _T_2108) node _T_2124 = or(_T_2123, _T_2122) node _T_2125 = and(_T_2047, _T_2124) node _T_2126 = asUInt(reset) node _T_2127 = eq(_T_2126, UInt<1>(0h0)) when _T_2127 : node _T_2128 = eq(_T_2125, UInt<1>(0h0)) when _T_2128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2125, UInt<1>(0h1), "") : assert_143 node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2130 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_2129 connect _WIRE_6[1], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_6[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = or(_T_2132, _T_2133) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2134 node _T_2135 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2136 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = or(UInt<1>(0h0), _T_2137) node _T_2139 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2140 = cvt(_T_2139) node _T_2141 = and(_T_2140, asSInt(UInt<14>(0h2000))) node _T_2142 = asSInt(_T_2141) node _T_2143 = eq(_T_2142, asSInt(UInt<1>(0h0))) node _T_2144 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2145 = cvt(_T_2144) node _T_2146 = and(_T_2145, asSInt(UInt<13>(0h1000))) node _T_2147 = asSInt(_T_2146) node _T_2148 = eq(_T_2147, asSInt(UInt<1>(0h0))) node _T_2149 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2150 = cvt(_T_2149) node _T_2151 = and(_T_2150, asSInt(UInt<17>(0h10000))) node _T_2152 = asSInt(_T_2151) node _T_2153 = eq(_T_2152, asSInt(UInt<1>(0h0))) node _T_2154 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2155 = cvt(_T_2154) node _T_2156 = and(_T_2155, asSInt(UInt<15>(0h4000))) node _T_2157 = asSInt(_T_2156) node _T_2158 = eq(_T_2157, asSInt(UInt<1>(0h0))) node _T_2159 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2160 = cvt(_T_2159) node _T_2161 = and(_T_2160, asSInt(UInt<13>(0h1000))) node _T_2162 = asSInt(_T_2161) node _T_2163 = eq(_T_2162, asSInt(UInt<1>(0h0))) node _T_2164 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2165 = cvt(_T_2164) node _T_2166 = and(_T_2165, asSInt(UInt<18>(0h2f000))) node _T_2167 = asSInt(_T_2166) node _T_2168 = eq(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<17>(0h10000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<27>(0h4000000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<13>(0h1000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<29>(0h10000000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = or(_T_2143, _T_2148) node _T_2200 = or(_T_2199, _T_2153) node _T_2201 = or(_T_2200, _T_2158) node _T_2202 = or(_T_2201, _T_2163) node _T_2203 = or(_T_2202, _T_2168) node _T_2204 = or(_T_2203, _T_2173) node _T_2205 = or(_T_2204, _T_2178) node _T_2206 = or(_T_2205, _T_2183) node _T_2207 = or(_T_2206, _T_2188) node _T_2208 = or(_T_2207, _T_2193) node _T_2209 = or(_T_2208, _T_2198) node _T_2210 = and(_T_2138, _T_2209) node _T_2211 = or(UInt<1>(0h0), _T_2210) node _T_2212 = and(_WIRE_7, _T_2211) node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(_T_2212, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2212, UInt<1>(0h1), "") : assert_144 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(source_ok_2, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2219 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_146 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2226 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_148 node _T_2230 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_149 node _T_2234 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2234 : node _T_2235 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2236 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2237 = and(_T_2235, _T_2236) node _T_2238 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2239 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2240 = or(_T_2238, _T_2239) node _T_2241 = and(_T_2237, _T_2240) node _T_2242 = or(UInt<1>(0h0), _T_2241) node _T_2243 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2244 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2245 = cvt(_T_2244) node _T_2246 = and(_T_2245, asSInt(UInt<14>(0h2000))) node _T_2247 = asSInt(_T_2246) node _T_2248 = eq(_T_2247, asSInt(UInt<1>(0h0))) node _T_2249 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2250 = cvt(_T_2249) node _T_2251 = and(_T_2250, asSInt(UInt<13>(0h1000))) node _T_2252 = asSInt(_T_2251) node _T_2253 = eq(_T_2252, asSInt(UInt<1>(0h0))) node _T_2254 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2255 = cvt(_T_2254) node _T_2256 = and(_T_2255, asSInt(UInt<17>(0h10000))) node _T_2257 = asSInt(_T_2256) node _T_2258 = eq(_T_2257, asSInt(UInt<1>(0h0))) node _T_2259 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2260 = cvt(_T_2259) node _T_2261 = and(_T_2260, asSInt(UInt<15>(0h4000))) node _T_2262 = asSInt(_T_2261) node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0))) node _T_2264 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2265 = cvt(_T_2264) node _T_2266 = and(_T_2265, asSInt(UInt<13>(0h1000))) node _T_2267 = asSInt(_T_2266) node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0))) node _T_2269 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = or(_T_2248, _T_2253) node _T_2295 = or(_T_2294, _T_2258) node _T_2296 = or(_T_2295, _T_2263) node _T_2297 = or(_T_2296, _T_2268) node _T_2298 = or(_T_2297, _T_2273) node _T_2299 = or(_T_2298, _T_2278) node _T_2300 = or(_T_2299, _T_2283) node _T_2301 = or(_T_2300, _T_2288) node _T_2302 = or(_T_2301, _T_2293) node _T_2303 = and(_T_2243, _T_2302) node _T_2304 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2305 = or(UInt<1>(0h0), _T_2304) node _T_2306 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2307 = cvt(_T_2306) node _T_2308 = and(_T_2307, asSInt(UInt<17>(0h10000))) node _T_2309 = asSInt(_T_2308) node _T_2310 = eq(_T_2309, asSInt(UInt<1>(0h0))) node _T_2311 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2312 = cvt(_T_2311) node _T_2313 = and(_T_2312, asSInt(UInt<29>(0h10000000))) node _T_2314 = asSInt(_T_2313) node _T_2315 = eq(_T_2314, asSInt(UInt<1>(0h0))) node _T_2316 = or(_T_2310, _T_2315) node _T_2317 = and(_T_2305, _T_2316) node _T_2318 = or(UInt<1>(0h0), _T_2303) node _T_2319 = or(_T_2318, _T_2317) node _T_2320 = and(_T_2242, _T_2319) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_150 node _T_2324 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2325 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2324 connect _WIRE_8[1], _T_2325 node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = mux(_WIRE_8[0], _T_2326, UInt<1>(0h0)) node _T_2328 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2329 = or(_T_2327, _T_2328) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2329 node _T_2330 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2331 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2332 = and(_T_2330, _T_2331) node _T_2333 = or(UInt<1>(0h0), _T_2332) node _T_2334 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2335 = cvt(_T_2334) node _T_2336 = and(_T_2335, asSInt(UInt<14>(0h2000))) node _T_2337 = asSInt(_T_2336) node _T_2338 = eq(_T_2337, asSInt(UInt<1>(0h0))) node _T_2339 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2340 = cvt(_T_2339) node _T_2341 = and(_T_2340, asSInt(UInt<13>(0h1000))) node _T_2342 = asSInt(_T_2341) node _T_2343 = eq(_T_2342, asSInt(UInt<1>(0h0))) node _T_2344 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2345 = cvt(_T_2344) node _T_2346 = and(_T_2345, asSInt(UInt<17>(0h10000))) node _T_2347 = asSInt(_T_2346) node _T_2348 = eq(_T_2347, asSInt(UInt<1>(0h0))) node _T_2349 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2350 = cvt(_T_2349) node _T_2351 = and(_T_2350, asSInt(UInt<15>(0h4000))) node _T_2352 = asSInt(_T_2351) node _T_2353 = eq(_T_2352, asSInt(UInt<1>(0h0))) node _T_2354 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2355 = cvt(_T_2354) node _T_2356 = and(_T_2355, asSInt(UInt<13>(0h1000))) node _T_2357 = asSInt(_T_2356) node _T_2358 = eq(_T_2357, asSInt(UInt<1>(0h0))) node _T_2359 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2360 = cvt(_T_2359) node _T_2361 = and(_T_2360, asSInt(UInt<18>(0h2f000))) node _T_2362 = asSInt(_T_2361) node _T_2363 = eq(_T_2362, asSInt(UInt<1>(0h0))) node _T_2364 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2365 = cvt(_T_2364) node _T_2366 = and(_T_2365, asSInt(UInt<17>(0h10000))) node _T_2367 = asSInt(_T_2366) node _T_2368 = eq(_T_2367, asSInt(UInt<1>(0h0))) node _T_2369 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2370 = cvt(_T_2369) node _T_2371 = and(_T_2370, asSInt(UInt<13>(0h1000))) node _T_2372 = asSInt(_T_2371) node _T_2373 = eq(_T_2372, asSInt(UInt<1>(0h0))) node _T_2374 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2375 = cvt(_T_2374) node _T_2376 = and(_T_2375, asSInt(UInt<17>(0h10000))) node _T_2377 = asSInt(_T_2376) node _T_2378 = eq(_T_2377, asSInt(UInt<1>(0h0))) node _T_2379 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2380 = cvt(_T_2379) node _T_2381 = and(_T_2380, asSInt(UInt<27>(0h4000000))) node _T_2382 = asSInt(_T_2381) node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0))) node _T_2384 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2385 = cvt(_T_2384) node _T_2386 = and(_T_2385, asSInt(UInt<13>(0h1000))) node _T_2387 = asSInt(_T_2386) node _T_2388 = eq(_T_2387, asSInt(UInt<1>(0h0))) node _T_2389 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2390 = cvt(_T_2389) node _T_2391 = and(_T_2390, asSInt(UInt<29>(0h10000000))) node _T_2392 = asSInt(_T_2391) node _T_2393 = eq(_T_2392, asSInt(UInt<1>(0h0))) node _T_2394 = or(_T_2338, _T_2343) node _T_2395 = or(_T_2394, _T_2348) node _T_2396 = or(_T_2395, _T_2353) node _T_2397 = or(_T_2396, _T_2358) node _T_2398 = or(_T_2397, _T_2363) node _T_2399 = or(_T_2398, _T_2368) node _T_2400 = or(_T_2399, _T_2373) node _T_2401 = or(_T_2400, _T_2378) node _T_2402 = or(_T_2401, _T_2383) node _T_2403 = or(_T_2402, _T_2388) node _T_2404 = or(_T_2403, _T_2393) node _T_2405 = and(_T_2333, _T_2404) node _T_2406 = or(UInt<1>(0h0), _T_2405) node _T_2407 = and(_WIRE_9, _T_2406) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_151 node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(source_ok_2, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2414 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_153 node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2421 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_155 node _T_2425 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2425 : node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(address_ok_1, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2429 = asUInt(reset) node _T_2430 = eq(_T_2429, UInt<1>(0h0)) when _T_2430 : node _T_2431 = eq(source_ok_2, UInt<1>(0h0)) when _T_2431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2435 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_159 node _T_2439 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_160 node _T_2443 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2443 : node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(address_ok_1, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(source_ok_2, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2453 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_164 node _T_2457 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2457 : node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(address_ok_1, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(source_ok_2, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2467 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_168 node _T_2471 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2472 = asUInt(reset) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) when _T_2473 : node _T_2474 = eq(_T_2471, UInt<1>(0h0)) when _T_2474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2471, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2475 = asUInt(reset) node _T_2476 = eq(_T_2475, UInt<1>(0h0)) when _T_2476 : node _T_2477 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2478 = eq(a_first, UInt<1>(0h0)) node _T_2479 = and(io.in.a.valid, _T_2478) when _T_2479 : node _T_2480 = eq(io.in.a.bits.opcode, opcode) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_171 node _T_2484 = eq(io.in.a.bits.param, param) node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(_T_2484, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2484, UInt<1>(0h1), "") : assert_172 node _T_2488 = eq(io.in.a.bits.size, size) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_173 node _T_2492 = eq(io.in.a.bits.source, source) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_174 node _T_2496 = eq(io.in.a.bits.address, address) node _T_2497 = asUInt(reset) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) when _T_2498 : node _T_2499 = eq(_T_2496, UInt<1>(0h0)) when _T_2499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2496, UInt<1>(0h1), "") : assert_175 node _T_2500 = and(io.in.a.ready, io.in.a.valid) node _T_2501 = and(_T_2500, a_first) when _T_2501 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2502 = eq(d_first, UInt<1>(0h0)) node _T_2503 = and(io.in.d.valid, _T_2502) when _T_2503 : node _T_2504 = eq(io.in.d.bits.opcode, opcode_1) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_176 node _T_2508 = eq(io.in.d.bits.param, param_1) node _T_2509 = asUInt(reset) node _T_2510 = eq(_T_2509, UInt<1>(0h0)) when _T_2510 : node _T_2511 = eq(_T_2508, UInt<1>(0h0)) when _T_2511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2508, UInt<1>(0h1), "") : assert_177 node _T_2512 = eq(io.in.d.bits.size, size_1) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_178 node _T_2516 = eq(io.in.d.bits.source, source_1) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_179 node _T_2520 = eq(io.in.d.bits.sink, sink) node _T_2521 = asUInt(reset) node _T_2522 = eq(_T_2521, UInt<1>(0h0)) when _T_2522 : node _T_2523 = eq(_T_2520, UInt<1>(0h0)) when _T_2523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2520, UInt<1>(0h1), "") : assert_180 node _T_2524 = eq(io.in.d.bits.denied, denied) node _T_2525 = asUInt(reset) node _T_2526 = eq(_T_2525, UInt<1>(0h0)) when _T_2526 : node _T_2527 = eq(_T_2524, UInt<1>(0h0)) when _T_2527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2524, UInt<1>(0h1), "") : assert_181 node _T_2528 = and(io.in.d.ready, io.in.d.valid) node _T_2529 = and(_T_2528, d_first) when _T_2529 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2530 = eq(b_first, UInt<1>(0h0)) node _T_2531 = and(io.in.b.valid, _T_2530) when _T_2531 : node _T_2532 = eq(io.in.b.bits.opcode, opcode_2) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_182 node _T_2536 = eq(io.in.b.bits.param, param_2) node _T_2537 = asUInt(reset) node _T_2538 = eq(_T_2537, UInt<1>(0h0)) when _T_2538 : node _T_2539 = eq(_T_2536, UInt<1>(0h0)) when _T_2539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2536, UInt<1>(0h1), "") : assert_183 node _T_2540 = eq(io.in.b.bits.size, size_2) node _T_2541 = asUInt(reset) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) when _T_2542 : node _T_2543 = eq(_T_2540, UInt<1>(0h0)) when _T_2543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2540, UInt<1>(0h1), "") : assert_184 node _T_2544 = eq(io.in.b.bits.source, source_2) node _T_2545 = asUInt(reset) node _T_2546 = eq(_T_2545, UInt<1>(0h0)) when _T_2546 : node _T_2547 = eq(_T_2544, UInt<1>(0h0)) when _T_2547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2544, UInt<1>(0h1), "") : assert_185 node _T_2548 = eq(io.in.b.bits.address, address_1) node _T_2549 = asUInt(reset) node _T_2550 = eq(_T_2549, UInt<1>(0h0)) when _T_2550 : node _T_2551 = eq(_T_2548, UInt<1>(0h0)) when _T_2551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2548, UInt<1>(0h1), "") : assert_186 node _T_2552 = and(io.in.b.ready, io.in.b.valid) node _T_2553 = and(_T_2552, b_first) when _T_2553 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2554 = eq(c_first, UInt<1>(0h0)) node _T_2555 = and(io.in.c.valid, _T_2554) when _T_2555 : node _T_2556 = eq(io.in.c.bits.opcode, opcode_3) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_187 node _T_2560 = eq(io.in.c.bits.param, param_3) node _T_2561 = asUInt(reset) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) when _T_2562 : node _T_2563 = eq(_T_2560, UInt<1>(0h0)) when _T_2563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2560, UInt<1>(0h1), "") : assert_188 node _T_2564 = eq(io.in.c.bits.size, size_3) node _T_2565 = asUInt(reset) node _T_2566 = eq(_T_2565, UInt<1>(0h0)) when _T_2566 : node _T_2567 = eq(_T_2564, UInt<1>(0h0)) when _T_2567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2564, UInt<1>(0h1), "") : assert_189 node _T_2568 = eq(io.in.c.bits.source, source_3) node _T_2569 = asUInt(reset) node _T_2570 = eq(_T_2569, UInt<1>(0h0)) when _T_2570 : node _T_2571 = eq(_T_2568, UInt<1>(0h0)) when _T_2571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2568, UInt<1>(0h1), "") : assert_190 node _T_2572 = eq(io.in.c.bits.address, address_2) node _T_2573 = asUInt(reset) node _T_2574 = eq(_T_2573, UInt<1>(0h0)) when _T_2574 : node _T_2575 = eq(_T_2572, UInt<1>(0h0)) when _T_2575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2572, UInt<1>(0h1), "") : assert_191 node _T_2576 = and(io.in.c.ready, io.in.c.valid) node _T_2577 = and(_T_2576, c_first) when _T_2577 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2578 = and(io.in.a.valid, a_first_1) node _T_2579 = and(_T_2578, UInt<1>(0h1)) when _T_2579 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2580 = and(io.in.a.ready, io.in.a.valid) node _T_2581 = and(_T_2580, a_first_1) node _T_2582 = and(_T_2581, UInt<1>(0h1)) when _T_2582 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2583 = dshr(inflight, io.in.a.bits.source) node _T_2584 = bits(_T_2583, 0, 0) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2589 = and(io.in.d.valid, d_first_1) node _T_2590 = and(_T_2589, UInt<1>(0h1)) node _T_2591 = eq(d_release_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2593 = and(io.in.d.ready, io.in.d.valid) node _T_2594 = and(_T_2593, d_first_1) node _T_2595 = and(_T_2594, UInt<1>(0h1)) node _T_2596 = eq(d_release_ack, UInt<1>(0h0)) node _T_2597 = and(_T_2595, _T_2596) when _T_2597 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2598 = and(io.in.d.valid, d_first_1) node _T_2599 = and(_T_2598, UInt<1>(0h1)) node _T_2600 = eq(d_release_ack, UInt<1>(0h0)) node _T_2601 = and(_T_2599, _T_2600) when _T_2601 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2602 = dshr(inflight, io.in.d.bits.source) node _T_2603 = bits(_T_2602, 0, 0) node _T_2604 = or(_T_2603, same_cycle_resp) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2608 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2609 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2610 = or(_T_2608, _T_2609) node _T_2611 = asUInt(reset) node _T_2612 = eq(_T_2611, UInt<1>(0h0)) when _T_2612 : node _T_2613 = eq(_T_2610, UInt<1>(0h0)) when _T_2613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2610, UInt<1>(0h1), "") : assert_194 node _T_2614 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2615 = asUInt(reset) node _T_2616 = eq(_T_2615, UInt<1>(0h0)) when _T_2616 : node _T_2617 = eq(_T_2614, UInt<1>(0h0)) when _T_2617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2614, UInt<1>(0h1), "") : assert_195 else : node _T_2618 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2619 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2620 = or(_T_2618, _T_2619) node _T_2621 = asUInt(reset) node _T_2622 = eq(_T_2621, UInt<1>(0h0)) when _T_2622 : node _T_2623 = eq(_T_2620, UInt<1>(0h0)) when _T_2623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2620, UInt<1>(0h1), "") : assert_196 node _T_2624 = eq(io.in.d.bits.size, a_size_lookup) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_197 node _T_2628 = and(io.in.d.valid, d_first_1) node _T_2629 = and(_T_2628, a_first_1) node _T_2630 = and(_T_2629, io.in.a.valid) node _T_2631 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2632 = and(_T_2630, _T_2631) node _T_2633 = eq(d_release_ack, UInt<1>(0h0)) node _T_2634 = and(_T_2632, _T_2633) when _T_2634 : node _T_2635 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2636 = or(_T_2635, io.in.a.ready) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_198 node _T_2640 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2641 = orr(a_set_wo_ready) node _T_2642 = eq(_T_2641, UInt<1>(0h0)) node _T_2643 = or(_T_2640, _T_2642) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_161 node _T_2647 = orr(inflight) node _T_2648 = eq(_T_2647, UInt<1>(0h0)) node _T_2649 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2650 = or(_T_2648, _T_2649) node _T_2651 = lt(watchdog, plusarg_reader.out) node _T_2652 = or(_T_2650, _T_2651) node _T_2653 = asUInt(reset) node _T_2654 = eq(_T_2653, UInt<1>(0h0)) when _T_2654 : node _T_2655 = eq(_T_2652, UInt<1>(0h0)) when _T_2655 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2652, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2656 = and(io.in.a.ready, io.in.a.valid) node _T_2657 = and(io.in.d.ready, io.in.d.valid) node _T_2658 = or(_T_2656, _T_2657) when _T_2658 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2659 = and(io.in.c.valid, c_first_1) node _T_2660 = bits(io.in.c.bits.opcode, 2, 2) node _T_2661 = bits(io.in.c.bits.opcode, 1, 1) node _T_2662 = and(_T_2660, _T_2661) node _T_2663 = and(_T_2659, _T_2662) when _T_2663 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2664 = and(io.in.c.ready, io.in.c.valid) node _T_2665 = and(_T_2664, c_first_1) node _T_2666 = bits(io.in.c.bits.opcode, 2, 2) node _T_2667 = bits(io.in.c.bits.opcode, 1, 1) node _T_2668 = and(_T_2666, _T_2667) node _T_2669 = and(_T_2665, _T_2668) when _T_2669 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2670 = dshr(inflight_1, io.in.c.bits.source) node _T_2671 = bits(_T_2670, 0, 0) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) node _T_2673 = asUInt(reset) node _T_2674 = eq(_T_2673, UInt<1>(0h0)) when _T_2674 : node _T_2675 = eq(_T_2672, UInt<1>(0h0)) when _T_2675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2672, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2676 = and(io.in.d.valid, d_first_2) node _T_2677 = and(_T_2676, UInt<1>(0h1)) node _T_2678 = and(_T_2677, d_release_ack_1) when _T_2678 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2679 = and(io.in.d.ready, io.in.d.valid) node _T_2680 = and(_T_2679, d_first_2) node _T_2681 = and(_T_2680, UInt<1>(0h1)) node _T_2682 = and(_T_2681, d_release_ack_1) when _T_2682 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2683 = and(io.in.d.valid, d_first_2) node _T_2684 = and(_T_2683, UInt<1>(0h1)) node _T_2685 = and(_T_2684, d_release_ack_1) when _T_2685 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2686 = dshr(inflight_1, io.in.d.bits.source) node _T_2687 = bits(_T_2686, 0, 0) node _T_2688 = or(_T_2687, same_cycle_resp_1) node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(_T_2688, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2688, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2692 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2693 = asUInt(reset) node _T_2694 = eq(_T_2693, UInt<1>(0h0)) when _T_2694 : node _T_2695 = eq(_T_2692, UInt<1>(0h0)) when _T_2695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2692, UInt<1>(0h1), "") : assert_203 else : node _T_2696 = eq(io.in.d.bits.size, c_size_lookup) node _T_2697 = asUInt(reset) node _T_2698 = eq(_T_2697, UInt<1>(0h0)) when _T_2698 : node _T_2699 = eq(_T_2696, UInt<1>(0h0)) when _T_2699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2696, UInt<1>(0h1), "") : assert_204 node _T_2700 = and(io.in.d.valid, d_first_2) node _T_2701 = and(_T_2700, c_first_1) node _T_2702 = and(_T_2701, io.in.c.valid) node _T_2703 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2704 = and(_T_2702, _T_2703) node _T_2705 = and(_T_2704, d_release_ack_1) node _T_2706 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2707 = and(_T_2705, _T_2706) when _T_2707 : node _T_2708 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2709 = or(_T_2708, io.in.c.ready) node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(_T_2709, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2709, UInt<1>(0h1), "") : assert_205 node _T_2713 = orr(c_set_wo_ready) when _T_2713 : node _T_2714 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2715 = asUInt(reset) node _T_2716 = eq(_T_2715, UInt<1>(0h0)) when _T_2716 : node _T_2717 = eq(_T_2714, UInt<1>(0h0)) when _T_2717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2714, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_162 node _T_2718 = orr(inflight_1) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) node _T_2720 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2721 = or(_T_2719, _T_2720) node _T_2722 = lt(watchdog_1, plusarg_reader_1.out) node _T_2723 = or(_T_2721, _T_2722) node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(_T_2723, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2723, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2727 = and(io.in.c.ready, io.in.c.valid) node _T_2728 = and(io.in.d.ready, io.in.d.valid) node _T_2729 = or(_T_2727, _T_2728) when _T_2729 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2730 = and(io.in.d.ready, io.in.d.valid) node _T_2731 = and(_T_2730, d_first_3) node _T_2732 = bits(io.in.d.bits.opcode, 2, 2) node _T_2733 = bits(io.in.d.bits.opcode, 1, 1) node _T_2734 = eq(_T_2733, UInt<1>(0h0)) node _T_2735 = and(_T_2732, _T_2734) node _T_2736 = and(_T_2731, _T_2735) when _T_2736 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2737 = dshr(inflight_2, io.in.d.bits.sink) node _T_2738 = bits(_T_2737, 0, 0) node _T_2739 = eq(_T_2738, UInt<1>(0h0)) node _T_2740 = asUInt(reset) node _T_2741 = eq(_T_2740, UInt<1>(0h0)) when _T_2741 : node _T_2742 = eq(_T_2739, UInt<1>(0h0)) when _T_2742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2739, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2743 = and(io.in.e.ready, io.in.e.valid) node _T_2744 = and(_T_2743, UInt<1>(0h1)) node _T_2745 = and(_T_2744, UInt<1>(0h1)) when _T_2745 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2746 = or(d_set, inflight_2) node _T_2747 = dshr(_T_2746, io.in.e.bits.sink) node _T_2748 = bits(_T_2747, 0, 0) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/manager/Manager.scala:222:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_79( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 | _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 | _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 | _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 | _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 | _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_10 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_10; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_11 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_11; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_12 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_13 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_15 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_16 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_18 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_20 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_21 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_21}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 | _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 | _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 | _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 | _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 | _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35] wire [26:0] _GEN_22 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_22; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_23 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_23; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_23; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_24 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_24; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_24; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_25 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_26 = 2'h1 << _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_26; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_27 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_27; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_27; // @[Monitor.scala:673:46, :783:46] wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_28 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_29 = 2'h1 << _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_29; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_30 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_31 = 2'h1 << _GEN_30; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_31; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_31; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_32 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35] assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_33 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_33; // @[OneHot.scala:58:35] assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_14 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_112 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_113 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_114 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_115 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_14( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_112 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_113 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_114 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_115 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_prci_ctrl : input clock : Clock input reset : Reset output auto : { fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fixer of TLFIFOFixer_3 connect fixer.clock, clock connect fixer.reset, reset inst buffer of TLBuffer_a21d64s5k1z3u connect buffer.clock, clock connect buffer.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect buffer.auto.in, tlOut connect fixer.auto.anon_in, buffer.auto.out connect tlIn, auto.tl_in connect fixer.auto.anon_out.d, auto.fixer_anon_out.d connect auto.fixer_anon_out.a.bits, fixer.auto.anon_out.a.bits connect auto.fixer_anon_out.a.valid, fixer.auto.anon_out.a.valid connect fixer.auto.anon_out.a.ready, auto.fixer_anon_out.a.ready
module TLInterconnectCoupler_cbus_to_prci_ctrl( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire tlOut_d_bits_denied; // @[MixedNode.scala:542:17] wire tlOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [4:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [20:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire auto_fixer_anon_out_a_ready_0 = auto_fixer_anon_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_fixer_anon_out_d_valid_0 = auto_fixer_anon_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fixer_anon_out_d_bits_opcode_0 = auto_fixer_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fixer_anon_out_d_bits_size_0 = auto_fixer_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_fixer_anon_out_d_bits_source_0 = auto_fixer_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fixer_anon_out_d_bits_data_0 = auto_fixer_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire [21:0] fixer__a_notFIFO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] fixer__a_notFIFO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire [25:0] fixer__allIDs_FIFOed_T = 26'h3FFFFFF; // @[FIFOFixer.scala:127:48] wire auto_fixer_anon_out_d_bits_sink = 1'h0; // @[LazyModuleImp.scala:138:7] wire auto_fixer_anon_out_d_bits_denied = 1'h0; // @[LazyModuleImp.scala:138:7] wire auto_fixer_anon_out_d_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire [1:0] auto_fixer_anon_out_d_bits_param = 2'h0; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire fixer_auto_anon_out_a_ready = auto_fixer_anon_out_a_ready_0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [20:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_valid = auto_fixer_anon_out_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode = auto_fixer_anon_out_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size = auto_fixer_anon_out_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_d_bits_source = auto_fixer_anon_out_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data = auto_fixer_anon_out_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [4:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_fixer_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fixer_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fixer_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_fixer_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [20:0] auto_fixer_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_fixer_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fixer_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_fixer_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_fixer_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_fixer_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [20:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_valid_0 = fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_opcode_0 = fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_param_0 = fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_size_0 = fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_source_0 = fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [20:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_address_0 = fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_mask_0 = fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_data_0 = fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_a_bits_corrupt_0 = fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] assign auto_fixer_anon_out_d_ready_0 = fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [20:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [20:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire [21:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [20:0] fixer__a_id_T_5 = {fixer_anonIn_a_bits_address[20:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [21:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} | fixer__a_id_T_11; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [25:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [25:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [25:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [31:0] fixer__SourceIdSet_T = 32'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [31:0] fixer__SourceIdClear_T = 32'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [25:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_param_0 = tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_sink_0 = tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LazyModuleImp.scala:138:7] if (reset) begin // @[LazyModuleImp.scala:138:7] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 26'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:138:7] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) TLBuffer_a21d64s5k1z3u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (tlOut_a_ready), .auto_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_in_d_valid (tlOut_d_valid), .auto_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_in_d_bits_param (tlOut_d_bits_param), .auto_in_d_bits_size (tlOut_d_bits_size), .auto_in_d_bits_source (tlOut_d_bits_source), .auto_in_d_bits_sink (tlOut_d_bits_sink), .auto_in_d_bits_denied (tlOut_d_bits_denied), .auto_in_d_bits_data (tlOut_d_bits_data), .auto_in_d_bits_corrupt (tlOut_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] assign auto_fixer_anon_out_a_valid = auto_fixer_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_opcode = auto_fixer_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_param = auto_fixer_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_size = auto_fixer_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_source = auto_fixer_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_address = auto_fixer_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_mask = auto_fixer_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_data = auto_fixer_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_a_bits_corrupt = auto_fixer_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_fixer_anon_out_d_ready = auto_fixer_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_param = auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_sink = auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ShuttleFPPipe : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}, flip frs1_data : UInt<65>, flip frs2_data : UInt<65>, flip frs3_data : UInt<65>, flip fcsr_rm : UInt<3>, flip s1_kill : UInt<1>, s1_store_data : UInt<64>, s1_fpiu_toint : UInt<64>, s1_fpiu_fexc : UInt, s1_fpiu_fdiv : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, flip s2_kill : UInt<1>, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, out_rd : UInt<5>, out_tag : UInt<2>} node _rm_T = bits(io.in.bits.inst, 14, 12) node _rm_T_1 = eq(_rm_T, UInt<3>(0h7)) node _rm_T_2 = bits(io.in.bits.inst, 14, 12) node rm = mux(_rm_T_1, io.fcsr_rm, _rm_T_2) inst fpiu of FPToInt connect fpiu.clock, clock connect fpiu.reset, reset node _fpiu_io_in_valid_T = or(io.in.bits.fp_ctrl.toint, io.in.bits.fp_ctrl.div) node _fpiu_io_in_valid_T_1 = or(_fpiu_io_in_valid_T, io.in.bits.fp_ctrl.sqrt) node _fpiu_io_in_valid_T_2 = and(io.in.bits.fp_ctrl.fastpipe, io.in.bits.fp_ctrl.wflags) node _fpiu_io_in_valid_T_3 = or(_fpiu_io_in_valid_T_1, _fpiu_io_in_valid_T_2) node _fpiu_io_in_valid_T_4 = and(io.in.valid, _fpiu_io_in_valid_T_3) connect fpiu.io.in.valid, _fpiu_io_in_valid_T_4 wire fpiu_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect fpiu_io_in_bits_req.ldst, io.in.bits.fp_ctrl.ldst connect fpiu_io_in_bits_req.wen, io.in.bits.fp_ctrl.wen connect fpiu_io_in_bits_req.ren1, io.in.bits.fp_ctrl.ren1 connect fpiu_io_in_bits_req.ren2, io.in.bits.fp_ctrl.ren2 connect fpiu_io_in_bits_req.ren3, io.in.bits.fp_ctrl.ren3 connect fpiu_io_in_bits_req.swap12, io.in.bits.fp_ctrl.swap12 connect fpiu_io_in_bits_req.swap23, io.in.bits.fp_ctrl.swap23 connect fpiu_io_in_bits_req.typeTagIn, io.in.bits.fp_ctrl.typeTagIn connect fpiu_io_in_bits_req.typeTagOut, io.in.bits.fp_ctrl.typeTagOut connect fpiu_io_in_bits_req.fromint, io.in.bits.fp_ctrl.fromint connect fpiu_io_in_bits_req.toint, io.in.bits.fp_ctrl.toint connect fpiu_io_in_bits_req.fastpipe, io.in.bits.fp_ctrl.fastpipe connect fpiu_io_in_bits_req.fma, io.in.bits.fp_ctrl.fma connect fpiu_io_in_bits_req.div, io.in.bits.fp_ctrl.div connect fpiu_io_in_bits_req.sqrt, io.in.bits.fp_ctrl.sqrt connect fpiu_io_in_bits_req.wflags, io.in.bits.fp_ctrl.wflags connect fpiu_io_in_bits_req.vec, io.in.bits.fp_ctrl.vec connect fpiu_io_in_bits_req.rm, rm node _fpiu_io_in_bits_req_in1_prev_unswizzled_T = bits(io.frs1_data, 31, 31) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.frs1_data, 52, 52) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.frs1_data, 30, 0) node fpiu_io_in_bits_req_in1_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in1_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in1_floats_0 = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in1_prev_prev_0_1 = and(fpiu_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in1_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in1_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in1_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in1_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in1_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in1_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut) node fpiu_io_in_bits_req_in1_floats_1 = cat(fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut) node _fpiu_io_in_bits_req_in1_prev_isbox_T = bits(io.frs1_data, 64, 60) node fpiu_io_in_bits_req_in1_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_isbox_T) node fpiu_io_in_bits_req_in1_oks_0 = and(fpiu_io_in_bits_req_in1_prev_isbox, fpiu_io_in_bits_req_in1_prev_prev_0_1) node fpiu_io_in_bits_req_in1_oks_1 = and(fpiu_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_1 = mux(_fpiu_io_in_bits_req_in1_T, fpiu_io_in_bits_req_in1_oks_1, fpiu_io_in_bits_req_in1_oks_0) node _fpiu_io_in_bits_req_in1_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in1_T_3 = mux(_fpiu_io_in_bits_req_in1_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in1_T_1) node _fpiu_io_in_bits_req_in1_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in1_T_5 = mux(_fpiu_io_in_bits_req_in1_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in1_T_3) node _fpiu_io_in_bits_req_in1_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_7 = mux(_fpiu_io_in_bits_req_in1_T_6, fpiu_io_in_bits_req_in1_floats_1, fpiu_io_in_bits_req_in1_floats_0) node _fpiu_io_in_bits_req_in1_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in1_T_9 = mux(_fpiu_io_in_bits_req_in1_T_8, io.frs1_data, _fpiu_io_in_bits_req_in1_T_7) node _fpiu_io_in_bits_req_in1_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in1_T_11 = mux(_fpiu_io_in_bits_req_in1_T_10, io.frs1_data, _fpiu_io_in_bits_req_in1_T_9) node _fpiu_io_in_bits_req_in1_T_12 = mux(_fpiu_io_in_bits_req_in1_T_5, _fpiu_io_in_bits_req_in1_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in1, _fpiu_io_in_bits_req_in1_T_12 node _fpiu_io_in_bits_req_in2_prev_unswizzled_T = bits(io.frs2_data, 31, 31) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.frs2_data, 52, 52) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.frs2_data, 30, 0) node fpiu_io_in_bits_req_in2_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in2_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in2_floats_0 = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in2_prev_prev_0_1 = and(fpiu_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in2_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in2_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in2_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in2_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in2_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in2_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut) node fpiu_io_in_bits_req_in2_floats_1 = cat(fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut) node _fpiu_io_in_bits_req_in2_prev_isbox_T = bits(io.frs2_data, 64, 60) node fpiu_io_in_bits_req_in2_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_isbox_T) node fpiu_io_in_bits_req_in2_oks_0 = and(fpiu_io_in_bits_req_in2_prev_isbox, fpiu_io_in_bits_req_in2_prev_prev_0_1) node fpiu_io_in_bits_req_in2_oks_1 = and(fpiu_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_1 = mux(_fpiu_io_in_bits_req_in2_T, fpiu_io_in_bits_req_in2_oks_1, fpiu_io_in_bits_req_in2_oks_0) node _fpiu_io_in_bits_req_in2_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in2_T_3 = mux(_fpiu_io_in_bits_req_in2_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in2_T_1) node _fpiu_io_in_bits_req_in2_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in2_T_5 = mux(_fpiu_io_in_bits_req_in2_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in2_T_3) node _fpiu_io_in_bits_req_in2_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_7 = mux(_fpiu_io_in_bits_req_in2_T_6, fpiu_io_in_bits_req_in2_floats_1, fpiu_io_in_bits_req_in2_floats_0) node _fpiu_io_in_bits_req_in2_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in2_T_9 = mux(_fpiu_io_in_bits_req_in2_T_8, io.frs2_data, _fpiu_io_in_bits_req_in2_T_7) node _fpiu_io_in_bits_req_in2_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in2_T_11 = mux(_fpiu_io_in_bits_req_in2_T_10, io.frs2_data, _fpiu_io_in_bits_req_in2_T_9) node _fpiu_io_in_bits_req_in2_T_12 = mux(_fpiu_io_in_bits_req_in2_T_5, _fpiu_io_in_bits_req_in2_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in2, _fpiu_io_in_bits_req_in2_T_12 node _fpiu_io_in_bits_req_in3_prev_unswizzled_T = bits(io.frs3_data, 31, 31) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.frs3_data, 52, 52) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.frs3_data, 30, 0) node fpiu_io_in_bits_req_in3_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in3_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in3_floats_0 = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in3_prev_prev_0_1 = and(fpiu_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in3_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in3_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in3_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in3_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in3_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in3_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut) node fpiu_io_in_bits_req_in3_floats_1 = cat(fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut) node _fpiu_io_in_bits_req_in3_prev_isbox_T = bits(io.frs3_data, 64, 60) node fpiu_io_in_bits_req_in3_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_isbox_T) node fpiu_io_in_bits_req_in3_oks_0 = and(fpiu_io_in_bits_req_in3_prev_isbox, fpiu_io_in_bits_req_in3_prev_prev_0_1) node fpiu_io_in_bits_req_in3_oks_1 = and(fpiu_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_1 = mux(_fpiu_io_in_bits_req_in3_T, fpiu_io_in_bits_req_in3_oks_1, fpiu_io_in_bits_req_in3_oks_0) node _fpiu_io_in_bits_req_in3_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in3_T_3 = mux(_fpiu_io_in_bits_req_in3_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in3_T_1) node _fpiu_io_in_bits_req_in3_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in3_T_5 = mux(_fpiu_io_in_bits_req_in3_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in3_T_3) node _fpiu_io_in_bits_req_in3_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_7 = mux(_fpiu_io_in_bits_req_in3_T_6, fpiu_io_in_bits_req_in3_floats_1, fpiu_io_in_bits_req_in3_floats_0) node _fpiu_io_in_bits_req_in3_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in3_T_9 = mux(_fpiu_io_in_bits_req_in3_T_8, io.frs3_data, _fpiu_io_in_bits_req_in3_T_7) node _fpiu_io_in_bits_req_in3_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in3_T_11 = mux(_fpiu_io_in_bits_req_in3_T_10, io.frs3_data, _fpiu_io_in_bits_req_in3_T_9) node _fpiu_io_in_bits_req_in3_T_12 = mux(_fpiu_io_in_bits_req_in3_T_5, _fpiu_io_in_bits_req_in3_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in3, _fpiu_io_in_bits_req_in3_T_12 node _fpiu_io_in_bits_req_typ_T = bits(io.in.bits.inst, 21, 20) connect fpiu_io_in_bits_req.typ, _fpiu_io_in_bits_req_typ_T node _fpiu_io_in_bits_req_fmt_T = bits(io.in.bits.inst, 26, 25) connect fpiu_io_in_bits_req.fmt, _fpiu_io_in_bits_req_fmt_T node _fpiu_io_in_bits_req_fmaCmd_T = bits(io.in.bits.inst, 3, 2) node _fpiu_io_in_bits_req_fmaCmd_T_1 = eq(io.in.bits.fp_ctrl.ren3, UInt<1>(0h0)) node _fpiu_io_in_bits_req_fmaCmd_T_2 = bits(io.in.bits.inst, 27, 27) node _fpiu_io_in_bits_req_fmaCmd_T_3 = and(_fpiu_io_in_bits_req_fmaCmd_T_1, _fpiu_io_in_bits_req_fmaCmd_T_2) node _fpiu_io_in_bits_req_fmaCmd_T_4 = or(_fpiu_io_in_bits_req_fmaCmd_T, _fpiu_io_in_bits_req_fmaCmd_T_3) connect fpiu_io_in_bits_req.fmaCmd, _fpiu_io_in_bits_req_fmaCmd_T_4 connect fpiu_io_in_bits_req.vec, UInt<1>(0h0) connect fpiu.io.in.bits.in3, fpiu_io_in_bits_req.in3 connect fpiu.io.in.bits.in2, fpiu_io_in_bits_req.in2 connect fpiu.io.in.bits.in1, fpiu_io_in_bits_req.in1 connect fpiu.io.in.bits.fmt, fpiu_io_in_bits_req.fmt connect fpiu.io.in.bits.typ, fpiu_io_in_bits_req.typ connect fpiu.io.in.bits.fmaCmd, fpiu_io_in_bits_req.fmaCmd connect fpiu.io.in.bits.rm, fpiu_io_in_bits_req.rm connect fpiu.io.in.bits.vec, fpiu_io_in_bits_req.vec connect fpiu.io.in.bits.wflags, fpiu_io_in_bits_req.wflags connect fpiu.io.in.bits.sqrt, fpiu_io_in_bits_req.sqrt connect fpiu.io.in.bits.div, fpiu_io_in_bits_req.div connect fpiu.io.in.bits.fma, fpiu_io_in_bits_req.fma connect fpiu.io.in.bits.fastpipe, fpiu_io_in_bits_req.fastpipe connect fpiu.io.in.bits.toint, fpiu_io_in_bits_req.toint connect fpiu.io.in.bits.fromint, fpiu_io_in_bits_req.fromint connect fpiu.io.in.bits.typeTagOut, fpiu_io_in_bits_req.typeTagOut connect fpiu.io.in.bits.typeTagIn, fpiu_io_in_bits_req.typeTagIn connect fpiu.io.in.bits.swap23, fpiu_io_in_bits_req.swap23 connect fpiu.io.in.bits.swap12, fpiu_io_in_bits_req.swap12 connect fpiu.io.in.bits.ren3, fpiu_io_in_bits_req.ren3 connect fpiu.io.in.bits.ren2, fpiu_io_in_bits_req.ren2 connect fpiu.io.in.bits.ren1, fpiu_io_in_bits_req.ren1 connect fpiu.io.in.bits.wen, fpiu_io_in_bits_req.wen connect fpiu.io.in.bits.ldst, fpiu_io_in_bits_req.ldst connect io.s1_store_data, fpiu.io.out.bits.store connect io.s1_fpiu_toint, fpiu.io.out.bits.toint connect io.s1_fpiu_fexc, fpiu.io.out.bits.exc connect io.s1_fpiu_fdiv, fpiu.io.out.bits.in inst dfma of FPUFMAPipe_l4_f64 connect dfma.clock, clock connect dfma.reset, reset inst sfma of FPUFMAPipe_l4_f32 connect sfma.clock, clock connect sfma.reset, reset inst hfma of FPUFMAPipe_l4_f16 connect hfma.clock, clock connect hfma.reset, reset node _dfma_io_in_valid_T = eq(io.in.bits.fp_ctrl.typeTagOut, UInt<2>(0h2)) node _dfma_io_in_valid_T_1 = and(io.in.valid, _dfma_io_in_valid_T) node _dfma_io_in_valid_T_2 = and(_dfma_io_in_valid_T_1, io.in.bits.fp_ctrl.fma) connect dfma.io.in.valid, _dfma_io_in_valid_T_2 wire dfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect dfma_io_in_bits_req.ldst, io.in.bits.fp_ctrl.ldst connect dfma_io_in_bits_req.wen, io.in.bits.fp_ctrl.wen connect dfma_io_in_bits_req.ren1, io.in.bits.fp_ctrl.ren1 connect dfma_io_in_bits_req.ren2, io.in.bits.fp_ctrl.ren2 connect dfma_io_in_bits_req.ren3, io.in.bits.fp_ctrl.ren3 connect dfma_io_in_bits_req.swap12, io.in.bits.fp_ctrl.swap12 connect dfma_io_in_bits_req.swap23, io.in.bits.fp_ctrl.swap23 connect dfma_io_in_bits_req.typeTagIn, io.in.bits.fp_ctrl.typeTagIn connect dfma_io_in_bits_req.typeTagOut, io.in.bits.fp_ctrl.typeTagOut connect dfma_io_in_bits_req.fromint, io.in.bits.fp_ctrl.fromint connect dfma_io_in_bits_req.toint, io.in.bits.fp_ctrl.toint connect dfma_io_in_bits_req.fastpipe, io.in.bits.fp_ctrl.fastpipe connect dfma_io_in_bits_req.fma, io.in.bits.fp_ctrl.fma connect dfma_io_in_bits_req.div, io.in.bits.fp_ctrl.div connect dfma_io_in_bits_req.sqrt, io.in.bits.fp_ctrl.sqrt connect dfma_io_in_bits_req.wflags, io.in.bits.fp_ctrl.wflags connect dfma_io_in_bits_req.vec, io.in.bits.fp_ctrl.vec connect dfma_io_in_bits_req.rm, rm node _dfma_io_in_bits_req_in1_prev_unswizzled_T = bits(io.frs1_data, 31, 31) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.frs1_data, 52, 52) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.frs1_data, 30, 0) node dfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1) node dfma_io_in_bits_req_in1_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in1_floats_0 = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in1_prev_prev_0_1 = and(dfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in1_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in1_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in1_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in1_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in1_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut) node dfma_io_in_bits_req_in1_floats_1 = cat(dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut) node _dfma_io_in_bits_req_in1_prev_isbox_T = bits(io.frs1_data, 64, 60) node dfma_io_in_bits_req_in1_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_isbox_T) node dfma_io_in_bits_req_in1_oks_0 = and(dfma_io_in_bits_req_in1_prev_isbox, dfma_io_in_bits_req_in1_prev_prev_0_1) node dfma_io_in_bits_req_in1_oks_1 = and(dfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in1_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in1_T_1 = or(io.frs1_data, _dfma_io_in_bits_req_in1_T) connect dfma_io_in_bits_req.in1, _dfma_io_in_bits_req_in1_T_1 node _dfma_io_in_bits_req_in2_prev_unswizzled_T = bits(io.frs2_data, 31, 31) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.frs2_data, 52, 52) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.frs2_data, 30, 0) node dfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1) node dfma_io_in_bits_req_in2_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in2_floats_0 = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in2_prev_prev_0_1 = and(dfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in2_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in2_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in2_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in2_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in2_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut) node dfma_io_in_bits_req_in2_floats_1 = cat(dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut) node _dfma_io_in_bits_req_in2_prev_isbox_T = bits(io.frs2_data, 64, 60) node dfma_io_in_bits_req_in2_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_isbox_T) node dfma_io_in_bits_req_in2_oks_0 = and(dfma_io_in_bits_req_in2_prev_isbox, dfma_io_in_bits_req_in2_prev_prev_0_1) node dfma_io_in_bits_req_in2_oks_1 = and(dfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in2_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in2_T_1 = or(io.frs2_data, _dfma_io_in_bits_req_in2_T) connect dfma_io_in_bits_req.in2, _dfma_io_in_bits_req_in2_T_1 node _dfma_io_in_bits_req_in3_prev_unswizzled_T = bits(io.frs3_data, 31, 31) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.frs3_data, 52, 52) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.frs3_data, 30, 0) node dfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1) node dfma_io_in_bits_req_in3_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in3_floats_0 = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in3_prev_prev_0_1 = and(dfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in3_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in3_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in3_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in3_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in3_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut) node dfma_io_in_bits_req_in3_floats_1 = cat(dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut) node _dfma_io_in_bits_req_in3_prev_isbox_T = bits(io.frs3_data, 64, 60) node dfma_io_in_bits_req_in3_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_isbox_T) node dfma_io_in_bits_req_in3_oks_0 = and(dfma_io_in_bits_req_in3_prev_isbox, dfma_io_in_bits_req_in3_prev_prev_0_1) node dfma_io_in_bits_req_in3_oks_1 = and(dfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in3_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in3_T_1 = or(io.frs3_data, _dfma_io_in_bits_req_in3_T) connect dfma_io_in_bits_req.in3, _dfma_io_in_bits_req_in3_T_1 node _dfma_io_in_bits_req_typ_T = bits(io.in.bits.inst, 21, 20) connect dfma_io_in_bits_req.typ, _dfma_io_in_bits_req_typ_T node _dfma_io_in_bits_req_fmt_T = bits(io.in.bits.inst, 26, 25) connect dfma_io_in_bits_req.fmt, _dfma_io_in_bits_req_fmt_T node _dfma_io_in_bits_req_fmaCmd_T = bits(io.in.bits.inst, 3, 2) node _dfma_io_in_bits_req_fmaCmd_T_1 = eq(io.in.bits.fp_ctrl.ren3, UInt<1>(0h0)) node _dfma_io_in_bits_req_fmaCmd_T_2 = bits(io.in.bits.inst, 27, 27) node _dfma_io_in_bits_req_fmaCmd_T_3 = and(_dfma_io_in_bits_req_fmaCmd_T_1, _dfma_io_in_bits_req_fmaCmd_T_2) node _dfma_io_in_bits_req_fmaCmd_T_4 = or(_dfma_io_in_bits_req_fmaCmd_T, _dfma_io_in_bits_req_fmaCmd_T_3) connect dfma_io_in_bits_req.fmaCmd, _dfma_io_in_bits_req_fmaCmd_T_4 connect dfma_io_in_bits_req.vec, UInt<1>(0h0) connect dfma.io.in.bits.in3, dfma_io_in_bits_req.in3 connect dfma.io.in.bits.in2, dfma_io_in_bits_req.in2 connect dfma.io.in.bits.in1, dfma_io_in_bits_req.in1 connect dfma.io.in.bits.fmt, dfma_io_in_bits_req.fmt connect dfma.io.in.bits.typ, dfma_io_in_bits_req.typ connect dfma.io.in.bits.fmaCmd, dfma_io_in_bits_req.fmaCmd connect dfma.io.in.bits.rm, dfma_io_in_bits_req.rm connect dfma.io.in.bits.vec, dfma_io_in_bits_req.vec connect dfma.io.in.bits.wflags, dfma_io_in_bits_req.wflags connect dfma.io.in.bits.sqrt, dfma_io_in_bits_req.sqrt connect dfma.io.in.bits.div, dfma_io_in_bits_req.div connect dfma.io.in.bits.fma, dfma_io_in_bits_req.fma connect dfma.io.in.bits.fastpipe, dfma_io_in_bits_req.fastpipe connect dfma.io.in.bits.toint, dfma_io_in_bits_req.toint connect dfma.io.in.bits.fromint, dfma_io_in_bits_req.fromint connect dfma.io.in.bits.typeTagOut, dfma_io_in_bits_req.typeTagOut connect dfma.io.in.bits.typeTagIn, dfma_io_in_bits_req.typeTagIn connect dfma.io.in.bits.swap23, dfma_io_in_bits_req.swap23 connect dfma.io.in.bits.swap12, dfma_io_in_bits_req.swap12 connect dfma.io.in.bits.ren3, dfma_io_in_bits_req.ren3 connect dfma.io.in.bits.ren2, dfma_io_in_bits_req.ren2 connect dfma.io.in.bits.ren1, dfma_io_in_bits_req.ren1 connect dfma.io.in.bits.wen, dfma_io_in_bits_req.wen connect dfma.io.in.bits.ldst, dfma_io_in_bits_req.ldst node _sfma_io_in_valid_T = eq(io.in.bits.fp_ctrl.typeTagOut, UInt<1>(0h1)) node _sfma_io_in_valid_T_1 = and(io.in.valid, _sfma_io_in_valid_T) node _sfma_io_in_valid_T_2 = and(_sfma_io_in_valid_T_1, io.in.bits.fp_ctrl.fma) connect sfma.io.in.valid, _sfma_io_in_valid_T_2 wire sfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect sfma_io_in_bits_req.ldst, io.in.bits.fp_ctrl.ldst connect sfma_io_in_bits_req.wen, io.in.bits.fp_ctrl.wen connect sfma_io_in_bits_req.ren1, io.in.bits.fp_ctrl.ren1 connect sfma_io_in_bits_req.ren2, io.in.bits.fp_ctrl.ren2 connect sfma_io_in_bits_req.ren3, io.in.bits.fp_ctrl.ren3 connect sfma_io_in_bits_req.swap12, io.in.bits.fp_ctrl.swap12 connect sfma_io_in_bits_req.swap23, io.in.bits.fp_ctrl.swap23 connect sfma_io_in_bits_req.typeTagIn, io.in.bits.fp_ctrl.typeTagIn connect sfma_io_in_bits_req.typeTagOut, io.in.bits.fp_ctrl.typeTagOut connect sfma_io_in_bits_req.fromint, io.in.bits.fp_ctrl.fromint connect sfma_io_in_bits_req.toint, io.in.bits.fp_ctrl.toint connect sfma_io_in_bits_req.fastpipe, io.in.bits.fp_ctrl.fastpipe connect sfma_io_in_bits_req.fma, io.in.bits.fp_ctrl.fma connect sfma_io_in_bits_req.div, io.in.bits.fp_ctrl.div connect sfma_io_in_bits_req.sqrt, io.in.bits.fp_ctrl.sqrt connect sfma_io_in_bits_req.wflags, io.in.bits.fp_ctrl.wflags connect sfma_io_in_bits_req.vec, io.in.bits.fp_ctrl.vec connect sfma_io_in_bits_req.rm, rm node _sfma_io_in_bits_req_in1_prev_unswizzled_T = bits(io.frs1_data, 31, 31) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.frs1_data, 52, 52) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.frs1_data, 30, 0) node sfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1) node sfma_io_in_bits_req_in1_floats_1 = cat(sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in1_floats_1, 15, 15) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in1_floats_1, 23, 23) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in1_floats_1, 14, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in1_floats_0 = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in1_floats_1, 32, 28) node sfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in1_prev_prev_0_1 = and(sfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in1_prev_isbox_T = bits(io.frs1_data, 64, 60) node sfma_io_in_bits_req_in1_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_isbox_T) node sfma_io_in_bits_req_in1_oks_0 = and(sfma_io_in_bits_req_in1_prev_isbox, sfma_io_in_bits_req_in1_prev_prev_0_1) node sfma_io_in_bits_req_in1_oks_1 = and(sfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in1_sign = bits(io.frs1_data, 64, 64) node sfma_io_in_bits_req_in1_fractIn = bits(io.frs1_data, 51, 0) node sfma_io_in_bits_req_in1_expIn = bits(io.frs1_data, 63, 52) node _sfma_io_in_bits_req_in1_fractOut_T = shl(sfma_io_in_bits_req_in1_fractIn, 24) node sfma_io_in_bits_req_in1_fractOut = shr(_sfma_io_in_bits_req_in1_fractOut_T, 53) node sfma_io_in_bits_req_in1_expOut_expCode = bits(sfma_io_in_bits_req_in1_expIn, 11, 9) node _sfma_io_in_bits_req_in1_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in1_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in1_expOut_T = eq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in1_expOut_T_1 = geq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in1_expOut_T_2 = or(_sfma_io_in_bits_req_in1_expOut_T, _sfma_io_in_bits_req_in1_expOut_T_1) node _sfma_io_in_bits_req_in1_expOut_T_3 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in1_expOut_T_4 = cat(sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3) node _sfma_io_in_bits_req_in1_expOut_T_5 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in1_expOut = mux(_sfma_io_in_bits_req_in1_expOut_T_2, _sfma_io_in_bits_req_in1_expOut_T_4, _sfma_io_in_bits_req_in1_expOut_T_5) node sfma_io_in_bits_req_in1_hi = cat(sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut) node sfma_io_in_bits_req_in1_floats_2 = cat(sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut) node _sfma_io_in_bits_req_in1_T = mux(sfma_io_in_bits_req_in1_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in1_T_1 = or(sfma_io_in_bits_req_in1_floats_1, _sfma_io_in_bits_req_in1_T) connect sfma_io_in_bits_req.in1, _sfma_io_in_bits_req_in1_T_1 node _sfma_io_in_bits_req_in2_prev_unswizzled_T = bits(io.frs2_data, 31, 31) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.frs2_data, 52, 52) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.frs2_data, 30, 0) node sfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1) node sfma_io_in_bits_req_in2_floats_1 = cat(sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in2_floats_1, 15, 15) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in2_floats_1, 23, 23) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in2_floats_1, 14, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in2_floats_0 = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in2_floats_1, 32, 28) node sfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in2_prev_prev_0_1 = and(sfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in2_prev_isbox_T = bits(io.frs2_data, 64, 60) node sfma_io_in_bits_req_in2_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_isbox_T) node sfma_io_in_bits_req_in2_oks_0 = and(sfma_io_in_bits_req_in2_prev_isbox, sfma_io_in_bits_req_in2_prev_prev_0_1) node sfma_io_in_bits_req_in2_oks_1 = and(sfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in2_sign = bits(io.frs2_data, 64, 64) node sfma_io_in_bits_req_in2_fractIn = bits(io.frs2_data, 51, 0) node sfma_io_in_bits_req_in2_expIn = bits(io.frs2_data, 63, 52) node _sfma_io_in_bits_req_in2_fractOut_T = shl(sfma_io_in_bits_req_in2_fractIn, 24) node sfma_io_in_bits_req_in2_fractOut = shr(_sfma_io_in_bits_req_in2_fractOut_T, 53) node sfma_io_in_bits_req_in2_expOut_expCode = bits(sfma_io_in_bits_req_in2_expIn, 11, 9) node _sfma_io_in_bits_req_in2_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in2_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in2_expOut_T = eq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in2_expOut_T_1 = geq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in2_expOut_T_2 = or(_sfma_io_in_bits_req_in2_expOut_T, _sfma_io_in_bits_req_in2_expOut_T_1) node _sfma_io_in_bits_req_in2_expOut_T_3 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in2_expOut_T_4 = cat(sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3) node _sfma_io_in_bits_req_in2_expOut_T_5 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in2_expOut = mux(_sfma_io_in_bits_req_in2_expOut_T_2, _sfma_io_in_bits_req_in2_expOut_T_4, _sfma_io_in_bits_req_in2_expOut_T_5) node sfma_io_in_bits_req_in2_hi = cat(sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut) node sfma_io_in_bits_req_in2_floats_2 = cat(sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut) node _sfma_io_in_bits_req_in2_T = mux(sfma_io_in_bits_req_in2_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in2_T_1 = or(sfma_io_in_bits_req_in2_floats_1, _sfma_io_in_bits_req_in2_T) connect sfma_io_in_bits_req.in2, _sfma_io_in_bits_req_in2_T_1 node _sfma_io_in_bits_req_in3_prev_unswizzled_T = bits(io.frs3_data, 31, 31) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.frs3_data, 52, 52) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.frs3_data, 30, 0) node sfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1) node sfma_io_in_bits_req_in3_floats_1 = cat(sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in3_floats_1, 15, 15) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in3_floats_1, 23, 23) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in3_floats_1, 14, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in3_floats_0 = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in3_floats_1, 32, 28) node sfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in3_prev_prev_0_1 = and(sfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in3_prev_isbox_T = bits(io.frs3_data, 64, 60) node sfma_io_in_bits_req_in3_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_isbox_T) node sfma_io_in_bits_req_in3_oks_0 = and(sfma_io_in_bits_req_in3_prev_isbox, sfma_io_in_bits_req_in3_prev_prev_0_1) node sfma_io_in_bits_req_in3_oks_1 = and(sfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in3_sign = bits(io.frs3_data, 64, 64) node sfma_io_in_bits_req_in3_fractIn = bits(io.frs3_data, 51, 0) node sfma_io_in_bits_req_in3_expIn = bits(io.frs3_data, 63, 52) node _sfma_io_in_bits_req_in3_fractOut_T = shl(sfma_io_in_bits_req_in3_fractIn, 24) node sfma_io_in_bits_req_in3_fractOut = shr(_sfma_io_in_bits_req_in3_fractOut_T, 53) node sfma_io_in_bits_req_in3_expOut_expCode = bits(sfma_io_in_bits_req_in3_expIn, 11, 9) node _sfma_io_in_bits_req_in3_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in3_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in3_expOut_T = eq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in3_expOut_T_1 = geq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in3_expOut_T_2 = or(_sfma_io_in_bits_req_in3_expOut_T, _sfma_io_in_bits_req_in3_expOut_T_1) node _sfma_io_in_bits_req_in3_expOut_T_3 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in3_expOut_T_4 = cat(sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3) node _sfma_io_in_bits_req_in3_expOut_T_5 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in3_expOut = mux(_sfma_io_in_bits_req_in3_expOut_T_2, _sfma_io_in_bits_req_in3_expOut_T_4, _sfma_io_in_bits_req_in3_expOut_T_5) node sfma_io_in_bits_req_in3_hi = cat(sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut) node sfma_io_in_bits_req_in3_floats_2 = cat(sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut) node _sfma_io_in_bits_req_in3_T = mux(sfma_io_in_bits_req_in3_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in3_T_1 = or(sfma_io_in_bits_req_in3_floats_1, _sfma_io_in_bits_req_in3_T) connect sfma_io_in_bits_req.in3, _sfma_io_in_bits_req_in3_T_1 node _sfma_io_in_bits_req_typ_T = bits(io.in.bits.inst, 21, 20) connect sfma_io_in_bits_req.typ, _sfma_io_in_bits_req_typ_T node _sfma_io_in_bits_req_fmt_T = bits(io.in.bits.inst, 26, 25) connect sfma_io_in_bits_req.fmt, _sfma_io_in_bits_req_fmt_T node _sfma_io_in_bits_req_fmaCmd_T = bits(io.in.bits.inst, 3, 2) node _sfma_io_in_bits_req_fmaCmd_T_1 = eq(io.in.bits.fp_ctrl.ren3, UInt<1>(0h0)) node _sfma_io_in_bits_req_fmaCmd_T_2 = bits(io.in.bits.inst, 27, 27) node _sfma_io_in_bits_req_fmaCmd_T_3 = and(_sfma_io_in_bits_req_fmaCmd_T_1, _sfma_io_in_bits_req_fmaCmd_T_2) node _sfma_io_in_bits_req_fmaCmd_T_4 = or(_sfma_io_in_bits_req_fmaCmd_T, _sfma_io_in_bits_req_fmaCmd_T_3) connect sfma_io_in_bits_req.fmaCmd, _sfma_io_in_bits_req_fmaCmd_T_4 connect sfma_io_in_bits_req.vec, UInt<1>(0h0) connect sfma.io.in.bits.in3, sfma_io_in_bits_req.in3 connect sfma.io.in.bits.in2, sfma_io_in_bits_req.in2 connect sfma.io.in.bits.in1, sfma_io_in_bits_req.in1 connect sfma.io.in.bits.fmt, sfma_io_in_bits_req.fmt connect sfma.io.in.bits.typ, sfma_io_in_bits_req.typ connect sfma.io.in.bits.fmaCmd, sfma_io_in_bits_req.fmaCmd connect sfma.io.in.bits.rm, sfma_io_in_bits_req.rm connect sfma.io.in.bits.vec, sfma_io_in_bits_req.vec connect sfma.io.in.bits.wflags, sfma_io_in_bits_req.wflags connect sfma.io.in.bits.sqrt, sfma_io_in_bits_req.sqrt connect sfma.io.in.bits.div, sfma_io_in_bits_req.div connect sfma.io.in.bits.fma, sfma_io_in_bits_req.fma connect sfma.io.in.bits.fastpipe, sfma_io_in_bits_req.fastpipe connect sfma.io.in.bits.toint, sfma_io_in_bits_req.toint connect sfma.io.in.bits.fromint, sfma_io_in_bits_req.fromint connect sfma.io.in.bits.typeTagOut, sfma_io_in_bits_req.typeTagOut connect sfma.io.in.bits.typeTagIn, sfma_io_in_bits_req.typeTagIn connect sfma.io.in.bits.swap23, sfma_io_in_bits_req.swap23 connect sfma.io.in.bits.swap12, sfma_io_in_bits_req.swap12 connect sfma.io.in.bits.ren3, sfma_io_in_bits_req.ren3 connect sfma.io.in.bits.ren2, sfma_io_in_bits_req.ren2 connect sfma.io.in.bits.ren1, sfma_io_in_bits_req.ren1 connect sfma.io.in.bits.wen, sfma_io_in_bits_req.wen connect sfma.io.in.bits.ldst, sfma_io_in_bits_req.ldst node _hfma_io_in_valid_T = eq(io.in.bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _hfma_io_in_valid_T_1 = and(io.in.valid, _hfma_io_in_valid_T) node _hfma_io_in_valid_T_2 = and(_hfma_io_in_valid_T_1, io.in.bits.fp_ctrl.fma) connect hfma.io.in.valid, _hfma_io_in_valid_T_2 wire hfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect hfma_io_in_bits_req.ldst, io.in.bits.fp_ctrl.ldst connect hfma_io_in_bits_req.wen, io.in.bits.fp_ctrl.wen connect hfma_io_in_bits_req.ren1, io.in.bits.fp_ctrl.ren1 connect hfma_io_in_bits_req.ren2, io.in.bits.fp_ctrl.ren2 connect hfma_io_in_bits_req.ren3, io.in.bits.fp_ctrl.ren3 connect hfma_io_in_bits_req.swap12, io.in.bits.fp_ctrl.swap12 connect hfma_io_in_bits_req.swap23, io.in.bits.fp_ctrl.swap23 connect hfma_io_in_bits_req.typeTagIn, io.in.bits.fp_ctrl.typeTagIn connect hfma_io_in_bits_req.typeTagOut, io.in.bits.fp_ctrl.typeTagOut connect hfma_io_in_bits_req.fromint, io.in.bits.fp_ctrl.fromint connect hfma_io_in_bits_req.toint, io.in.bits.fp_ctrl.toint connect hfma_io_in_bits_req.fastpipe, io.in.bits.fp_ctrl.fastpipe connect hfma_io_in_bits_req.fma, io.in.bits.fp_ctrl.fma connect hfma_io_in_bits_req.div, io.in.bits.fp_ctrl.div connect hfma_io_in_bits_req.sqrt, io.in.bits.fp_ctrl.sqrt connect hfma_io_in_bits_req.wflags, io.in.bits.fp_ctrl.wflags connect hfma_io_in_bits_req.vec, io.in.bits.fp_ctrl.vec connect hfma_io_in_bits_req.rm, rm node _hfma_io_in_bits_req_in1_prev_unswizzled_T = bits(io.frs1_data, 31, 31) node _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.frs1_data, 52, 52) node _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.frs1_data, 30, 0) node hfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1) node hfma_io_in_bits_req_in1_prev_unswizzled = cat(hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in1_floats_0 = cat(hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in1_prev_prev_0_1 = and(hfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in1_prev_prev_sign = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in1_prev_prev_fractIn = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in1_prev_prev_expIn = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in1_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in1_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in1_prev_prev_expOut_T, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in1_prev_prev_expOut = mux(_hfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in1_prev_prev_hi = cat(hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut) node hfma_io_in_bits_req_in1_floats_1 = cat(hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut) node _hfma_io_in_bits_req_in1_prev_isbox_T = bits(io.frs1_data, 64, 60) node hfma_io_in_bits_req_in1_prev_isbox = andr(_hfma_io_in_bits_req_in1_prev_isbox_T) node hfma_io_in_bits_req_in1_oks_0 = and(hfma_io_in_bits_req_in1_prev_isbox, hfma_io_in_bits_req_in1_prev_prev_0_1) node hfma_io_in_bits_req_in1_oks_1 = and(hfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in1_sign = bits(io.frs1_data, 64, 64) node hfma_io_in_bits_req_in1_fractIn = bits(io.frs1_data, 51, 0) node hfma_io_in_bits_req_in1_expIn = bits(io.frs1_data, 63, 52) node _hfma_io_in_bits_req_in1_fractOut_T = shl(hfma_io_in_bits_req_in1_fractIn, 11) node hfma_io_in_bits_req_in1_fractOut = shr(_hfma_io_in_bits_req_in1_fractOut_T, 53) node hfma_io_in_bits_req_in1_expOut_expCode = bits(hfma_io_in_bits_req_in1_expIn, 11, 9) node _hfma_io_in_bits_req_in1_expOut_commonCase_T = add(hfma_io_in_bits_req_in1_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in1_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in1_expOut_commonCase = tail(_hfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in1_expOut_T = eq(hfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in1_expOut_T_1 = geq(hfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in1_expOut_T_2 = or(_hfma_io_in_bits_req_in1_expOut_T, _hfma_io_in_bits_req_in1_expOut_T_1) node _hfma_io_in_bits_req_in1_expOut_T_3 = bits(hfma_io_in_bits_req_in1_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in1_expOut_T_4 = cat(hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3) node _hfma_io_in_bits_req_in1_expOut_T_5 = bits(hfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in1_expOut = mux(_hfma_io_in_bits_req_in1_expOut_T_2, _hfma_io_in_bits_req_in1_expOut_T_4, _hfma_io_in_bits_req_in1_expOut_T_5) node hfma_io_in_bits_req_in1_hi = cat(hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut) node hfma_io_in_bits_req_in1_floats_2 = cat(hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut) node _hfma_io_in_bits_req_in1_T = mux(hfma_io_in_bits_req_in1_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in1_T_1 = or(hfma_io_in_bits_req_in1_floats_0, _hfma_io_in_bits_req_in1_T) connect hfma_io_in_bits_req.in1, _hfma_io_in_bits_req_in1_T_1 node _hfma_io_in_bits_req_in2_prev_unswizzled_T = bits(io.frs2_data, 31, 31) node _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.frs2_data, 52, 52) node _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.frs2_data, 30, 0) node hfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1) node hfma_io_in_bits_req_in2_prev_unswizzled = cat(hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in2_floats_0 = cat(hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in2_prev_prev_0_1 = and(hfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in2_prev_prev_sign = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in2_prev_prev_fractIn = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in2_prev_prev_expIn = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in2_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in2_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in2_prev_prev_expOut_T, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in2_prev_prev_expOut = mux(_hfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in2_prev_prev_hi = cat(hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut) node hfma_io_in_bits_req_in2_floats_1 = cat(hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut) node _hfma_io_in_bits_req_in2_prev_isbox_T = bits(io.frs2_data, 64, 60) node hfma_io_in_bits_req_in2_prev_isbox = andr(_hfma_io_in_bits_req_in2_prev_isbox_T) node hfma_io_in_bits_req_in2_oks_0 = and(hfma_io_in_bits_req_in2_prev_isbox, hfma_io_in_bits_req_in2_prev_prev_0_1) node hfma_io_in_bits_req_in2_oks_1 = and(hfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in2_sign = bits(io.frs2_data, 64, 64) node hfma_io_in_bits_req_in2_fractIn = bits(io.frs2_data, 51, 0) node hfma_io_in_bits_req_in2_expIn = bits(io.frs2_data, 63, 52) node _hfma_io_in_bits_req_in2_fractOut_T = shl(hfma_io_in_bits_req_in2_fractIn, 11) node hfma_io_in_bits_req_in2_fractOut = shr(_hfma_io_in_bits_req_in2_fractOut_T, 53) node hfma_io_in_bits_req_in2_expOut_expCode = bits(hfma_io_in_bits_req_in2_expIn, 11, 9) node _hfma_io_in_bits_req_in2_expOut_commonCase_T = add(hfma_io_in_bits_req_in2_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in2_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in2_expOut_commonCase = tail(_hfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in2_expOut_T = eq(hfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in2_expOut_T_1 = geq(hfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in2_expOut_T_2 = or(_hfma_io_in_bits_req_in2_expOut_T, _hfma_io_in_bits_req_in2_expOut_T_1) node _hfma_io_in_bits_req_in2_expOut_T_3 = bits(hfma_io_in_bits_req_in2_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in2_expOut_T_4 = cat(hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3) node _hfma_io_in_bits_req_in2_expOut_T_5 = bits(hfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in2_expOut = mux(_hfma_io_in_bits_req_in2_expOut_T_2, _hfma_io_in_bits_req_in2_expOut_T_4, _hfma_io_in_bits_req_in2_expOut_T_5) node hfma_io_in_bits_req_in2_hi = cat(hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut) node hfma_io_in_bits_req_in2_floats_2 = cat(hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut) node _hfma_io_in_bits_req_in2_T = mux(hfma_io_in_bits_req_in2_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in2_T_1 = or(hfma_io_in_bits_req_in2_floats_0, _hfma_io_in_bits_req_in2_T) connect hfma_io_in_bits_req.in2, _hfma_io_in_bits_req_in2_T_1 node _hfma_io_in_bits_req_in3_prev_unswizzled_T = bits(io.frs3_data, 31, 31) node _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.frs3_data, 52, 52) node _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.frs3_data, 30, 0) node hfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1) node hfma_io_in_bits_req_in3_prev_unswizzled = cat(hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in3_floats_0 = cat(hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in3_prev_prev_0_1 = and(hfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in3_prev_prev_sign = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in3_prev_prev_fractIn = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in3_prev_prev_expIn = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in3_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in3_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in3_prev_prev_expOut_T, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in3_prev_prev_expOut = mux(_hfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in3_prev_prev_hi = cat(hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut) node hfma_io_in_bits_req_in3_floats_1 = cat(hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut) node _hfma_io_in_bits_req_in3_prev_isbox_T = bits(io.frs3_data, 64, 60) node hfma_io_in_bits_req_in3_prev_isbox = andr(_hfma_io_in_bits_req_in3_prev_isbox_T) node hfma_io_in_bits_req_in3_oks_0 = and(hfma_io_in_bits_req_in3_prev_isbox, hfma_io_in_bits_req_in3_prev_prev_0_1) node hfma_io_in_bits_req_in3_oks_1 = and(hfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in3_sign = bits(io.frs3_data, 64, 64) node hfma_io_in_bits_req_in3_fractIn = bits(io.frs3_data, 51, 0) node hfma_io_in_bits_req_in3_expIn = bits(io.frs3_data, 63, 52) node _hfma_io_in_bits_req_in3_fractOut_T = shl(hfma_io_in_bits_req_in3_fractIn, 11) node hfma_io_in_bits_req_in3_fractOut = shr(_hfma_io_in_bits_req_in3_fractOut_T, 53) node hfma_io_in_bits_req_in3_expOut_expCode = bits(hfma_io_in_bits_req_in3_expIn, 11, 9) node _hfma_io_in_bits_req_in3_expOut_commonCase_T = add(hfma_io_in_bits_req_in3_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in3_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in3_expOut_commonCase = tail(_hfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in3_expOut_T = eq(hfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in3_expOut_T_1 = geq(hfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in3_expOut_T_2 = or(_hfma_io_in_bits_req_in3_expOut_T, _hfma_io_in_bits_req_in3_expOut_T_1) node _hfma_io_in_bits_req_in3_expOut_T_3 = bits(hfma_io_in_bits_req_in3_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in3_expOut_T_4 = cat(hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3) node _hfma_io_in_bits_req_in3_expOut_T_5 = bits(hfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in3_expOut = mux(_hfma_io_in_bits_req_in3_expOut_T_2, _hfma_io_in_bits_req_in3_expOut_T_4, _hfma_io_in_bits_req_in3_expOut_T_5) node hfma_io_in_bits_req_in3_hi = cat(hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut) node hfma_io_in_bits_req_in3_floats_2 = cat(hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut) node _hfma_io_in_bits_req_in3_T = mux(hfma_io_in_bits_req_in3_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in3_T_1 = or(hfma_io_in_bits_req_in3_floats_0, _hfma_io_in_bits_req_in3_T) connect hfma_io_in_bits_req.in3, _hfma_io_in_bits_req_in3_T_1 node _hfma_io_in_bits_req_typ_T = bits(io.in.bits.inst, 21, 20) connect hfma_io_in_bits_req.typ, _hfma_io_in_bits_req_typ_T node _hfma_io_in_bits_req_fmt_T = bits(io.in.bits.inst, 26, 25) connect hfma_io_in_bits_req.fmt, _hfma_io_in_bits_req_fmt_T node _hfma_io_in_bits_req_fmaCmd_T = bits(io.in.bits.inst, 3, 2) node _hfma_io_in_bits_req_fmaCmd_T_1 = eq(io.in.bits.fp_ctrl.ren3, UInt<1>(0h0)) node _hfma_io_in_bits_req_fmaCmd_T_2 = bits(io.in.bits.inst, 27, 27) node _hfma_io_in_bits_req_fmaCmd_T_3 = and(_hfma_io_in_bits_req_fmaCmd_T_1, _hfma_io_in_bits_req_fmaCmd_T_2) node _hfma_io_in_bits_req_fmaCmd_T_4 = or(_hfma_io_in_bits_req_fmaCmd_T, _hfma_io_in_bits_req_fmaCmd_T_3) connect hfma_io_in_bits_req.fmaCmd, _hfma_io_in_bits_req_fmaCmd_T_4 connect hfma_io_in_bits_req.vec, UInt<1>(0h0) connect hfma.io.in.bits.in3, hfma_io_in_bits_req.in3 connect hfma.io.in.bits.in2, hfma_io_in_bits_req.in2 connect hfma.io.in.bits.in1, hfma_io_in_bits_req.in1 connect hfma.io.in.bits.fmt, hfma_io_in_bits_req.fmt connect hfma.io.in.bits.typ, hfma_io_in_bits_req.typ connect hfma.io.in.bits.fmaCmd, hfma_io_in_bits_req.fmaCmd connect hfma.io.in.bits.rm, hfma_io_in_bits_req.rm connect hfma.io.in.bits.vec, hfma_io_in_bits_req.vec connect hfma.io.in.bits.wflags, hfma_io_in_bits_req.wflags connect hfma.io.in.bits.sqrt, hfma_io_in_bits_req.sqrt connect hfma.io.in.bits.div, hfma_io_in_bits_req.div connect hfma.io.in.bits.fma, hfma_io_in_bits_req.fma connect hfma.io.in.bits.fastpipe, hfma_io_in_bits_req.fastpipe connect hfma.io.in.bits.toint, hfma_io_in_bits_req.toint connect hfma.io.in.bits.fromint, hfma_io_in_bits_req.fromint connect hfma.io.in.bits.typeTagOut, hfma_io_in_bits_req.typeTagOut connect hfma.io.in.bits.typeTagIn, hfma_io_in_bits_req.typeTagIn connect hfma.io.in.bits.swap23, hfma_io_in_bits_req.swap23 connect hfma.io.in.bits.swap12, hfma_io_in_bits_req.swap12 connect hfma.io.in.bits.ren3, hfma_io_in_bits_req.ren3 connect hfma.io.in.bits.ren2, hfma_io_in_bits_req.ren2 connect hfma.io.in.bits.ren1, hfma_io_in_bits_req.ren1 connect hfma.io.in.bits.wen, hfma_io_in_bits_req.wen connect hfma.io.in.bits.ldst, hfma_io_in_bits_req.ldst inst ifpu of IntToFP connect ifpu.clock, clock connect ifpu.reset, reset node _ifpu_io_in_valid_T = and(io.in.valid, io.in.bits.fp_ctrl.fromint) connect ifpu.io.in.valid, _ifpu_io_in_valid_T wire ifpu_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect ifpu_io_in_bits_req.ldst, io.in.bits.fp_ctrl.ldst connect ifpu_io_in_bits_req.wen, io.in.bits.fp_ctrl.wen connect ifpu_io_in_bits_req.ren1, io.in.bits.fp_ctrl.ren1 connect ifpu_io_in_bits_req.ren2, io.in.bits.fp_ctrl.ren2 connect ifpu_io_in_bits_req.ren3, io.in.bits.fp_ctrl.ren3 connect ifpu_io_in_bits_req.swap12, io.in.bits.fp_ctrl.swap12 connect ifpu_io_in_bits_req.swap23, io.in.bits.fp_ctrl.swap23 connect ifpu_io_in_bits_req.typeTagIn, io.in.bits.fp_ctrl.typeTagIn connect ifpu_io_in_bits_req.typeTagOut, io.in.bits.fp_ctrl.typeTagOut connect ifpu_io_in_bits_req.fromint, io.in.bits.fp_ctrl.fromint connect ifpu_io_in_bits_req.toint, io.in.bits.fp_ctrl.toint connect ifpu_io_in_bits_req.fastpipe, io.in.bits.fp_ctrl.fastpipe connect ifpu_io_in_bits_req.fma, io.in.bits.fp_ctrl.fma connect ifpu_io_in_bits_req.div, io.in.bits.fp_ctrl.div connect ifpu_io_in_bits_req.sqrt, io.in.bits.fp_ctrl.sqrt connect ifpu_io_in_bits_req.wflags, io.in.bits.fp_ctrl.wflags connect ifpu_io_in_bits_req.vec, io.in.bits.fp_ctrl.vec connect ifpu_io_in_bits_req.rm, rm node _ifpu_io_in_bits_req_in1_prev_unswizzled_T = bits(io.frs1_data, 31, 31) node _ifpu_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.frs1_data, 52, 52) node _ifpu_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.frs1_data, 30, 0) node ifpu_io_in_bits_req_in1_prev_unswizzled_hi = cat(_ifpu_io_in_bits_req_in1_prev_unswizzled_T, _ifpu_io_in_bits_req_in1_prev_unswizzled_T_1) node ifpu_io_in_bits_req_in1_prev_unswizzled = cat(ifpu_io_in_bits_req_in1_prev_unswizzled_hi, _ifpu_io_in_bits_req_in1_prev_unswizzled_T_2) node _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(ifpu_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(ifpu_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(ifpu_io_in_bits_req_in1_prev_unswizzled, 14, 0) node ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node ifpu_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_sign, ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node ifpu_io_in_bits_req_in1_floats_0 = cat(ifpu_io_in_bits_req_in1_prev_prev_prev_prev_hi, ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _ifpu_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(ifpu_io_in_bits_req_in1_prev_unswizzled, 32, 28) node ifpu_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_ifpu_io_in_bits_req_in1_prev_prev_prev_isbox_T) node ifpu_io_in_bits_req_in1_prev_prev_0_1 = and(ifpu_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node ifpu_io_in_bits_req_in1_prev_prev_sign = bits(ifpu_io_in_bits_req_in1_prev_unswizzled, 32, 32) node ifpu_io_in_bits_req_in1_prev_prev_fractIn = bits(ifpu_io_in_bits_req_in1_prev_unswizzled, 22, 0) node ifpu_io_in_bits_req_in1_prev_prev_expIn = bits(ifpu_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _ifpu_io_in_bits_req_in1_prev_prev_fractOut_T = shl(ifpu_io_in_bits_req_in1_prev_prev_fractIn, 53) node ifpu_io_in_bits_req_in1_prev_prev_fractOut = shr(_ifpu_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(ifpu_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(ifpu_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_T = eq(ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_ifpu_io_in_bits_req_in1_prev_prev_expOut_T, _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_1) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_3) node _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node ifpu_io_in_bits_req_in1_prev_prev_expOut = mux(_ifpu_io_in_bits_req_in1_prev_prev_expOut_T_2, _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_4, _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_5) node ifpu_io_in_bits_req_in1_prev_prev_hi = cat(ifpu_io_in_bits_req_in1_prev_prev_sign, ifpu_io_in_bits_req_in1_prev_prev_expOut) node ifpu_io_in_bits_req_in1_floats_1 = cat(ifpu_io_in_bits_req_in1_prev_prev_hi, ifpu_io_in_bits_req_in1_prev_prev_fractOut) node _ifpu_io_in_bits_req_in1_prev_isbox_T = bits(io.frs1_data, 64, 60) node ifpu_io_in_bits_req_in1_prev_isbox = andr(_ifpu_io_in_bits_req_in1_prev_isbox_T) node ifpu_io_in_bits_req_in1_oks_0 = and(ifpu_io_in_bits_req_in1_prev_isbox, ifpu_io_in_bits_req_in1_prev_prev_0_1) node ifpu_io_in_bits_req_in1_oks_1 = and(ifpu_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in1_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in1_T_1 = mux(_ifpu_io_in_bits_req_in1_T, ifpu_io_in_bits_req_in1_oks_1, ifpu_io_in_bits_req_in1_oks_0) node _ifpu_io_in_bits_req_in1_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _ifpu_io_in_bits_req_in1_T_3 = mux(_ifpu_io_in_bits_req_in1_T_2, UInt<1>(0h1), _ifpu_io_in_bits_req_in1_T_1) node _ifpu_io_in_bits_req_in1_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _ifpu_io_in_bits_req_in1_T_5 = mux(_ifpu_io_in_bits_req_in1_T_4, UInt<1>(0h1), _ifpu_io_in_bits_req_in1_T_3) node _ifpu_io_in_bits_req_in1_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in1_T_7 = mux(_ifpu_io_in_bits_req_in1_T_6, ifpu_io_in_bits_req_in1_floats_1, ifpu_io_in_bits_req_in1_floats_0) node _ifpu_io_in_bits_req_in1_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _ifpu_io_in_bits_req_in1_T_9 = mux(_ifpu_io_in_bits_req_in1_T_8, io.frs1_data, _ifpu_io_in_bits_req_in1_T_7) node _ifpu_io_in_bits_req_in1_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _ifpu_io_in_bits_req_in1_T_11 = mux(_ifpu_io_in_bits_req_in1_T_10, io.frs1_data, _ifpu_io_in_bits_req_in1_T_9) node _ifpu_io_in_bits_req_in1_T_12 = mux(_ifpu_io_in_bits_req_in1_T_5, _ifpu_io_in_bits_req_in1_T_11, UInt<65>(0he008000000000000)) connect ifpu_io_in_bits_req.in1, _ifpu_io_in_bits_req_in1_T_12 node _ifpu_io_in_bits_req_in2_prev_unswizzled_T = bits(io.frs2_data, 31, 31) node _ifpu_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.frs2_data, 52, 52) node _ifpu_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.frs2_data, 30, 0) node ifpu_io_in_bits_req_in2_prev_unswizzled_hi = cat(_ifpu_io_in_bits_req_in2_prev_unswizzled_T, _ifpu_io_in_bits_req_in2_prev_unswizzled_T_1) node ifpu_io_in_bits_req_in2_prev_unswizzled = cat(ifpu_io_in_bits_req_in2_prev_unswizzled_hi, _ifpu_io_in_bits_req_in2_prev_unswizzled_T_2) node _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(ifpu_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(ifpu_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(ifpu_io_in_bits_req_in2_prev_unswizzled, 14, 0) node ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node ifpu_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_sign, ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node ifpu_io_in_bits_req_in2_floats_0 = cat(ifpu_io_in_bits_req_in2_prev_prev_prev_prev_hi, ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _ifpu_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(ifpu_io_in_bits_req_in2_prev_unswizzled, 32, 28) node ifpu_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_ifpu_io_in_bits_req_in2_prev_prev_prev_isbox_T) node ifpu_io_in_bits_req_in2_prev_prev_0_1 = and(ifpu_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node ifpu_io_in_bits_req_in2_prev_prev_sign = bits(ifpu_io_in_bits_req_in2_prev_unswizzled, 32, 32) node ifpu_io_in_bits_req_in2_prev_prev_fractIn = bits(ifpu_io_in_bits_req_in2_prev_unswizzled, 22, 0) node ifpu_io_in_bits_req_in2_prev_prev_expIn = bits(ifpu_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _ifpu_io_in_bits_req_in2_prev_prev_fractOut_T = shl(ifpu_io_in_bits_req_in2_prev_prev_fractIn, 53) node ifpu_io_in_bits_req_in2_prev_prev_fractOut = shr(_ifpu_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(ifpu_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(ifpu_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_T = eq(ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_ifpu_io_in_bits_req_in2_prev_prev_expOut_T, _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_1) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_3) node _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node ifpu_io_in_bits_req_in2_prev_prev_expOut = mux(_ifpu_io_in_bits_req_in2_prev_prev_expOut_T_2, _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_4, _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_5) node ifpu_io_in_bits_req_in2_prev_prev_hi = cat(ifpu_io_in_bits_req_in2_prev_prev_sign, ifpu_io_in_bits_req_in2_prev_prev_expOut) node ifpu_io_in_bits_req_in2_floats_1 = cat(ifpu_io_in_bits_req_in2_prev_prev_hi, ifpu_io_in_bits_req_in2_prev_prev_fractOut) node _ifpu_io_in_bits_req_in2_prev_isbox_T = bits(io.frs2_data, 64, 60) node ifpu_io_in_bits_req_in2_prev_isbox = andr(_ifpu_io_in_bits_req_in2_prev_isbox_T) node ifpu_io_in_bits_req_in2_oks_0 = and(ifpu_io_in_bits_req_in2_prev_isbox, ifpu_io_in_bits_req_in2_prev_prev_0_1) node ifpu_io_in_bits_req_in2_oks_1 = and(ifpu_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in2_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in2_T_1 = mux(_ifpu_io_in_bits_req_in2_T, ifpu_io_in_bits_req_in2_oks_1, ifpu_io_in_bits_req_in2_oks_0) node _ifpu_io_in_bits_req_in2_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _ifpu_io_in_bits_req_in2_T_3 = mux(_ifpu_io_in_bits_req_in2_T_2, UInt<1>(0h1), _ifpu_io_in_bits_req_in2_T_1) node _ifpu_io_in_bits_req_in2_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _ifpu_io_in_bits_req_in2_T_5 = mux(_ifpu_io_in_bits_req_in2_T_4, UInt<1>(0h1), _ifpu_io_in_bits_req_in2_T_3) node _ifpu_io_in_bits_req_in2_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in2_T_7 = mux(_ifpu_io_in_bits_req_in2_T_6, ifpu_io_in_bits_req_in2_floats_1, ifpu_io_in_bits_req_in2_floats_0) node _ifpu_io_in_bits_req_in2_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _ifpu_io_in_bits_req_in2_T_9 = mux(_ifpu_io_in_bits_req_in2_T_8, io.frs2_data, _ifpu_io_in_bits_req_in2_T_7) node _ifpu_io_in_bits_req_in2_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _ifpu_io_in_bits_req_in2_T_11 = mux(_ifpu_io_in_bits_req_in2_T_10, io.frs2_data, _ifpu_io_in_bits_req_in2_T_9) node _ifpu_io_in_bits_req_in2_T_12 = mux(_ifpu_io_in_bits_req_in2_T_5, _ifpu_io_in_bits_req_in2_T_11, UInt<65>(0he008000000000000)) connect ifpu_io_in_bits_req.in2, _ifpu_io_in_bits_req_in2_T_12 node _ifpu_io_in_bits_req_in3_prev_unswizzled_T = bits(io.frs3_data, 31, 31) node _ifpu_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.frs3_data, 52, 52) node _ifpu_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.frs3_data, 30, 0) node ifpu_io_in_bits_req_in3_prev_unswizzled_hi = cat(_ifpu_io_in_bits_req_in3_prev_unswizzled_T, _ifpu_io_in_bits_req_in3_prev_unswizzled_T_1) node ifpu_io_in_bits_req_in3_prev_unswizzled = cat(ifpu_io_in_bits_req_in3_prev_unswizzled_hi, _ifpu_io_in_bits_req_in3_prev_unswizzled_T_2) node _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(ifpu_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(ifpu_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(ifpu_io_in_bits_req_in3_prev_unswizzled, 14, 0) node ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node ifpu_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_sign, ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node ifpu_io_in_bits_req_in3_floats_0 = cat(ifpu_io_in_bits_req_in3_prev_prev_prev_prev_hi, ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _ifpu_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(ifpu_io_in_bits_req_in3_prev_unswizzled, 32, 28) node ifpu_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_ifpu_io_in_bits_req_in3_prev_prev_prev_isbox_T) node ifpu_io_in_bits_req_in3_prev_prev_0_1 = and(ifpu_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node ifpu_io_in_bits_req_in3_prev_prev_sign = bits(ifpu_io_in_bits_req_in3_prev_unswizzled, 32, 32) node ifpu_io_in_bits_req_in3_prev_prev_fractIn = bits(ifpu_io_in_bits_req_in3_prev_unswizzled, 22, 0) node ifpu_io_in_bits_req_in3_prev_prev_expIn = bits(ifpu_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _ifpu_io_in_bits_req_in3_prev_prev_fractOut_T = shl(ifpu_io_in_bits_req_in3_prev_prev_fractIn, 53) node ifpu_io_in_bits_req_in3_prev_prev_fractOut = shr(_ifpu_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(ifpu_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(ifpu_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_T = eq(ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_ifpu_io_in_bits_req_in3_prev_prev_expOut_T, _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_1) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_3) node _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node ifpu_io_in_bits_req_in3_prev_prev_expOut = mux(_ifpu_io_in_bits_req_in3_prev_prev_expOut_T_2, _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_4, _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_5) node ifpu_io_in_bits_req_in3_prev_prev_hi = cat(ifpu_io_in_bits_req_in3_prev_prev_sign, ifpu_io_in_bits_req_in3_prev_prev_expOut) node ifpu_io_in_bits_req_in3_floats_1 = cat(ifpu_io_in_bits_req_in3_prev_prev_hi, ifpu_io_in_bits_req_in3_prev_prev_fractOut) node _ifpu_io_in_bits_req_in3_prev_isbox_T = bits(io.frs3_data, 64, 60) node ifpu_io_in_bits_req_in3_prev_isbox = andr(_ifpu_io_in_bits_req_in3_prev_isbox_T) node ifpu_io_in_bits_req_in3_oks_0 = and(ifpu_io_in_bits_req_in3_prev_isbox, ifpu_io_in_bits_req_in3_prev_prev_0_1) node ifpu_io_in_bits_req_in3_oks_1 = and(ifpu_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in3_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in3_T_1 = mux(_ifpu_io_in_bits_req_in3_T, ifpu_io_in_bits_req_in3_oks_1, ifpu_io_in_bits_req_in3_oks_0) node _ifpu_io_in_bits_req_in3_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _ifpu_io_in_bits_req_in3_T_3 = mux(_ifpu_io_in_bits_req_in3_T_2, UInt<1>(0h1), _ifpu_io_in_bits_req_in3_T_1) node _ifpu_io_in_bits_req_in3_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _ifpu_io_in_bits_req_in3_T_5 = mux(_ifpu_io_in_bits_req_in3_T_4, UInt<1>(0h1), _ifpu_io_in_bits_req_in3_T_3) node _ifpu_io_in_bits_req_in3_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _ifpu_io_in_bits_req_in3_T_7 = mux(_ifpu_io_in_bits_req_in3_T_6, ifpu_io_in_bits_req_in3_floats_1, ifpu_io_in_bits_req_in3_floats_0) node _ifpu_io_in_bits_req_in3_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _ifpu_io_in_bits_req_in3_T_9 = mux(_ifpu_io_in_bits_req_in3_T_8, io.frs3_data, _ifpu_io_in_bits_req_in3_T_7) node _ifpu_io_in_bits_req_in3_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _ifpu_io_in_bits_req_in3_T_11 = mux(_ifpu_io_in_bits_req_in3_T_10, io.frs3_data, _ifpu_io_in_bits_req_in3_T_9) node _ifpu_io_in_bits_req_in3_T_12 = mux(_ifpu_io_in_bits_req_in3_T_5, _ifpu_io_in_bits_req_in3_T_11, UInt<65>(0he008000000000000)) connect ifpu_io_in_bits_req.in3, _ifpu_io_in_bits_req_in3_T_12 node _ifpu_io_in_bits_req_typ_T = bits(io.in.bits.inst, 21, 20) connect ifpu_io_in_bits_req.typ, _ifpu_io_in_bits_req_typ_T node _ifpu_io_in_bits_req_fmt_T = bits(io.in.bits.inst, 26, 25) connect ifpu_io_in_bits_req.fmt, _ifpu_io_in_bits_req_fmt_T node _ifpu_io_in_bits_req_fmaCmd_T = bits(io.in.bits.inst, 3, 2) node _ifpu_io_in_bits_req_fmaCmd_T_1 = eq(io.in.bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ifpu_io_in_bits_req_fmaCmd_T_2 = bits(io.in.bits.inst, 27, 27) node _ifpu_io_in_bits_req_fmaCmd_T_3 = and(_ifpu_io_in_bits_req_fmaCmd_T_1, _ifpu_io_in_bits_req_fmaCmd_T_2) node _ifpu_io_in_bits_req_fmaCmd_T_4 = or(_ifpu_io_in_bits_req_fmaCmd_T, _ifpu_io_in_bits_req_fmaCmd_T_3) connect ifpu_io_in_bits_req.fmaCmd, _ifpu_io_in_bits_req_fmaCmd_T_4 connect ifpu_io_in_bits_req.vec, UInt<1>(0h0) connect ifpu.io.in.bits.in1, ifpu_io_in_bits_req.in1 connect ifpu.io.in.bits.typ, ifpu_io_in_bits_req.typ connect ifpu.io.in.bits.rm, ifpu_io_in_bits_req.rm connect ifpu.io.in.bits.vec, ifpu_io_in_bits_req.vec connect ifpu.io.in.bits.wflags, ifpu_io_in_bits_req.wflags connect ifpu.io.in.bits.sqrt, ifpu_io_in_bits_req.sqrt connect ifpu.io.in.bits.div, ifpu_io_in_bits_req.div connect ifpu.io.in.bits.fma, ifpu_io_in_bits_req.fma connect ifpu.io.in.bits.fastpipe, ifpu_io_in_bits_req.fastpipe connect ifpu.io.in.bits.toint, ifpu_io_in_bits_req.toint connect ifpu.io.in.bits.fromint, ifpu_io_in_bits_req.fromint connect ifpu.io.in.bits.typeTagOut, ifpu_io_in_bits_req.typeTagOut connect ifpu.io.in.bits.typeTagIn, ifpu_io_in_bits_req.typeTagIn connect ifpu.io.in.bits.swap23, ifpu_io_in_bits_req.swap23 connect ifpu.io.in.bits.swap12, ifpu_io_in_bits_req.swap12 connect ifpu.io.in.bits.ren3, ifpu_io_in_bits_req.ren3 connect ifpu.io.in.bits.ren2, ifpu_io_in_bits_req.ren2 connect ifpu.io.in.bits.ren1, ifpu_io_in_bits_req.ren1 connect ifpu.io.in.bits.wen, ifpu_io_in_bits_req.wen connect ifpu.io.in.bits.ldst, ifpu_io_in_bits_req.ldst connect ifpu.io.in.bits.in1, io.in.bits.rs1_data inst fpmu of FPToFP connect fpmu.clock, clock connect fpmu.reset, reset connect fpmu.io.lt, fpiu.io.out.bits.lt node _fpmu_io_in_valid_T = and(io.in.valid, io.in.bits.fp_ctrl.fastpipe) connect fpmu.io.in.valid, _fpmu_io_in_valid_T wire fpmu_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect fpmu_io_in_bits_req.ldst, io.in.bits.fp_ctrl.ldst connect fpmu_io_in_bits_req.wen, io.in.bits.fp_ctrl.wen connect fpmu_io_in_bits_req.ren1, io.in.bits.fp_ctrl.ren1 connect fpmu_io_in_bits_req.ren2, io.in.bits.fp_ctrl.ren2 connect fpmu_io_in_bits_req.ren3, io.in.bits.fp_ctrl.ren3 connect fpmu_io_in_bits_req.swap12, io.in.bits.fp_ctrl.swap12 connect fpmu_io_in_bits_req.swap23, io.in.bits.fp_ctrl.swap23 connect fpmu_io_in_bits_req.typeTagIn, io.in.bits.fp_ctrl.typeTagIn connect fpmu_io_in_bits_req.typeTagOut, io.in.bits.fp_ctrl.typeTagOut connect fpmu_io_in_bits_req.fromint, io.in.bits.fp_ctrl.fromint connect fpmu_io_in_bits_req.toint, io.in.bits.fp_ctrl.toint connect fpmu_io_in_bits_req.fastpipe, io.in.bits.fp_ctrl.fastpipe connect fpmu_io_in_bits_req.fma, io.in.bits.fp_ctrl.fma connect fpmu_io_in_bits_req.div, io.in.bits.fp_ctrl.div connect fpmu_io_in_bits_req.sqrt, io.in.bits.fp_ctrl.sqrt connect fpmu_io_in_bits_req.wflags, io.in.bits.fp_ctrl.wflags connect fpmu_io_in_bits_req.vec, io.in.bits.fp_ctrl.vec connect fpmu_io_in_bits_req.rm, rm node _fpmu_io_in_bits_req_in1_prev_unswizzled_T = bits(io.frs1_data, 31, 31) node _fpmu_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.frs1_data, 52, 52) node _fpmu_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.frs1_data, 30, 0) node fpmu_io_in_bits_req_in1_prev_unswizzled_hi = cat(_fpmu_io_in_bits_req_in1_prev_unswizzled_T, _fpmu_io_in_bits_req_in1_prev_unswizzled_T_1) node fpmu_io_in_bits_req_in1_prev_unswizzled = cat(fpmu_io_in_bits_req_in1_prev_unswizzled_hi, _fpmu_io_in_bits_req_in1_prev_unswizzled_T_2) node _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(fpmu_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(fpmu_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(fpmu_io_in_bits_req_in1_prev_unswizzled, 14, 0) node fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node fpmu_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node fpmu_io_in_bits_req_in1_floats_0 = cat(fpmu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _fpmu_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(fpmu_io_in_bits_req_in1_prev_unswizzled, 32, 28) node fpmu_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_fpmu_io_in_bits_req_in1_prev_prev_prev_isbox_T) node fpmu_io_in_bits_req_in1_prev_prev_0_1 = and(fpmu_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node fpmu_io_in_bits_req_in1_prev_prev_sign = bits(fpmu_io_in_bits_req_in1_prev_unswizzled, 32, 32) node fpmu_io_in_bits_req_in1_prev_prev_fractIn = bits(fpmu_io_in_bits_req_in1_prev_unswizzled, 22, 0) node fpmu_io_in_bits_req_in1_prev_prev_expIn = bits(fpmu_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _fpmu_io_in_bits_req_in1_prev_prev_fractOut_T = shl(fpmu_io_in_bits_req_in1_prev_prev_fractIn, 53) node fpmu_io_in_bits_req_in1_prev_prev_fractOut = shr(_fpmu_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(fpmu_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(fpmu_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_T = eq(fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_fpmu_io_in_bits_req_in1_prev_prev_expOut_T, _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_1) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_3) node _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node fpmu_io_in_bits_req_in1_prev_prev_expOut = mux(_fpmu_io_in_bits_req_in1_prev_prev_expOut_T_2, _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_4, _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_5) node fpmu_io_in_bits_req_in1_prev_prev_hi = cat(fpmu_io_in_bits_req_in1_prev_prev_sign, fpmu_io_in_bits_req_in1_prev_prev_expOut) node fpmu_io_in_bits_req_in1_floats_1 = cat(fpmu_io_in_bits_req_in1_prev_prev_hi, fpmu_io_in_bits_req_in1_prev_prev_fractOut) node _fpmu_io_in_bits_req_in1_prev_isbox_T = bits(io.frs1_data, 64, 60) node fpmu_io_in_bits_req_in1_prev_isbox = andr(_fpmu_io_in_bits_req_in1_prev_isbox_T) node fpmu_io_in_bits_req_in1_oks_0 = and(fpmu_io_in_bits_req_in1_prev_isbox, fpmu_io_in_bits_req_in1_prev_prev_0_1) node fpmu_io_in_bits_req_in1_oks_1 = and(fpmu_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in1_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in1_T_1 = mux(_fpmu_io_in_bits_req_in1_T, fpmu_io_in_bits_req_in1_oks_1, fpmu_io_in_bits_req_in1_oks_0) node _fpmu_io_in_bits_req_in1_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpmu_io_in_bits_req_in1_T_3 = mux(_fpmu_io_in_bits_req_in1_T_2, UInt<1>(0h1), _fpmu_io_in_bits_req_in1_T_1) node _fpmu_io_in_bits_req_in1_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpmu_io_in_bits_req_in1_T_5 = mux(_fpmu_io_in_bits_req_in1_T_4, UInt<1>(0h1), _fpmu_io_in_bits_req_in1_T_3) node _fpmu_io_in_bits_req_in1_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in1_T_7 = mux(_fpmu_io_in_bits_req_in1_T_6, fpmu_io_in_bits_req_in1_floats_1, fpmu_io_in_bits_req_in1_floats_0) node _fpmu_io_in_bits_req_in1_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpmu_io_in_bits_req_in1_T_9 = mux(_fpmu_io_in_bits_req_in1_T_8, io.frs1_data, _fpmu_io_in_bits_req_in1_T_7) node _fpmu_io_in_bits_req_in1_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpmu_io_in_bits_req_in1_T_11 = mux(_fpmu_io_in_bits_req_in1_T_10, io.frs1_data, _fpmu_io_in_bits_req_in1_T_9) node _fpmu_io_in_bits_req_in1_T_12 = mux(_fpmu_io_in_bits_req_in1_T_5, _fpmu_io_in_bits_req_in1_T_11, UInt<65>(0he008000000000000)) connect fpmu_io_in_bits_req.in1, _fpmu_io_in_bits_req_in1_T_12 node _fpmu_io_in_bits_req_in2_prev_unswizzled_T = bits(io.frs2_data, 31, 31) node _fpmu_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.frs2_data, 52, 52) node _fpmu_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.frs2_data, 30, 0) node fpmu_io_in_bits_req_in2_prev_unswizzled_hi = cat(_fpmu_io_in_bits_req_in2_prev_unswizzled_T, _fpmu_io_in_bits_req_in2_prev_unswizzled_T_1) node fpmu_io_in_bits_req_in2_prev_unswizzled = cat(fpmu_io_in_bits_req_in2_prev_unswizzled_hi, _fpmu_io_in_bits_req_in2_prev_unswizzled_T_2) node _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(fpmu_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(fpmu_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(fpmu_io_in_bits_req_in2_prev_unswizzled, 14, 0) node fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node fpmu_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node fpmu_io_in_bits_req_in2_floats_0 = cat(fpmu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _fpmu_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(fpmu_io_in_bits_req_in2_prev_unswizzled, 32, 28) node fpmu_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_fpmu_io_in_bits_req_in2_prev_prev_prev_isbox_T) node fpmu_io_in_bits_req_in2_prev_prev_0_1 = and(fpmu_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node fpmu_io_in_bits_req_in2_prev_prev_sign = bits(fpmu_io_in_bits_req_in2_prev_unswizzled, 32, 32) node fpmu_io_in_bits_req_in2_prev_prev_fractIn = bits(fpmu_io_in_bits_req_in2_prev_unswizzled, 22, 0) node fpmu_io_in_bits_req_in2_prev_prev_expIn = bits(fpmu_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _fpmu_io_in_bits_req_in2_prev_prev_fractOut_T = shl(fpmu_io_in_bits_req_in2_prev_prev_fractIn, 53) node fpmu_io_in_bits_req_in2_prev_prev_fractOut = shr(_fpmu_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(fpmu_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(fpmu_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_T = eq(fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_fpmu_io_in_bits_req_in2_prev_prev_expOut_T, _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_1) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_3) node _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node fpmu_io_in_bits_req_in2_prev_prev_expOut = mux(_fpmu_io_in_bits_req_in2_prev_prev_expOut_T_2, _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_4, _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_5) node fpmu_io_in_bits_req_in2_prev_prev_hi = cat(fpmu_io_in_bits_req_in2_prev_prev_sign, fpmu_io_in_bits_req_in2_prev_prev_expOut) node fpmu_io_in_bits_req_in2_floats_1 = cat(fpmu_io_in_bits_req_in2_prev_prev_hi, fpmu_io_in_bits_req_in2_prev_prev_fractOut) node _fpmu_io_in_bits_req_in2_prev_isbox_T = bits(io.frs2_data, 64, 60) node fpmu_io_in_bits_req_in2_prev_isbox = andr(_fpmu_io_in_bits_req_in2_prev_isbox_T) node fpmu_io_in_bits_req_in2_oks_0 = and(fpmu_io_in_bits_req_in2_prev_isbox, fpmu_io_in_bits_req_in2_prev_prev_0_1) node fpmu_io_in_bits_req_in2_oks_1 = and(fpmu_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in2_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in2_T_1 = mux(_fpmu_io_in_bits_req_in2_T, fpmu_io_in_bits_req_in2_oks_1, fpmu_io_in_bits_req_in2_oks_0) node _fpmu_io_in_bits_req_in2_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpmu_io_in_bits_req_in2_T_3 = mux(_fpmu_io_in_bits_req_in2_T_2, UInt<1>(0h1), _fpmu_io_in_bits_req_in2_T_1) node _fpmu_io_in_bits_req_in2_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpmu_io_in_bits_req_in2_T_5 = mux(_fpmu_io_in_bits_req_in2_T_4, UInt<1>(0h1), _fpmu_io_in_bits_req_in2_T_3) node _fpmu_io_in_bits_req_in2_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in2_T_7 = mux(_fpmu_io_in_bits_req_in2_T_6, fpmu_io_in_bits_req_in2_floats_1, fpmu_io_in_bits_req_in2_floats_0) node _fpmu_io_in_bits_req_in2_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpmu_io_in_bits_req_in2_T_9 = mux(_fpmu_io_in_bits_req_in2_T_8, io.frs2_data, _fpmu_io_in_bits_req_in2_T_7) node _fpmu_io_in_bits_req_in2_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpmu_io_in_bits_req_in2_T_11 = mux(_fpmu_io_in_bits_req_in2_T_10, io.frs2_data, _fpmu_io_in_bits_req_in2_T_9) node _fpmu_io_in_bits_req_in2_T_12 = mux(_fpmu_io_in_bits_req_in2_T_5, _fpmu_io_in_bits_req_in2_T_11, UInt<65>(0he008000000000000)) connect fpmu_io_in_bits_req.in2, _fpmu_io_in_bits_req_in2_T_12 node _fpmu_io_in_bits_req_in3_prev_unswizzled_T = bits(io.frs3_data, 31, 31) node _fpmu_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.frs3_data, 52, 52) node _fpmu_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.frs3_data, 30, 0) node fpmu_io_in_bits_req_in3_prev_unswizzled_hi = cat(_fpmu_io_in_bits_req_in3_prev_unswizzled_T, _fpmu_io_in_bits_req_in3_prev_unswizzled_T_1) node fpmu_io_in_bits_req_in3_prev_unswizzled = cat(fpmu_io_in_bits_req_in3_prev_unswizzled_hi, _fpmu_io_in_bits_req_in3_prev_unswizzled_T_2) node _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(fpmu_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(fpmu_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(fpmu_io_in_bits_req_in3_prev_unswizzled, 14, 0) node fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node fpmu_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node fpmu_io_in_bits_req_in3_floats_0 = cat(fpmu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _fpmu_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(fpmu_io_in_bits_req_in3_prev_unswizzled, 32, 28) node fpmu_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_fpmu_io_in_bits_req_in3_prev_prev_prev_isbox_T) node fpmu_io_in_bits_req_in3_prev_prev_0_1 = and(fpmu_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node fpmu_io_in_bits_req_in3_prev_prev_sign = bits(fpmu_io_in_bits_req_in3_prev_unswizzled, 32, 32) node fpmu_io_in_bits_req_in3_prev_prev_fractIn = bits(fpmu_io_in_bits_req_in3_prev_unswizzled, 22, 0) node fpmu_io_in_bits_req_in3_prev_prev_expIn = bits(fpmu_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _fpmu_io_in_bits_req_in3_prev_prev_fractOut_T = shl(fpmu_io_in_bits_req_in3_prev_prev_fractIn, 53) node fpmu_io_in_bits_req_in3_prev_prev_fractOut = shr(_fpmu_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(fpmu_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(fpmu_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_T = eq(fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_fpmu_io_in_bits_req_in3_prev_prev_expOut_T, _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_1) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_3) node _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node fpmu_io_in_bits_req_in3_prev_prev_expOut = mux(_fpmu_io_in_bits_req_in3_prev_prev_expOut_T_2, _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_4, _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_5) node fpmu_io_in_bits_req_in3_prev_prev_hi = cat(fpmu_io_in_bits_req_in3_prev_prev_sign, fpmu_io_in_bits_req_in3_prev_prev_expOut) node fpmu_io_in_bits_req_in3_floats_1 = cat(fpmu_io_in_bits_req_in3_prev_prev_hi, fpmu_io_in_bits_req_in3_prev_prev_fractOut) node _fpmu_io_in_bits_req_in3_prev_isbox_T = bits(io.frs3_data, 64, 60) node fpmu_io_in_bits_req_in3_prev_isbox = andr(_fpmu_io_in_bits_req_in3_prev_isbox_T) node fpmu_io_in_bits_req_in3_oks_0 = and(fpmu_io_in_bits_req_in3_prev_isbox, fpmu_io_in_bits_req_in3_prev_prev_0_1) node fpmu_io_in_bits_req_in3_oks_1 = and(fpmu_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in3_T = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in3_T_1 = mux(_fpmu_io_in_bits_req_in3_T, fpmu_io_in_bits_req_in3_oks_1, fpmu_io_in_bits_req_in3_oks_0) node _fpmu_io_in_bits_req_in3_T_2 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpmu_io_in_bits_req_in3_T_3 = mux(_fpmu_io_in_bits_req_in3_T_2, UInt<1>(0h1), _fpmu_io_in_bits_req_in3_T_1) node _fpmu_io_in_bits_req_in3_T_4 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpmu_io_in_bits_req_in3_T_5 = mux(_fpmu_io_in_bits_req_in3_T_4, UInt<1>(0h1), _fpmu_io_in_bits_req_in3_T_3) node _fpmu_io_in_bits_req_in3_T_6 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<1>(0h1)) node _fpmu_io_in_bits_req_in3_T_7 = mux(_fpmu_io_in_bits_req_in3_T_6, fpmu_io_in_bits_req_in3_floats_1, fpmu_io_in_bits_req_in3_floats_0) node _fpmu_io_in_bits_req_in3_T_8 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h2)) node _fpmu_io_in_bits_req_in3_T_9 = mux(_fpmu_io_in_bits_req_in3_T_8, io.frs3_data, _fpmu_io_in_bits_req_in3_T_7) node _fpmu_io_in_bits_req_in3_T_10 = eq(io.in.bits.fp_ctrl.typeTagIn, UInt<2>(0h3)) node _fpmu_io_in_bits_req_in3_T_11 = mux(_fpmu_io_in_bits_req_in3_T_10, io.frs3_data, _fpmu_io_in_bits_req_in3_T_9) node _fpmu_io_in_bits_req_in3_T_12 = mux(_fpmu_io_in_bits_req_in3_T_5, _fpmu_io_in_bits_req_in3_T_11, UInt<65>(0he008000000000000)) connect fpmu_io_in_bits_req.in3, _fpmu_io_in_bits_req_in3_T_12 node _fpmu_io_in_bits_req_typ_T = bits(io.in.bits.inst, 21, 20) connect fpmu_io_in_bits_req.typ, _fpmu_io_in_bits_req_typ_T node _fpmu_io_in_bits_req_fmt_T = bits(io.in.bits.inst, 26, 25) connect fpmu_io_in_bits_req.fmt, _fpmu_io_in_bits_req_fmt_T node _fpmu_io_in_bits_req_fmaCmd_T = bits(io.in.bits.inst, 3, 2) node _fpmu_io_in_bits_req_fmaCmd_T_1 = eq(io.in.bits.fp_ctrl.ren3, UInt<1>(0h0)) node _fpmu_io_in_bits_req_fmaCmd_T_2 = bits(io.in.bits.inst, 27, 27) node _fpmu_io_in_bits_req_fmaCmd_T_3 = and(_fpmu_io_in_bits_req_fmaCmd_T_1, _fpmu_io_in_bits_req_fmaCmd_T_2) node _fpmu_io_in_bits_req_fmaCmd_T_4 = or(_fpmu_io_in_bits_req_fmaCmd_T, _fpmu_io_in_bits_req_fmaCmd_T_3) connect fpmu_io_in_bits_req.fmaCmd, _fpmu_io_in_bits_req_fmaCmd_T_4 connect fpmu_io_in_bits_req.vec, UInt<1>(0h0) connect fpmu.io.in.bits.in3, fpmu_io_in_bits_req.in3 connect fpmu.io.in.bits.in2, fpmu_io_in_bits_req.in2 connect fpmu.io.in.bits.in1, fpmu_io_in_bits_req.in1 connect fpmu.io.in.bits.fmt, fpmu_io_in_bits_req.fmt connect fpmu.io.in.bits.typ, fpmu_io_in_bits_req.typ connect fpmu.io.in.bits.fmaCmd, fpmu_io_in_bits_req.fmaCmd connect fpmu.io.in.bits.rm, fpmu_io_in_bits_req.rm connect fpmu.io.in.bits.vec, fpmu_io_in_bits_req.vec connect fpmu.io.in.bits.wflags, fpmu_io_in_bits_req.wflags connect fpmu.io.in.bits.sqrt, fpmu_io_in_bits_req.sqrt connect fpmu.io.in.bits.div, fpmu_io_in_bits_req.div connect fpmu.io.in.bits.fma, fpmu_io_in_bits_req.fma connect fpmu.io.in.bits.fastpipe, fpmu_io_in_bits_req.fastpipe connect fpmu.io.in.bits.toint, fpmu_io_in_bits_req.toint connect fpmu.io.in.bits.fromint, fpmu_io_in_bits_req.fromint connect fpmu.io.in.bits.typeTagOut, fpmu_io_in_bits_req.typeTagOut connect fpmu.io.in.bits.typeTagIn, fpmu_io_in_bits_req.typeTagIn connect fpmu.io.in.bits.swap23, fpmu_io_in_bits_req.swap23 connect fpmu.io.in.bits.swap12, fpmu_io_in_bits_req.swap12 connect fpmu.io.in.bits.ren3, fpmu_io_in_bits_req.ren3 connect fpmu.io.in.bits.ren2, fpmu_io_in_bits_req.ren2 connect fpmu.io.in.bits.ren1, fpmu_io_in_bits_req.ren1 connect fpmu.io.in.bits.wen, fpmu_io_in_bits_req.wen connect fpmu.io.in.bits.ldst, fpmu_io_in_bits_req.ldst node _io_out_valid_T = or(io.in.bits.fp_ctrl.toint, io.in.bits.fp_ctrl.div) node _io_out_valid_T_1 = or(_io_out_valid_T, io.in.bits.fp_ctrl.sqrt) node _io_out_valid_T_2 = eq(_io_out_valid_T_1, UInt<1>(0h0)) node _io_out_valid_T_3 = and(io.in.valid, _io_out_valid_T_2) reg io_out_valid_r : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r, _io_out_valid_T_3 reg io_out_valid_r_1 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_1, io_out_valid_r reg io_out_valid_r_2 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_2, io_out_valid_r_1 reg io_out_valid_r_3 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_3, io_out_valid_r_2 reg io_out_valid_r_4 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_4, io.s1_kill reg io_out_valid_r_5 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_5, io_out_valid_r_4 reg io_out_valid_r_6 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_6, io_out_valid_r_5 node _io_out_valid_T_4 = eq(io_out_valid_r_6, UInt<1>(0h0)) node _io_out_valid_T_5 = and(io_out_valid_r_3, _io_out_valid_T_4) reg io_out_valid_r_7 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_7, io.s2_kill reg io_out_valid_r_8 : UInt<1>, clock when UInt<1>(0h1) : connect io_out_valid_r_8, io_out_valid_r_7 node _io_out_valid_T_6 = eq(io_out_valid_r_8, UInt<1>(0h0)) node _io_out_valid_T_7 = and(_io_out_valid_T_5, _io_out_valid_T_6) connect io.out.valid, _io_out_valid_T_7 wire _io_out_bits_WIRE : { data : UInt<65>, exc : UInt<5>} node _io_out_bits_T = mux(dfma.io.out.valid, dfma.io.out.bits.exc, UInt<1>(0h0)) node _io_out_bits_T_1 = mux(sfma.io.out.valid, sfma.io.out.bits.exc, UInt<1>(0h0)) node _io_out_bits_T_2 = mux(hfma.io.out.valid, hfma.io.out.bits.exc, UInt<1>(0h0)) node _io_out_bits_T_3 = mux(ifpu.io.out.valid, ifpu.io.out.bits.exc, UInt<1>(0h0)) node _io_out_bits_T_4 = mux(fpmu.io.out.valid, fpmu.io.out.bits.exc, UInt<1>(0h0)) node _io_out_bits_T_5 = or(_io_out_bits_T, _io_out_bits_T_1) node _io_out_bits_T_6 = or(_io_out_bits_T_5, _io_out_bits_T_2) node _io_out_bits_T_7 = or(_io_out_bits_T_6, _io_out_bits_T_3) node _io_out_bits_T_8 = or(_io_out_bits_T_7, _io_out_bits_T_4) wire _io_out_bits_WIRE_1 : UInt<5> connect _io_out_bits_WIRE_1, _io_out_bits_T_8 connect _io_out_bits_WIRE.exc, _io_out_bits_WIRE_1 node _io_out_bits_T_9 = mux(dfma.io.out.valid, dfma.io.out.bits.data, UInt<1>(0h0)) node _io_out_bits_T_10 = mux(sfma.io.out.valid, sfma.io.out.bits.data, UInt<1>(0h0)) node _io_out_bits_T_11 = mux(hfma.io.out.valid, hfma.io.out.bits.data, UInt<1>(0h0)) node _io_out_bits_T_12 = mux(ifpu.io.out.valid, ifpu.io.out.bits.data, UInt<1>(0h0)) node _io_out_bits_T_13 = mux(fpmu.io.out.valid, fpmu.io.out.bits.data, UInt<1>(0h0)) node _io_out_bits_T_14 = or(_io_out_bits_T_9, _io_out_bits_T_10) node _io_out_bits_T_15 = or(_io_out_bits_T_14, _io_out_bits_T_11) node _io_out_bits_T_16 = or(_io_out_bits_T_15, _io_out_bits_T_12) node _io_out_bits_T_17 = or(_io_out_bits_T_16, _io_out_bits_T_13) wire _io_out_bits_WIRE_2 : UInt<65> connect _io_out_bits_WIRE_2, _io_out_bits_T_17 connect _io_out_bits_WIRE.data, _io_out_bits_WIRE_2 connect io.out.bits, _io_out_bits_WIRE node _io_out_rd_T = bits(io.in.bits.inst, 11, 7) reg io_out_rd_r : UInt<5>, clock when UInt<1>(0h1) : connect io_out_rd_r, _io_out_rd_T reg io_out_rd_r_1 : UInt<5>, clock when UInt<1>(0h1) : connect io_out_rd_r_1, io_out_rd_r reg io_out_rd_r_2 : UInt<5>, clock when UInt<1>(0h1) : connect io_out_rd_r_2, io_out_rd_r_1 reg io_out_rd_r_3 : UInt<5>, clock when UInt<1>(0h1) : connect io_out_rd_r_3, io_out_rd_r_2 connect io.out_rd, io_out_rd_r_3 reg io_out_tag_r : UInt<2>, clock when UInt<1>(0h1) : connect io_out_tag_r, io.in.bits.fp_ctrl.typeTagOut reg io_out_tag_r_1 : UInt<2>, clock when UInt<1>(0h1) : connect io_out_tag_r_1, io_out_tag_r reg io_out_tag_r_2 : UInt<2>, clock when UInt<1>(0h1) : connect io_out_tag_r_2, io_out_tag_r_1 reg io_out_tag_r_3 : UInt<2>, clock when UInt<1>(0h1) : connect io_out_tag_r_3, io_out_tag_r_2 connect io.out_tag, io_out_tag_r_3
module ShuttleFPPipe( // @[FPU.scala:15:7] input clock, // @[FPU.scala:15:7] input reset, // @[FPU.scala:15:7] input io_in_valid, // @[FPU.scala:17:14] input [31:0] io_in_bits_inst, // @[FPU.scala:17:14] input [31:0] io_in_bits_raw_inst, // @[FPU.scala:17:14] input [39:0] io_in_bits_pc, // @[FPU.scala:17:14] input io_in_bits_edge_inst, // @[FPU.scala:17:14] input io_in_bits_ctrl_legal, // @[FPU.scala:17:14] input io_in_bits_ctrl_fp, // @[FPU.scala:17:14] input io_in_bits_ctrl_rocc, // @[FPU.scala:17:14] input io_in_bits_ctrl_branch, // @[FPU.scala:17:14] input io_in_bits_ctrl_jal, // @[FPU.scala:17:14] input io_in_bits_ctrl_jalr, // @[FPU.scala:17:14] input io_in_bits_ctrl_rxs2, // @[FPU.scala:17:14] input io_in_bits_ctrl_rxs1, // @[FPU.scala:17:14] input [2:0] io_in_bits_ctrl_sel_alu2, // @[FPU.scala:17:14] input [1:0] io_in_bits_ctrl_sel_alu1, // @[FPU.scala:17:14] input [2:0] io_in_bits_ctrl_sel_imm, // @[FPU.scala:17:14] input io_in_bits_ctrl_alu_dw, // @[FPU.scala:17:14] input [4:0] io_in_bits_ctrl_alu_fn, // @[FPU.scala:17:14] input io_in_bits_ctrl_mem, // @[FPU.scala:17:14] input [4:0] io_in_bits_ctrl_mem_cmd, // @[FPU.scala:17:14] input io_in_bits_ctrl_rfs1, // @[FPU.scala:17:14] input io_in_bits_ctrl_rfs2, // @[FPU.scala:17:14] input io_in_bits_ctrl_rfs3, // @[FPU.scala:17:14] input io_in_bits_ctrl_wfd, // @[FPU.scala:17:14] input io_in_bits_ctrl_mul, // @[FPU.scala:17:14] input io_in_bits_ctrl_div, // @[FPU.scala:17:14] input io_in_bits_ctrl_wxd, // @[FPU.scala:17:14] input [2:0] io_in_bits_ctrl_csr, // @[FPU.scala:17:14] input io_in_bits_ctrl_fence_i, // @[FPU.scala:17:14] input io_in_bits_ctrl_fence, // @[FPU.scala:17:14] input io_in_bits_ctrl_amo, // @[FPU.scala:17:14] input io_in_bits_ctrl_dp, // @[FPU.scala:17:14] input io_in_bits_ctrl_vec, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_ldst, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_wen, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_ren1, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_ren2, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_ren3, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_swap12, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_swap23, // @[FPU.scala:17:14] input [1:0] io_in_bits_fp_ctrl_typeTagIn, // @[FPU.scala:17:14] input [1:0] io_in_bits_fp_ctrl_typeTagOut, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_fromint, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_toint, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_fastpipe, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_fma, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_div, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_sqrt, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_wflags, // @[FPU.scala:17:14] input io_in_bits_fp_ctrl_vec, // @[FPU.scala:17:14] input io_in_bits_rvc, // @[FPU.scala:17:14] input io_in_bits_btb_resp_valid, // @[FPU.scala:17:14] input [1:0] io_in_bits_btb_resp_bits_cfiType, // @[FPU.scala:17:14] input io_in_bits_btb_resp_bits_taken, // @[FPU.scala:17:14] input [3:0] io_in_bits_btb_resp_bits_mask, // @[FPU.scala:17:14] input [1:0] io_in_bits_btb_resp_bits_bridx, // @[FPU.scala:17:14] input [38:0] io_in_bits_btb_resp_bits_target, // @[FPU.scala:17:14] input [5:0] io_in_bits_btb_resp_bits_entry, // @[FPU.scala:17:14] input [7:0] io_in_bits_btb_resp_bits_bht_history, // @[FPU.scala:17:14] input [1:0] io_in_bits_btb_resp_bits_bht_value, // @[FPU.scala:17:14] input io_in_bits_sfb_br, // @[FPU.scala:17:14] input io_in_bits_next_pc_valid, // @[FPU.scala:17:14] input [39:0] io_in_bits_next_pc_bits, // @[FPU.scala:17:14] input [2:0] io_in_bits_ras_head, // @[FPU.scala:17:14] input io_in_bits_taken, // @[FPU.scala:17:14] input io_in_bits_xcpt, // @[FPU.scala:17:14] input [63:0] io_in_bits_xcpt_cause, // @[FPU.scala:17:14] input io_in_bits_needs_replay, // @[FPU.scala:17:14] input [63:0] io_in_bits_rs1_data, // @[FPU.scala:17:14] input [63:0] io_in_bits_rs2_data, // @[FPU.scala:17:14] input [63:0] io_in_bits_rs3_data, // @[FPU.scala:17:14] input io_in_bits_wdata_valid, // @[FPU.scala:17:14] input [63:0] io_in_bits_wdata_bits, // @[FPU.scala:17:14] input [4:0] io_in_bits_fra1, // @[FPU.scala:17:14] input [4:0] io_in_bits_fra2, // @[FPU.scala:17:14] input [4:0] io_in_bits_fra3, // @[FPU.scala:17:14] input [4:0] io_in_bits_fexc, // @[FPU.scala:17:14] input io_in_bits_fdivin_ldst, // @[FPU.scala:17:14] input io_in_bits_fdivin_wen, // @[FPU.scala:17:14] input io_in_bits_fdivin_ren1, // @[FPU.scala:17:14] input io_in_bits_fdivin_ren2, // @[FPU.scala:17:14] input io_in_bits_fdivin_ren3, // @[FPU.scala:17:14] input io_in_bits_fdivin_swap12, // @[FPU.scala:17:14] input io_in_bits_fdivin_swap23, // @[FPU.scala:17:14] input [1:0] io_in_bits_fdivin_typeTagIn, // @[FPU.scala:17:14] input [1:0] io_in_bits_fdivin_typeTagOut, // @[FPU.scala:17:14] input io_in_bits_fdivin_fromint, // @[FPU.scala:17:14] input io_in_bits_fdivin_toint, // @[FPU.scala:17:14] input io_in_bits_fdivin_fastpipe, // @[FPU.scala:17:14] input io_in_bits_fdivin_fma, // @[FPU.scala:17:14] input io_in_bits_fdivin_div, // @[FPU.scala:17:14] input io_in_bits_fdivin_sqrt, // @[FPU.scala:17:14] input io_in_bits_fdivin_wflags, // @[FPU.scala:17:14] input io_in_bits_fdivin_vec, // @[FPU.scala:17:14] input [2:0] io_in_bits_fdivin_rm, // @[FPU.scala:17:14] input [1:0] io_in_bits_fdivin_fmaCmd, // @[FPU.scala:17:14] input [1:0] io_in_bits_fdivin_typ, // @[FPU.scala:17:14] input [1:0] io_in_bits_fdivin_fmt, // @[FPU.scala:17:14] input [64:0] io_in_bits_fdivin_in1, // @[FPU.scala:17:14] input [64:0] io_in_bits_fdivin_in2, // @[FPU.scala:17:14] input [64:0] io_in_bits_fdivin_in3, // @[FPU.scala:17:14] input [1:0] io_in_bits_mem_size, // @[FPU.scala:17:14] input io_in_bits_flush_pipe, // @[FPU.scala:17:14] input [64:0] io_frs1_data, // @[FPU.scala:17:14] input [64:0] io_frs2_data, // @[FPU.scala:17:14] input [64:0] io_frs3_data, // @[FPU.scala:17:14] input [2:0] io_fcsr_rm, // @[FPU.scala:17:14] input io_s1_kill, // @[FPU.scala:17:14] output [63:0] io_s1_store_data, // @[FPU.scala:17:14] output [63:0] io_s1_fpiu_toint, // @[FPU.scala:17:14] output [4:0] io_s1_fpiu_fexc, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_ldst, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_wen, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_ren1, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_ren2, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_ren3, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_swap12, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_swap23, // @[FPU.scala:17:14] output [1:0] io_s1_fpiu_fdiv_typeTagIn, // @[FPU.scala:17:14] output [1:0] io_s1_fpiu_fdiv_typeTagOut, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_fromint, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_toint, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_fastpipe, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_fma, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_div, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_sqrt, // @[FPU.scala:17:14] output io_s1_fpiu_fdiv_wflags, // @[FPU.scala:17:14] output [2:0] io_s1_fpiu_fdiv_rm, // @[FPU.scala:17:14] output [1:0] io_s1_fpiu_fdiv_fmaCmd, // @[FPU.scala:17:14] output [1:0] io_s1_fpiu_fdiv_typ, // @[FPU.scala:17:14] output [1:0] io_s1_fpiu_fdiv_fmt, // @[FPU.scala:17:14] output [64:0] io_s1_fpiu_fdiv_in1, // @[FPU.scala:17:14] output [64:0] io_s1_fpiu_fdiv_in2, // @[FPU.scala:17:14] output [64:0] io_s1_fpiu_fdiv_in3, // @[FPU.scala:17:14] output io_out_valid, // @[FPU.scala:17:14] output [64:0] io_out_bits_data, // @[FPU.scala:17:14] output [4:0] io_out_bits_exc, // @[FPU.scala:17:14] output [4:0] io_out_rd, // @[FPU.scala:17:14] output [1:0] io_out_tag // @[FPU.scala:17:14] ); wire _fpmu_io_out_valid; // @[FPU.scala:93:20] wire [64:0] _fpmu_io_out_bits_data; // @[FPU.scala:93:20] wire [4:0] _fpmu_io_out_bits_exc; // @[FPU.scala:93:20] wire _ifpu_io_out_valid; // @[FPU.scala:88:20] wire [64:0] _ifpu_io_out_bits_data; // @[FPU.scala:88:20] wire [4:0] _ifpu_io_out_bits_exc; // @[FPU.scala:88:20] wire _hfma_io_out_valid; // @[FPU.scala:81:20] wire [64:0] _hfma_io_out_bits_data; // @[FPU.scala:81:20] wire [4:0] _hfma_io_out_bits_exc; // @[FPU.scala:81:20] wire _sfma_io_out_valid; // @[FPU.scala:80:20] wire [64:0] _sfma_io_out_bits_data; // @[FPU.scala:80:20] wire [4:0] _sfma_io_out_bits_exc; // @[FPU.scala:80:20] wire _dfma_io_out_valid; // @[FPU.scala:79:20] wire [64:0] _dfma_io_out_bits_data; // @[FPU.scala:79:20] wire [4:0] _dfma_io_out_bits_exc; // @[FPU.scala:79:20] wire _fpiu_io_out_bits_lt; // @[FPU.scala:71:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:15:7] wire [31:0] io_in_bits_inst_0 = io_in_bits_inst; // @[FPU.scala:15:7] wire [31:0] io_in_bits_raw_inst_0 = io_in_bits_raw_inst; // @[FPU.scala:15:7] wire [39:0] io_in_bits_pc_0 = io_in_bits_pc; // @[FPU.scala:15:7] wire io_in_bits_edge_inst_0 = io_in_bits_edge_inst; // @[FPU.scala:15:7] wire io_in_bits_ctrl_legal_0 = io_in_bits_ctrl_legal; // @[FPU.scala:15:7] wire io_in_bits_ctrl_fp_0 = io_in_bits_ctrl_fp; // @[FPU.scala:15:7] wire io_in_bits_ctrl_rocc_0 = io_in_bits_ctrl_rocc; // @[FPU.scala:15:7] wire io_in_bits_ctrl_branch_0 = io_in_bits_ctrl_branch; // @[FPU.scala:15:7] wire io_in_bits_ctrl_jal_0 = io_in_bits_ctrl_jal; // @[FPU.scala:15:7] wire io_in_bits_ctrl_jalr_0 = io_in_bits_ctrl_jalr; // @[FPU.scala:15:7] wire io_in_bits_ctrl_rxs2_0 = io_in_bits_ctrl_rxs2; // @[FPU.scala:15:7] wire io_in_bits_ctrl_rxs1_0 = io_in_bits_ctrl_rxs1; // @[FPU.scala:15:7] wire [2:0] io_in_bits_ctrl_sel_alu2_0 = io_in_bits_ctrl_sel_alu2; // @[FPU.scala:15:7] wire [1:0] io_in_bits_ctrl_sel_alu1_0 = io_in_bits_ctrl_sel_alu1; // @[FPU.scala:15:7] wire [2:0] io_in_bits_ctrl_sel_imm_0 = io_in_bits_ctrl_sel_imm; // @[FPU.scala:15:7] wire io_in_bits_ctrl_alu_dw_0 = io_in_bits_ctrl_alu_dw; // @[FPU.scala:15:7] wire [4:0] io_in_bits_ctrl_alu_fn_0 = io_in_bits_ctrl_alu_fn; // @[FPU.scala:15:7] wire io_in_bits_ctrl_mem_0 = io_in_bits_ctrl_mem; // @[FPU.scala:15:7] wire [4:0] io_in_bits_ctrl_mem_cmd_0 = io_in_bits_ctrl_mem_cmd; // @[FPU.scala:15:7] wire io_in_bits_ctrl_rfs1_0 = io_in_bits_ctrl_rfs1; // @[FPU.scala:15:7] wire io_in_bits_ctrl_rfs2_0 = io_in_bits_ctrl_rfs2; // @[FPU.scala:15:7] wire io_in_bits_ctrl_rfs3_0 = io_in_bits_ctrl_rfs3; // @[FPU.scala:15:7] wire io_in_bits_ctrl_wfd_0 = io_in_bits_ctrl_wfd; // @[FPU.scala:15:7] wire io_in_bits_ctrl_mul_0 = io_in_bits_ctrl_mul; // @[FPU.scala:15:7] wire io_in_bits_ctrl_div_0 = io_in_bits_ctrl_div; // @[FPU.scala:15:7] wire io_in_bits_ctrl_wxd_0 = io_in_bits_ctrl_wxd; // @[FPU.scala:15:7] wire [2:0] io_in_bits_ctrl_csr_0 = io_in_bits_ctrl_csr; // @[FPU.scala:15:7] wire io_in_bits_ctrl_fence_i_0 = io_in_bits_ctrl_fence_i; // @[FPU.scala:15:7] wire io_in_bits_ctrl_fence_0 = io_in_bits_ctrl_fence; // @[FPU.scala:15:7] wire io_in_bits_ctrl_amo_0 = io_in_bits_ctrl_amo; // @[FPU.scala:15:7] wire io_in_bits_ctrl_dp_0 = io_in_bits_ctrl_dp; // @[FPU.scala:15:7] wire io_in_bits_ctrl_vec_0 = io_in_bits_ctrl_vec; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_ldst_0 = io_in_bits_fp_ctrl_ldst; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_wen_0 = io_in_bits_fp_ctrl_wen; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_ren1_0 = io_in_bits_fp_ctrl_ren1; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_ren2_0 = io_in_bits_fp_ctrl_ren2; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_ren3_0 = io_in_bits_fp_ctrl_ren3; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_swap12_0 = io_in_bits_fp_ctrl_swap12; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_swap23_0 = io_in_bits_fp_ctrl_swap23; // @[FPU.scala:15:7] wire [1:0] io_in_bits_fp_ctrl_typeTagIn_0 = io_in_bits_fp_ctrl_typeTagIn; // @[FPU.scala:15:7] wire [1:0] io_in_bits_fp_ctrl_typeTagOut_0 = io_in_bits_fp_ctrl_typeTagOut; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_fromint_0 = io_in_bits_fp_ctrl_fromint; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_toint_0 = io_in_bits_fp_ctrl_toint; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_fastpipe_0 = io_in_bits_fp_ctrl_fastpipe; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_fma_0 = io_in_bits_fp_ctrl_fma; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_div_0 = io_in_bits_fp_ctrl_div; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_sqrt_0 = io_in_bits_fp_ctrl_sqrt; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_wflags_0 = io_in_bits_fp_ctrl_wflags; // @[FPU.scala:15:7] wire io_in_bits_fp_ctrl_vec_0 = io_in_bits_fp_ctrl_vec; // @[FPU.scala:15:7] wire io_in_bits_rvc_0 = io_in_bits_rvc; // @[FPU.scala:15:7] wire io_in_bits_btb_resp_valid_0 = io_in_bits_btb_resp_valid; // @[FPU.scala:15:7] wire [1:0] io_in_bits_btb_resp_bits_cfiType_0 = io_in_bits_btb_resp_bits_cfiType; // @[FPU.scala:15:7] wire io_in_bits_btb_resp_bits_taken_0 = io_in_bits_btb_resp_bits_taken; // @[FPU.scala:15:7] wire [3:0] io_in_bits_btb_resp_bits_mask_0 = io_in_bits_btb_resp_bits_mask; // @[FPU.scala:15:7] wire [1:0] io_in_bits_btb_resp_bits_bridx_0 = io_in_bits_btb_resp_bits_bridx; // @[FPU.scala:15:7] wire [38:0] io_in_bits_btb_resp_bits_target_0 = io_in_bits_btb_resp_bits_target; // @[FPU.scala:15:7] wire [5:0] io_in_bits_btb_resp_bits_entry_0 = io_in_bits_btb_resp_bits_entry; // @[FPU.scala:15:7] wire [7:0] io_in_bits_btb_resp_bits_bht_history_0 = io_in_bits_btb_resp_bits_bht_history; // @[FPU.scala:15:7] wire [1:0] io_in_bits_btb_resp_bits_bht_value_0 = io_in_bits_btb_resp_bits_bht_value; // @[FPU.scala:15:7] wire io_in_bits_sfb_br_0 = io_in_bits_sfb_br; // @[FPU.scala:15:7] wire io_in_bits_next_pc_valid_0 = io_in_bits_next_pc_valid; // @[FPU.scala:15:7] wire [39:0] io_in_bits_next_pc_bits_0 = io_in_bits_next_pc_bits; // @[FPU.scala:15:7] wire [2:0] io_in_bits_ras_head_0 = io_in_bits_ras_head; // @[FPU.scala:15:7] wire io_in_bits_taken_0 = io_in_bits_taken; // @[FPU.scala:15:7] wire io_in_bits_xcpt_0 = io_in_bits_xcpt; // @[FPU.scala:15:7] wire [63:0] io_in_bits_xcpt_cause_0 = io_in_bits_xcpt_cause; // @[FPU.scala:15:7] wire io_in_bits_needs_replay_0 = io_in_bits_needs_replay; // @[FPU.scala:15:7] wire [63:0] io_in_bits_rs1_data_0 = io_in_bits_rs1_data; // @[FPU.scala:15:7] wire [63:0] io_in_bits_rs2_data_0 = io_in_bits_rs2_data; // @[FPU.scala:15:7] wire [63:0] io_in_bits_rs3_data_0 = io_in_bits_rs3_data; // @[FPU.scala:15:7] wire io_in_bits_wdata_valid_0 = io_in_bits_wdata_valid; // @[FPU.scala:15:7] wire [63:0] io_in_bits_wdata_bits_0 = io_in_bits_wdata_bits; // @[FPU.scala:15:7] wire [4:0] io_in_bits_fra1_0 = io_in_bits_fra1; // @[FPU.scala:15:7] wire [4:0] io_in_bits_fra2_0 = io_in_bits_fra2; // @[FPU.scala:15:7] wire [4:0] io_in_bits_fra3_0 = io_in_bits_fra3; // @[FPU.scala:15:7] wire [4:0] io_in_bits_fexc_0 = io_in_bits_fexc; // @[FPU.scala:15:7] wire io_in_bits_fdivin_ldst_0 = io_in_bits_fdivin_ldst; // @[FPU.scala:15:7] wire io_in_bits_fdivin_wen_0 = io_in_bits_fdivin_wen; // @[FPU.scala:15:7] wire io_in_bits_fdivin_ren1_0 = io_in_bits_fdivin_ren1; // @[FPU.scala:15:7] wire io_in_bits_fdivin_ren2_0 = io_in_bits_fdivin_ren2; // @[FPU.scala:15:7] wire io_in_bits_fdivin_ren3_0 = io_in_bits_fdivin_ren3; // @[FPU.scala:15:7] wire io_in_bits_fdivin_swap12_0 = io_in_bits_fdivin_swap12; // @[FPU.scala:15:7] wire io_in_bits_fdivin_swap23_0 = io_in_bits_fdivin_swap23; // @[FPU.scala:15:7] wire [1:0] io_in_bits_fdivin_typeTagIn_0 = io_in_bits_fdivin_typeTagIn; // @[FPU.scala:15:7] wire [1:0] io_in_bits_fdivin_typeTagOut_0 = io_in_bits_fdivin_typeTagOut; // @[FPU.scala:15:7] wire io_in_bits_fdivin_fromint_0 = io_in_bits_fdivin_fromint; // @[FPU.scala:15:7] wire io_in_bits_fdivin_toint_0 = io_in_bits_fdivin_toint; // @[FPU.scala:15:7] wire io_in_bits_fdivin_fastpipe_0 = io_in_bits_fdivin_fastpipe; // @[FPU.scala:15:7] wire io_in_bits_fdivin_fma_0 = io_in_bits_fdivin_fma; // @[FPU.scala:15:7] wire io_in_bits_fdivin_div_0 = io_in_bits_fdivin_div; // @[FPU.scala:15:7] wire io_in_bits_fdivin_sqrt_0 = io_in_bits_fdivin_sqrt; // @[FPU.scala:15:7] wire io_in_bits_fdivin_wflags_0 = io_in_bits_fdivin_wflags; // @[FPU.scala:15:7] wire io_in_bits_fdivin_vec_0 = io_in_bits_fdivin_vec; // @[FPU.scala:15:7] wire [2:0] io_in_bits_fdivin_rm_0 = io_in_bits_fdivin_rm; // @[FPU.scala:15:7] wire [1:0] io_in_bits_fdivin_fmaCmd_0 = io_in_bits_fdivin_fmaCmd; // @[FPU.scala:15:7] wire [1:0] io_in_bits_fdivin_typ_0 = io_in_bits_fdivin_typ; // @[FPU.scala:15:7] wire [1:0] io_in_bits_fdivin_fmt_0 = io_in_bits_fdivin_fmt; // @[FPU.scala:15:7] wire [64:0] io_in_bits_fdivin_in1_0 = io_in_bits_fdivin_in1; // @[FPU.scala:15:7] wire [64:0] io_in_bits_fdivin_in2_0 = io_in_bits_fdivin_in2; // @[FPU.scala:15:7] wire [64:0] io_in_bits_fdivin_in3_0 = io_in_bits_fdivin_in3; // @[FPU.scala:15:7] wire [1:0] io_in_bits_mem_size_0 = io_in_bits_mem_size; // @[FPU.scala:15:7] wire io_in_bits_flush_pipe_0 = io_in_bits_flush_pipe; // @[FPU.scala:15:7] wire [64:0] io_frs1_data_0 = io_frs1_data; // @[FPU.scala:15:7] wire [64:0] io_frs2_data_0 = io_frs2_data; // @[FPU.scala:15:7] wire [64:0] io_frs3_data_0 = io_frs3_data; // @[FPU.scala:15:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[FPU.scala:15:7] wire io_s1_kill_0 = io_s1_kill; // @[FPU.scala:15:7] wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31] wire _io_out_valid_T_6 = 1'h1; // @[FPU.scala:101:8] wire io_in_bits_sets_vcfg = 1'h0; // @[FPU.scala:15:7] wire io_in_bits_sfb_shadow = 1'h0; // @[FPU.scala:15:7] wire io_in_bits_uses_memalu = 1'h0; // @[FPU.scala:15:7] wire io_in_bits_uses_latealu = 1'h0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_vec = 1'h0; // @[FPU.scala:15:7] wire io_s2_kill = 1'h0; // @[FPU.scala:15:7] wire fpiu_io_in_bits_req_vec = 1'h0; // @[FPU.scala:35:19] wire dfma_io_in_bits_req_vec = 1'h0; // @[FPU.scala:35:19] wire sfma_io_in_bits_req_vec = 1'h0; // @[FPU.scala:35:19] wire hfma_io_in_bits_req_vec = 1'h0; // @[FPU.scala:35:19] wire ifpu_io_in_bits_req_vec = 1'h0; // @[FPU.scala:35:19] wire fpmu_io_in_bits_req_vec = 1'h0; // @[FPU.scala:35:19] wire fpiu_io_in_bits_req_ldst = io_in_bits_fp_ctrl_ldst_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_ldst = io_in_bits_fp_ctrl_ldst_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_ldst = io_in_bits_fp_ctrl_ldst_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_ldst = io_in_bits_fp_ctrl_ldst_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_ldst = io_in_bits_fp_ctrl_ldst_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_ldst = io_in_bits_fp_ctrl_ldst_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_wen = io_in_bits_fp_ctrl_wen_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_wen = io_in_bits_fp_ctrl_wen_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_wen = io_in_bits_fp_ctrl_wen_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_wen = io_in_bits_fp_ctrl_wen_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_wen = io_in_bits_fp_ctrl_wen_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_wen = io_in_bits_fp_ctrl_wen_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_ren1 = io_in_bits_fp_ctrl_ren1_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_ren1 = io_in_bits_fp_ctrl_ren1_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_ren1 = io_in_bits_fp_ctrl_ren1_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_ren1 = io_in_bits_fp_ctrl_ren1_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_ren1 = io_in_bits_fp_ctrl_ren1_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_ren1 = io_in_bits_fp_ctrl_ren1_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_ren2 = io_in_bits_fp_ctrl_ren2_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_ren2 = io_in_bits_fp_ctrl_ren2_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_ren2 = io_in_bits_fp_ctrl_ren2_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_ren2 = io_in_bits_fp_ctrl_ren2_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_ren2 = io_in_bits_fp_ctrl_ren2_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_ren2 = io_in_bits_fp_ctrl_ren2_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_ren3 = io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_ren3 = io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_ren3 = io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_ren3 = io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_ren3 = io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_ren3 = io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_swap12 = io_in_bits_fp_ctrl_swap12_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_swap12 = io_in_bits_fp_ctrl_swap12_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_swap12 = io_in_bits_fp_ctrl_swap12_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_swap12 = io_in_bits_fp_ctrl_swap12_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_swap12 = io_in_bits_fp_ctrl_swap12_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_swap12 = io_in_bits_fp_ctrl_swap12_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_swap23 = io_in_bits_fp_ctrl_swap23_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_swap23 = io_in_bits_fp_ctrl_swap23_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_swap23 = io_in_bits_fp_ctrl_swap23_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_swap23 = io_in_bits_fp_ctrl_swap23_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_swap23 = io_in_bits_fp_ctrl_swap23_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_swap23 = io_in_bits_fp_ctrl_swap23_0; // @[FPU.scala:15:7, :35:19] wire [1:0] fpiu_io_in_bits_req_typeTagIn = io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7, :35:19] wire [1:0] dfma_io_in_bits_req_typeTagIn = io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7, :35:19] wire [1:0] sfma_io_in_bits_req_typeTagIn = io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7, :35:19] wire [1:0] hfma_io_in_bits_req_typeTagIn = io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7, :35:19] wire [1:0] ifpu_io_in_bits_req_typeTagIn = io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7, :35:19] wire [1:0] fpmu_io_in_bits_req_typeTagIn = io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7, :35:19] wire [1:0] fpiu_io_in_bits_req_typeTagOut = io_in_bits_fp_ctrl_typeTagOut_0; // @[FPU.scala:15:7, :35:19] wire [1:0] dfma_io_in_bits_req_typeTagOut = io_in_bits_fp_ctrl_typeTagOut_0; // @[FPU.scala:15:7, :35:19] wire [1:0] sfma_io_in_bits_req_typeTagOut = io_in_bits_fp_ctrl_typeTagOut_0; // @[FPU.scala:15:7, :35:19] wire [1:0] hfma_io_in_bits_req_typeTagOut = io_in_bits_fp_ctrl_typeTagOut_0; // @[FPU.scala:15:7, :35:19] wire [1:0] ifpu_io_in_bits_req_typeTagOut = io_in_bits_fp_ctrl_typeTagOut_0; // @[FPU.scala:15:7, :35:19] wire [1:0] fpmu_io_in_bits_req_typeTagOut = io_in_bits_fp_ctrl_typeTagOut_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_fromint = io_in_bits_fp_ctrl_fromint_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_fromint = io_in_bits_fp_ctrl_fromint_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_fromint = io_in_bits_fp_ctrl_fromint_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_fromint = io_in_bits_fp_ctrl_fromint_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_fromint = io_in_bits_fp_ctrl_fromint_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_fromint = io_in_bits_fp_ctrl_fromint_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_toint = io_in_bits_fp_ctrl_toint_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_toint = io_in_bits_fp_ctrl_toint_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_toint = io_in_bits_fp_ctrl_toint_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_toint = io_in_bits_fp_ctrl_toint_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_toint = io_in_bits_fp_ctrl_toint_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_toint = io_in_bits_fp_ctrl_toint_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_fastpipe = io_in_bits_fp_ctrl_fastpipe_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_fastpipe = io_in_bits_fp_ctrl_fastpipe_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_fastpipe = io_in_bits_fp_ctrl_fastpipe_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_fastpipe = io_in_bits_fp_ctrl_fastpipe_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_fastpipe = io_in_bits_fp_ctrl_fastpipe_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_fastpipe = io_in_bits_fp_ctrl_fastpipe_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_fma = io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_fma = io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_fma = io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_fma = io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_fma = io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_fma = io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_div = io_in_bits_fp_ctrl_div_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_div = io_in_bits_fp_ctrl_div_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_div = io_in_bits_fp_ctrl_div_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_div = io_in_bits_fp_ctrl_div_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_div = io_in_bits_fp_ctrl_div_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_div = io_in_bits_fp_ctrl_div_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_sqrt = io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_sqrt = io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_sqrt = io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_sqrt = io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_sqrt = io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_sqrt = io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :35:19] wire fpiu_io_in_bits_req_wflags = io_in_bits_fp_ctrl_wflags_0; // @[FPU.scala:15:7, :35:19] wire dfma_io_in_bits_req_wflags = io_in_bits_fp_ctrl_wflags_0; // @[FPU.scala:15:7, :35:19] wire sfma_io_in_bits_req_wflags = io_in_bits_fp_ctrl_wflags_0; // @[FPU.scala:15:7, :35:19] wire hfma_io_in_bits_req_wflags = io_in_bits_fp_ctrl_wflags_0; // @[FPU.scala:15:7, :35:19] wire ifpu_io_in_bits_req_wflags = io_in_bits_fp_ctrl_wflags_0; // @[FPU.scala:15:7, :35:19] wire fpmu_io_in_bits_req_wflags = io_in_bits_fp_ctrl_wflags_0; // @[FPU.scala:15:7, :35:19] wire [64:0] _dfma_io_in_bits_req_in1_T_1 = io_frs1_data_0; // @[FPU.scala:15:7] wire [64:0] _dfma_io_in_bits_req_in2_T_1 = io_frs2_data_0; // @[FPU.scala:15:7] wire [64:0] _dfma_io_in_bits_req_in3_T_1 = io_frs3_data_0; // @[FPU.scala:15:7] wire _io_out_valid_T_7; // @[FPU.scala:101:5] wire [64:0] _io_out_bits_WIRE_data; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_WIRE_exc; // @[Mux.scala:30:73] wire io_s1_fpiu_fdiv_ldst_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_wen_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_ren1_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_ren2_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_ren3_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_swap12_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_swap23_0; // @[FPU.scala:15:7] wire [1:0] io_s1_fpiu_fdiv_typeTagIn_0; // @[FPU.scala:15:7] wire [1:0] io_s1_fpiu_fdiv_typeTagOut_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_fromint_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_toint_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_fastpipe_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_fma_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_div_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_sqrt_0; // @[FPU.scala:15:7] wire io_s1_fpiu_fdiv_wflags_0; // @[FPU.scala:15:7] wire [2:0] io_s1_fpiu_fdiv_rm_0; // @[FPU.scala:15:7] wire [1:0] io_s1_fpiu_fdiv_fmaCmd_0; // @[FPU.scala:15:7] wire [1:0] io_s1_fpiu_fdiv_typ_0; // @[FPU.scala:15:7] wire [1:0] io_s1_fpiu_fdiv_fmt_0; // @[FPU.scala:15:7] wire [64:0] io_s1_fpiu_fdiv_in1_0; // @[FPU.scala:15:7] wire [64:0] io_s1_fpiu_fdiv_in2_0; // @[FPU.scala:15:7] wire [64:0] io_s1_fpiu_fdiv_in3_0; // @[FPU.scala:15:7] wire [64:0] io_out_bits_data_0; // @[FPU.scala:15:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:15:7] wire io_out_valid_0; // @[FPU.scala:15:7] wire [63:0] io_s1_store_data_0; // @[FPU.scala:15:7] wire [63:0] io_s1_fpiu_toint_0; // @[FPU.scala:15:7] wire [4:0] io_s1_fpiu_fexc_0; // @[FPU.scala:15:7] wire [4:0] io_out_rd_0; // @[FPU.scala:15:7] wire [1:0] io_out_tag_0; // @[FPU.scala:15:7] wire [2:0] _rm_T = io_in_bits_inst_0[14:12]; // @[FPU.scala:15:7, :69:20] wire [2:0] _rm_T_2 = io_in_bits_inst_0[14:12]; // @[FPU.scala:15:7, :69:{20,53}] wire _rm_T_1 = &_rm_T; // @[FPU.scala:69:{20,28}] wire [2:0] rm = _rm_T_1 ? io_fcsr_rm_0 : _rm_T_2; // @[FPU.scala:15:7, :69:{15,28,53}] wire [2:0] fpiu_io_in_bits_req_rm = rm; // @[FPU.scala:35:19, :69:15] wire [2:0] dfma_io_in_bits_req_rm = rm; // @[FPU.scala:35:19, :69:15] wire [2:0] sfma_io_in_bits_req_rm = rm; // @[FPU.scala:35:19, :69:15] wire [2:0] hfma_io_in_bits_req_rm = rm; // @[FPU.scala:35:19, :69:15] wire [2:0] ifpu_io_in_bits_req_rm = rm; // @[FPU.scala:35:19, :69:15] wire [2:0] fpmu_io_in_bits_req_rm = rm; // @[FPU.scala:35:19, :69:15] wire _GEN = io_in_bits_fp_ctrl_toint_0 | io_in_bits_fp_ctrl_div_0; // @[FPU.scala:15:7, :72:53] wire _fpiu_io_in_valid_T; // @[FPU.scala:72:53] assign _fpiu_io_in_valid_T = _GEN; // @[FPU.scala:72:53] wire _io_out_valid_T; // @[FPU.scala:99:65] assign _io_out_valid_T = _GEN; // @[FPU.scala:72:53, :99:65] wire _fpiu_io_in_valid_T_1 = _fpiu_io_in_valid_T | io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :72:{53,68}] wire _fpiu_io_in_valid_T_2 = io_in_bits_fp_ctrl_fastpipe_0 & io_in_bits_fp_ctrl_wflags_0; // @[FPU.scala:15:7, :72:105] wire _fpiu_io_in_valid_T_3 = _fpiu_io_in_valid_T_1 | _fpiu_io_in_valid_T_2; // @[FPU.scala:72:{68,84,105}] wire _fpiu_io_in_valid_T_4 = io_in_valid_0 & _fpiu_io_in_valid_T_3; // @[FPU.scala:15:7, :72:{35,84}] wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:60:29] wire [1:0] _fpiu_io_in_bits_req_typ_T; // @[FPU.scala:58:20] wire [1:0] _fpiu_io_in_bits_req_fmt_T; // @[FPU.scala:59:20] wire [64:0] _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[FPU.scala:35:19] wire [1:0] fpiu_io_in_bits_req_typ; // @[FPU.scala:35:19] wire [1:0] fpiu_io_in_bits_req_fmt; // @[FPU.scala:35:19] wire [64:0] fpiu_io_in_bits_req_in1; // @[FPU.scala:35:19] wire [64:0] fpiu_io_in_bits_req_in2; // @[FPU.scala:35:19] wire [64:0] fpiu_io_in_bits_req_in3; // @[FPU.scala:35:19] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = io_frs1_data_0[31]; // @[FPU.scala:15:7] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = io_frs1_data_0[31]; // @[FPU.scala:15:7] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = io_frs1_data_0[31]; // @[FPU.scala:15:7] wire _hfma_io_in_bits_req_in1_prev_unswizzled_T = io_frs1_data_0[31]; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in1_prev_unswizzled_T = io_frs1_data_0[31]; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in1_prev_unswizzled_T = io_frs1_data_0[31]; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = io_frs1_data_0[52]; // @[FPU.scala:15:7] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_frs1_data_0[52]; // @[FPU.scala:15:7] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_frs1_data_0[52]; // @[FPU.scala:15:7] wire _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_frs1_data_0[52]; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in1_prev_unswizzled_T_1 = io_frs1_data_0[52]; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in1_prev_unswizzled_T_1 = io_frs1_data_0[52]; // @[FPU.scala:15:7] wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = io_frs1_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_frs1_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_frs1_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_frs1_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _ifpu_io_in_bits_req_in1_prev_unswizzled_T_2 = io_frs1_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _fpmu_io_in_bits_req_in1_prev_unswizzled_T_2 = io_frs1_data_0[30:0]; // @[FPU.scala:15:7] wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_prev_prev_0_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_1 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = io_frs1_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = io_frs1_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = io_frs1_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _hfma_io_in_bits_req_in1_prev_isbox_T = io_frs1_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _ifpu_io_in_bits_req_in1_prev_isbox_T = io_frs1_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _fpmu_io_in_bits_req_in1_prev_isbox_T = io_frs1_data_0[64:60]; // @[FPU.scala:15:7] wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_oks_1 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox & fpiu_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _GEN_0 = io_in_bits_fp_ctrl_typeTagIn_0 == 2'h1; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in1_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T = _GEN_0; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_6 = _GEN_0; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T = _GEN_0; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_6 = _GEN_0; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T = _GEN_0; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_6 = _GEN_0; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in1_T; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in1_T = _GEN_0; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in1_T_6; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in1_T_6 = _GEN_0; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in2_T; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in2_T = _GEN_0; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in2_T_6; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in2_T_6 = _GEN_0; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in3_T; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in3_T = _GEN_0; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in3_T_6; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in3_T_6 = _GEN_0; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in1_T; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in1_T = _GEN_0; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in1_T_6; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in1_T_6 = _GEN_0; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in2_T; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in2_T = _GEN_0; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in2_T_6; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in2_T_6 = _GEN_0; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in3_T; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in3_T = _GEN_0; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in3_T_6; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in3_T_6 = _GEN_0; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T ? fpiu_io_in_bits_req_in1_oks_1 : fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire _GEN_1 = io_in_bits_fp_ctrl_typeTagIn_0 == 2'h2; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in1_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_2 = _GEN_1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_8 = _GEN_1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_2 = _GEN_1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_8 = _GEN_1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_2 = _GEN_1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_8 = _GEN_1; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in1_T_2; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in1_T_2 = _GEN_1; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in1_T_8; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in1_T_8 = _GEN_1; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in2_T_2; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in2_T_2 = _GEN_1; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in2_T_8; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in2_T_8 = _GEN_1; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in3_T_2; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in3_T_2 = _GEN_1; // @[package.scala:39:86] wire _ifpu_io_in_bits_req_in3_T_8; // @[package.scala:39:86] assign _ifpu_io_in_bits_req_in3_T_8 = _GEN_1; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in1_T_2; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in1_T_2 = _GEN_1; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in1_T_8; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in1_T_8 = _GEN_1; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in2_T_2; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in2_T_2 = _GEN_1; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in2_T_8; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in2_T_8 = _GEN_1; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in3_T_2; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in3_T_2 = _GEN_1; // @[package.scala:39:86] wire _fpmu_io_in_bits_req_in3_T_8; // @[package.scala:39:86] assign _fpmu_io_in_bits_req_in3_T_8 = _GEN_1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 | _fpiu_io_in_bits_req_in1_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in1_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in1_T_5 = _fpiu_io_in_bits_req_in1_T_4 | _fpiu_io_in_bits_req_in1_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in1_T_7 = _fpiu_io_in_bits_req_in1_T_6 ? fpiu_io_in_bits_req_in1_floats_1 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in1_T_9 = _fpiu_io_in_bits_req_in1_T_8 ? io_frs1_data_0 : _fpiu_io_in_bits_req_in1_T_7; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in1_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _fpiu_io_in_bits_req_in1_T_11 = _fpiu_io_in_bits_req_in1_T_10 ? io_frs1_data_0 : _fpiu_io_in_bits_req_in1_T_9; // @[FPU.scala:15:7] assign _fpiu_io_in_bits_req_in1_T_12 = _fpiu_io_in_bits_req_in1_T_5 ? _fpiu_io_in_bits_req_in1_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:35:19] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = io_frs2_data_0[31]; // @[FPU.scala:15:7] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = io_frs2_data_0[31]; // @[FPU.scala:15:7] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = io_frs2_data_0[31]; // @[FPU.scala:15:7] wire _hfma_io_in_bits_req_in2_prev_unswizzled_T = io_frs2_data_0[31]; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in2_prev_unswizzled_T = io_frs2_data_0[31]; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in2_prev_unswizzled_T = io_frs2_data_0[31]; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = io_frs2_data_0[52]; // @[FPU.scala:15:7] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_frs2_data_0[52]; // @[FPU.scala:15:7] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_frs2_data_0[52]; // @[FPU.scala:15:7] wire _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_frs2_data_0[52]; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in2_prev_unswizzled_T_1 = io_frs2_data_0[52]; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in2_prev_unswizzled_T_1 = io_frs2_data_0[52]; // @[FPU.scala:15:7] wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = io_frs2_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_frs2_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_frs2_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_frs2_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _ifpu_io_in_bits_req_in2_prev_unswizzled_T_2 = io_frs2_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _fpmu_io_in_bits_req_in2_prev_unswizzled_T_2 = io_frs2_data_0[30:0]; // @[FPU.scala:15:7] wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_prev_prev_0_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_1 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = io_frs2_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = io_frs2_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = io_frs2_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _hfma_io_in_bits_req_in2_prev_isbox_T = io_frs2_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _ifpu_io_in_bits_req_in2_prev_isbox_T = io_frs2_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _fpmu_io_in_bits_req_in2_prev_isbox_T = io_frs2_data_0[64:60]; // @[FPU.scala:15:7] wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_oks_1 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox & fpiu_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T ? fpiu_io_in_bits_req_in2_oks_1 : fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 | _fpiu_io_in_bits_req_in2_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in2_T_5 = _fpiu_io_in_bits_req_in2_T_4 | _fpiu_io_in_bits_req_in2_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in2_T_7 = _fpiu_io_in_bits_req_in2_T_6 ? fpiu_io_in_bits_req_in2_floats_1 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in2_T_9 = _fpiu_io_in_bits_req_in2_T_8 ? io_frs2_data_0 : _fpiu_io_in_bits_req_in2_T_7; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in2_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _fpiu_io_in_bits_req_in2_T_11 = _fpiu_io_in_bits_req_in2_T_10 ? io_frs2_data_0 : _fpiu_io_in_bits_req_in2_T_9; // @[FPU.scala:15:7] assign _fpiu_io_in_bits_req_in2_T_12 = _fpiu_io_in_bits_req_in2_T_5 ? _fpiu_io_in_bits_req_in2_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:35:19] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = io_frs3_data_0[31]; // @[FPU.scala:15:7] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = io_frs3_data_0[31]; // @[FPU.scala:15:7] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = io_frs3_data_0[31]; // @[FPU.scala:15:7] wire _hfma_io_in_bits_req_in3_prev_unswizzled_T = io_frs3_data_0[31]; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in3_prev_unswizzled_T = io_frs3_data_0[31]; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in3_prev_unswizzled_T = io_frs3_data_0[31]; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = io_frs3_data_0[52]; // @[FPU.scala:15:7] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_frs3_data_0[52]; // @[FPU.scala:15:7] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_frs3_data_0[52]; // @[FPU.scala:15:7] wire _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_frs3_data_0[52]; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in3_prev_unswizzled_T_1 = io_frs3_data_0[52]; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in3_prev_unswizzled_T_1 = io_frs3_data_0[52]; // @[FPU.scala:15:7] wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = io_frs3_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_frs3_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_frs3_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_frs3_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _ifpu_io_in_bits_req_in3_prev_unswizzled_T_2 = io_frs3_data_0[30:0]; // @[FPU.scala:15:7] wire [30:0] _fpmu_io_in_bits_req_in3_prev_unswizzled_T_2 = io_frs3_data_0[30:0]; // @[FPU.scala:15:7] wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_prev_prev_0_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_1 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = io_frs3_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = io_frs3_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = io_frs3_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _hfma_io_in_bits_req_in3_prev_isbox_T = io_frs3_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _ifpu_io_in_bits_req_in3_prev_isbox_T = io_frs3_data_0[64:60]; // @[FPU.scala:15:7] wire [4:0] _fpmu_io_in_bits_req_in3_prev_isbox_T = io_frs3_data_0[64:60]; // @[FPU.scala:15:7] wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_oks_1 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox & fpiu_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T ? fpiu_io_in_bits_req_in3_oks_1 : fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 | _fpiu_io_in_bits_req_in3_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in3_T_5 = _fpiu_io_in_bits_req_in3_T_4 | _fpiu_io_in_bits_req_in3_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_7 = _fpiu_io_in_bits_req_in3_T_6 ? fpiu_io_in_bits_req_in3_floats_1 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_9 = _fpiu_io_in_bits_req_in3_T_8 ? io_frs3_data_0 : _fpiu_io_in_bits_req_in3_T_7; // @[FPU.scala:15:7] wire _fpiu_io_in_bits_req_in3_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _fpiu_io_in_bits_req_in3_T_11 = _fpiu_io_in_bits_req_in3_T_10 ? io_frs3_data_0 : _fpiu_io_in_bits_req_in3_T_9; // @[FPU.scala:15:7] assign _fpiu_io_in_bits_req_in3_T_12 = _fpiu_io_in_bits_req_in3_T_5 ? _fpiu_io_in_bits_req_in3_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in3 = _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:35:19] assign _fpiu_io_in_bits_req_typ_T = io_in_bits_inst_0[21:20]; // @[FPU.scala:15:7, :58:20] wire [1:0] _dfma_io_in_bits_req_typ_T = io_in_bits_inst_0[21:20]; // @[FPU.scala:15:7, :58:20] wire [1:0] _sfma_io_in_bits_req_typ_T = io_in_bits_inst_0[21:20]; // @[FPU.scala:15:7, :58:20] wire [1:0] _hfma_io_in_bits_req_typ_T = io_in_bits_inst_0[21:20]; // @[FPU.scala:15:7, :58:20] wire [1:0] _ifpu_io_in_bits_req_typ_T = io_in_bits_inst_0[21:20]; // @[FPU.scala:15:7, :58:20] wire [1:0] _fpmu_io_in_bits_req_typ_T = io_in_bits_inst_0[21:20]; // @[FPU.scala:15:7, :58:20] assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[FPU.scala:35:19, :58:20] assign _fpiu_io_in_bits_req_fmt_T = io_in_bits_inst_0[26:25]; // @[FPU.scala:15:7, :59:20] wire [1:0] _dfma_io_in_bits_req_fmt_T = io_in_bits_inst_0[26:25]; // @[FPU.scala:15:7, :59:20] wire [1:0] _sfma_io_in_bits_req_fmt_T = io_in_bits_inst_0[26:25]; // @[FPU.scala:15:7, :59:20] wire [1:0] _hfma_io_in_bits_req_fmt_T = io_in_bits_inst_0[26:25]; // @[FPU.scala:15:7, :59:20] wire [1:0] _ifpu_io_in_bits_req_fmt_T = io_in_bits_inst_0[26:25]; // @[FPU.scala:15:7, :59:20] wire [1:0] _fpmu_io_in_bits_req_fmt_T = io_in_bits_inst_0[26:25]; // @[FPU.scala:15:7, :59:20] assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_req_fmt_T; // @[FPU.scala:35:19, :59:20] wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T = io_in_bits_inst_0[3:2]; // @[FPU.scala:15:7, :60:23] wire [1:0] _dfma_io_in_bits_req_fmaCmd_T = io_in_bits_inst_0[3:2]; // @[FPU.scala:15:7, :60:23] wire [1:0] _sfma_io_in_bits_req_fmaCmd_T = io_in_bits_inst_0[3:2]; // @[FPU.scala:15:7, :60:23] wire [1:0] _hfma_io_in_bits_req_fmaCmd_T = io_in_bits_inst_0[3:2]; // @[FPU.scala:15:7, :60:23] wire [1:0] _ifpu_io_in_bits_req_fmaCmd_T = io_in_bits_inst_0[3:2]; // @[FPU.scala:15:7, :60:23] wire [1:0] _fpmu_io_in_bits_req_fmaCmd_T = io_in_bits_inst_0[3:2]; // @[FPU.scala:15:7, :60:23] wire _fpiu_io_in_bits_req_fmaCmd_T_1 = ~io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :60:32] wire _fpiu_io_in_bits_req_fmaCmd_T_2 = io_in_bits_inst_0[27]; // @[FPU.scala:15:7, :60:50] wire _dfma_io_in_bits_req_fmaCmd_T_2 = io_in_bits_inst_0[27]; // @[FPU.scala:15:7, :60:50] wire _sfma_io_in_bits_req_fmaCmd_T_2 = io_in_bits_inst_0[27]; // @[FPU.scala:15:7, :60:50] wire _hfma_io_in_bits_req_fmaCmd_T_2 = io_in_bits_inst_0[27]; // @[FPU.scala:15:7, :60:50] wire _ifpu_io_in_bits_req_fmaCmd_T_2 = io_in_bits_inst_0[27]; // @[FPU.scala:15:7, :60:50] wire _fpmu_io_in_bits_req_fmaCmd_T_2 = io_in_bits_inst_0[27]; // @[FPU.scala:15:7, :60:50] wire _fpiu_io_in_bits_req_fmaCmd_T_3 = _fpiu_io_in_bits_req_fmaCmd_T_1 & _fpiu_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:60:{32,43,50}] assign _fpiu_io_in_bits_req_fmaCmd_T_4 = {_fpiu_io_in_bits_req_fmaCmd_T[1], _fpiu_io_in_bits_req_fmaCmd_T[0] | _fpiu_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:60:{23,29,43}] assign fpiu_io_in_bits_req_fmaCmd = _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:35:19, :60:29] wire _dfma_io_in_valid_T = io_in_bits_fp_ctrl_typeTagOut_0 == 2'h2; // @[FPU.scala:15:7, :84:58] wire _dfma_io_in_valid_T_1 = io_in_valid_0 & _dfma_io_in_valid_T; // @[FPU.scala:15:7, :84:{36,58}] wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T_1 & io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :84:{36,82}] wire [1:0] _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:60:29] wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[FPU.scala:35:19] wire [1:0] dfma_io_in_bits_req_typ; // @[FPU.scala:35:19] wire [1:0] dfma_io_in_bits_req_fmt; // @[FPU.scala:35:19] wire [64:0] dfma_io_in_bits_req_in1; // @[FPU.scala:35:19] wire [64:0] dfma_io_in_bits_req_in2; // @[FPU.scala:35:19] wire [64:0] dfma_io_in_bits_req_in3; // @[FPU.scala:35:19] wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_prev_prev_0_1 = dfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_1 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_oks_1 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox & dfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:35:19] wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_prev_prev_0_1 = dfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_1 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_oks_1 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox & dfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:35:19] wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_prev_prev_0_1 = dfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_1 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_oks_1 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox & dfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in3 = _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:35:19] assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[FPU.scala:35:19, :58:20] assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_req_fmt_T; // @[FPU.scala:35:19, :59:20] wire _dfma_io_in_bits_req_fmaCmd_T_1 = ~io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :60:32] wire _dfma_io_in_bits_req_fmaCmd_T_3 = _dfma_io_in_bits_req_fmaCmd_T_1 & _dfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:60:{32,43,50}] assign _dfma_io_in_bits_req_fmaCmd_T_4 = {_dfma_io_in_bits_req_fmaCmd_T[1], _dfma_io_in_bits_req_fmaCmd_T[0] | _dfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:60:{23,29,43}] assign dfma_io_in_bits_req_fmaCmd = _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:35:19, :60:29] wire _sfma_io_in_valid_T = io_in_bits_fp_ctrl_typeTagOut_0 == 2'h1; // @[FPU.scala:15:7, :84:58] wire _sfma_io_in_valid_T_1 = io_in_valid_0 & _sfma_io_in_valid_T; // @[FPU.scala:15:7, :84:{36,58}] wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T_1 & io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :84:{36,82}] wire [1:0] _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:60:29] wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[FPU.scala:35:19] wire [1:0] sfma_io_in_bits_req_typ; // @[FPU.scala:35:19] wire [1:0] sfma_io_in_bits_req_fmt; // @[FPU.scala:35:19] wire [64:0] sfma_io_in_bits_req_in1; // @[FPU.scala:35:19] wire [64:0] sfma_io_in_bits_req_in2; // @[FPU.scala:35:19] wire [64:0] sfma_io_in_bits_req_in3; // @[FPU.scala:35:19] wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in1_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in1_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in1_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in1_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_prev_prev_0_1 = sfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_oks_1 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox & sfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_sign = io_frs1_data_0[64]; // @[FPU.scala:15:7] wire hfma_io_in_bits_req_in1_sign = io_frs1_data_0[64]; // @[FPU.scala:15:7] wire [51:0] sfma_io_in_bits_req_in1_fractIn = io_frs1_data_0[51:0]; // @[FPU.scala:15:7] wire [51:0] hfma_io_in_bits_req_in1_fractIn = io_frs1_data_0[51:0]; // @[FPU.scala:15:7] wire [11:0] sfma_io_in_bits_req_in1_expIn = io_frs1_data_0[63:52]; // @[FPU.scala:15:7] wire [11:0] hfma_io_in_bits_req_in1_expIn = io_frs1_data_0[63:52]; // @[FPU.scala:15:7] wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T | _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_2 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_1 | _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:35:19, :55:13] wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in2_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in2_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in2_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in2_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_prev_prev_0_1 = sfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_oks_1 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox & sfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_sign = io_frs2_data_0[64]; // @[FPU.scala:15:7] wire hfma_io_in_bits_req_in2_sign = io_frs2_data_0[64]; // @[FPU.scala:15:7] wire [51:0] sfma_io_in_bits_req_in2_fractIn = io_frs2_data_0[51:0]; // @[FPU.scala:15:7] wire [51:0] hfma_io_in_bits_req_in2_fractIn = io_frs2_data_0[51:0]; // @[FPU.scala:15:7] wire [11:0] sfma_io_in_bits_req_in2_expIn = io_frs2_data_0[63:52]; // @[FPU.scala:15:7] wire [11:0] hfma_io_in_bits_req_in2_expIn = io_frs2_data_0[63:52]; // @[FPU.scala:15:7] wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T | _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_2 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_1 | _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:35:19, :55:13, :56:13] wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in3_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in3_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in3_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in3_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_prev_prev_0_1 = sfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_oks_1 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox & sfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_sign = io_frs3_data_0[64]; // @[FPU.scala:15:7] wire hfma_io_in_bits_req_in3_sign = io_frs3_data_0[64]; // @[FPU.scala:15:7] wire [51:0] sfma_io_in_bits_req_in3_fractIn = io_frs3_data_0[51:0]; // @[FPU.scala:15:7] wire [51:0] hfma_io_in_bits_req_in3_fractIn = io_frs3_data_0[51:0]; // @[FPU.scala:15:7] wire [11:0] sfma_io_in_bits_req_in3_expIn = io_frs3_data_0[63:52]; // @[FPU.scala:15:7] wire [11:0] hfma_io_in_bits_req_in3_expIn = io_frs3_data_0[63:52]; // @[FPU.scala:15:7] wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T | _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_2 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_1 | _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in3 = {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:35:19, :55:13, :57:13] assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[FPU.scala:35:19, :58:20] assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:35:19, :59:20] wire _sfma_io_in_bits_req_fmaCmd_T_1 = ~io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :60:32] wire _sfma_io_in_bits_req_fmaCmd_T_3 = _sfma_io_in_bits_req_fmaCmd_T_1 & _sfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:60:{32,43,50}] assign _sfma_io_in_bits_req_fmaCmd_T_4 = {_sfma_io_in_bits_req_fmaCmd_T[1], _sfma_io_in_bits_req_fmaCmd_T[0] | _sfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:60:{23,29,43}] assign sfma_io_in_bits_req_fmaCmd = _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:35:19, :60:29] wire _hfma_io_in_valid_T = io_in_bits_fp_ctrl_typeTagOut_0 == 2'h0; // @[FPU.scala:15:7, :84:58] wire _hfma_io_in_valid_T_1 = io_in_valid_0 & _hfma_io_in_valid_T; // @[FPU.scala:15:7, :84:{36,58}] wire _hfma_io_in_valid_T_2 = _hfma_io_in_valid_T_1 & io_in_bits_fp_ctrl_fma_0; // @[FPU.scala:15:7, :84:{36,82}] wire [1:0] _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:60:29] wire [1:0] hfma_io_in_bits_req_fmaCmd; // @[FPU.scala:35:19] wire [1:0] hfma_io_in_bits_req_typ; // @[FPU.scala:35:19] wire [1:0] hfma_io_in_bits_req_fmt; // @[FPU.scala:35:19] wire [64:0] hfma_io_in_bits_req_in1; // @[FPU.scala:35:19] wire [64:0] hfma_io_in_bits_req_in2; // @[FPU.scala:35:19] wire [64:0] hfma_io_in_bits_req_in3; // @[FPU.scala:35:19] wire [1:0] hfma_io_in_bits_req_in1_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in1_prev_unswizzled = {hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in1_floats_0 = {hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in1_prev_prev_0_1 = hfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in1_prev_prev_sign = hfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in1_prev_prev_fractIn = hfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expIn = hfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = {hfma_io_in_bits_req_in1_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in1_prev_prev_fractOut = _hfma_io_in_bits_req_in1_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = hfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in1_prev_prev_expOut_T | _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in1_prev_prev_expOut = _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in1_prev_prev_hi = {hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in1_floats_1 = {hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in1_prev_isbox = &_hfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in1_oks_1 = hfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in1_oks_0 = hfma_io_in_bits_req_in1_prev_isbox & hfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in1_fractOut_T = {hfma_io_in_bits_req_in1_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in1_fractOut = _hfma_io_in_bits_req_in1_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in1_expOut_expCode = hfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in1_expOut_commonCase = _hfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in1_expOut_T = hfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in1_expOut_T_1 = hfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in1_expOut_T_2 = _hfma_io_in_bits_req_in1_expOut_T | _hfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in1_expOut_T_3 = hfma_io_in_bits_req_in1_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_4 = {hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_5 = hfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in1_expOut = _hfma_io_in_bits_req_in1_expOut_T_2 ? _hfma_io_in_bits_req_in1_expOut_T_4 : _hfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in1_hi = {hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in1_floats_2 = {hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in1_T = hfma_io_in_bits_req_in1_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in1_T_1 = hfma_io_in_bits_req_in1_floats_0 | _hfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in1 = {48'h0, _hfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:35:19, :55:13] wire [1:0] hfma_io_in_bits_req_in2_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in2_prev_unswizzled = {hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in2_floats_0 = {hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in2_prev_prev_0_1 = hfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in2_prev_prev_sign = hfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in2_prev_prev_fractIn = hfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expIn = hfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = {hfma_io_in_bits_req_in2_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in2_prev_prev_fractOut = _hfma_io_in_bits_req_in2_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = hfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in2_prev_prev_expOut_T | _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in2_prev_prev_expOut = _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in2_prev_prev_hi = {hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in2_floats_1 = {hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in2_prev_isbox = &_hfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in2_oks_1 = hfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in2_oks_0 = hfma_io_in_bits_req_in2_prev_isbox & hfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in2_fractOut_T = {hfma_io_in_bits_req_in2_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in2_fractOut = _hfma_io_in_bits_req_in2_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in2_expOut_expCode = hfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in2_expOut_commonCase = _hfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in2_expOut_T = hfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in2_expOut_T_1 = hfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in2_expOut_T_2 = _hfma_io_in_bits_req_in2_expOut_T | _hfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in2_expOut_T_3 = hfma_io_in_bits_req_in2_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_4 = {hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_5 = hfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in2_expOut = _hfma_io_in_bits_req_in2_expOut_T_2 ? _hfma_io_in_bits_req_in2_expOut_T_4 : _hfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in2_hi = {hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in2_floats_2 = {hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in2_T = hfma_io_in_bits_req_in2_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in2_T_1 = hfma_io_in_bits_req_in2_floats_0 | _hfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in2 = {48'h0, _hfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:35:19, :55:13, :56:13] wire [1:0] hfma_io_in_bits_req_in3_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in3_prev_unswizzled = {hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in3_floats_0 = {hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in3_prev_prev_0_1 = hfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in3_prev_prev_sign = hfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in3_prev_prev_fractIn = hfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expIn = hfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = {hfma_io_in_bits_req_in3_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in3_prev_prev_fractOut = _hfma_io_in_bits_req_in3_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = hfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in3_prev_prev_expOut_T | _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in3_prev_prev_expOut = _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in3_prev_prev_hi = {hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in3_floats_1 = {hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in3_prev_isbox = &_hfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in3_oks_1 = hfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in3_oks_0 = hfma_io_in_bits_req_in3_prev_isbox & hfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in3_fractOut_T = {hfma_io_in_bits_req_in3_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in3_fractOut = _hfma_io_in_bits_req_in3_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in3_expOut_expCode = hfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in3_expOut_commonCase = _hfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in3_expOut_T = hfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in3_expOut_T_1 = hfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in3_expOut_T_2 = _hfma_io_in_bits_req_in3_expOut_T | _hfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in3_expOut_T_3 = hfma_io_in_bits_req_in3_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_4 = {hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_5 = hfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in3_expOut = _hfma_io_in_bits_req_in3_expOut_T_2 ? _hfma_io_in_bits_req_in3_expOut_T_4 : _hfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in3_hi = {hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in3_floats_2 = {hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in3_T = hfma_io_in_bits_req_in3_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in3_T_1 = hfma_io_in_bits_req_in3_floats_0 | _hfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in3 = {48'h0, _hfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:35:19, :55:13, :57:13] assign hfma_io_in_bits_req_typ = _hfma_io_in_bits_req_typ_T; // @[FPU.scala:35:19, :58:20] assign hfma_io_in_bits_req_fmt = _hfma_io_in_bits_req_fmt_T; // @[FPU.scala:35:19, :59:20] wire _hfma_io_in_bits_req_fmaCmd_T_1 = ~io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :60:32] wire _hfma_io_in_bits_req_fmaCmd_T_3 = _hfma_io_in_bits_req_fmaCmd_T_1 & _hfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:60:{32,43,50}] assign _hfma_io_in_bits_req_fmaCmd_T_4 = {_hfma_io_in_bits_req_fmaCmd_T[1], _hfma_io_in_bits_req_fmaCmd_T[0] | _hfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:60:{23,29,43}] assign hfma_io_in_bits_req_fmaCmd = _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:35:19, :60:29] wire _ifpu_io_in_valid_T = io_in_valid_0 & io_in_bits_fp_ctrl_fromint_0; // @[FPU.scala:15:7, :89:35] wire [1:0] _ifpu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:60:29] wire [64:0] _ifpu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10] wire [64:0] _ifpu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10] wire [64:0] _ifpu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10] wire [1:0] ifpu_io_in_bits_req_fmaCmd; // @[FPU.scala:35:19] wire [1:0] ifpu_io_in_bits_req_typ; // @[FPU.scala:35:19] wire [1:0] ifpu_io_in_bits_req_fmt; // @[FPU.scala:35:19] wire [64:0] ifpu_io_in_bits_req_in1; // @[FPU.scala:35:19] wire [64:0] ifpu_io_in_bits_req_in2; // @[FPU.scala:35:19] wire [64:0] ifpu_io_in_bits_req_in3; // @[FPU.scala:35:19] wire [1:0] ifpu_io_in_bits_req_in1_prev_unswizzled_hi = {_ifpu_io_in_bits_req_in1_prev_unswizzled_T, _ifpu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] ifpu_io_in_bits_req_in1_prev_unswizzled = {ifpu_io_in_bits_req_in1_prev_unswizzled_hi, _ifpu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = ifpu_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = ifpu_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = ifpu_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled = {ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire ifpu_io_in_bits_req_in1_prev_prev_prev_prev_sign = ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = ifpu_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] ifpu_io_in_bits_req_in1_prev_prev_prev_prev_hi = {ifpu_io_in_bits_req_in1_prev_prev_prev_prev_sign, ifpu_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] ifpu_io_in_bits_req_in1_floats_0 = {ifpu_io_in_bits_req_in1_prev_prev_prev_prev_hi, ifpu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _ifpu_io_in_bits_req_in1_prev_prev_prev_isbox_T = ifpu_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire ifpu_io_in_bits_req_in1_prev_prev_prev_isbox = &_ifpu_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire ifpu_io_in_bits_req_in1_prev_prev_0_1 = ifpu_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire ifpu_io_in_bits_req_in1_prev_prev_sign = ifpu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] ifpu_io_in_bits_req_in1_prev_prev_fractIn = ifpu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] ifpu_io_in_bits_req_in1_prev_prev_expIn = ifpu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _ifpu_io_in_bits_req_in1_prev_prev_fractOut_T = {ifpu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] ifpu_io_in_bits_req_in1_prev_prev_fractOut = _ifpu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode = ifpu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, ifpu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_5 = ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _ifpu_io_in_bits_req_in1_prev_prev_expOut_T = ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_1 = ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _ifpu_io_in_bits_req_in1_prev_prev_expOut_T | _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_3 = ifpu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {ifpu_io_in_bits_req_in1_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] ifpu_io_in_bits_req_in1_prev_prev_expOut = _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _ifpu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] ifpu_io_in_bits_req_in1_prev_prev_hi = {ifpu_io_in_bits_req_in1_prev_prev_sign, ifpu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] ifpu_io_in_bits_req_in1_floats_1 = {ifpu_io_in_bits_req_in1_prev_prev_hi, ifpu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire ifpu_io_in_bits_req_in1_prev_isbox = &_ifpu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire ifpu_io_in_bits_req_in1_oks_1 = ifpu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire ifpu_io_in_bits_req_in1_oks_0 = ifpu_io_in_bits_req_in1_prev_isbox & ifpu_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _ifpu_io_in_bits_req_in1_T_1 = _ifpu_io_in_bits_req_in1_T ? ifpu_io_in_bits_req_in1_oks_1 : ifpu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire _ifpu_io_in_bits_req_in1_T_3 = _ifpu_io_in_bits_req_in1_T_2 | _ifpu_io_in_bits_req_in1_T_1; // @[package.scala:39:{76,86}] wire _ifpu_io_in_bits_req_in1_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in1_T_5 = _ifpu_io_in_bits_req_in1_T_4 | _ifpu_io_in_bits_req_in1_T_3; // @[package.scala:39:{76,86}] wire [64:0] _ifpu_io_in_bits_req_in1_T_7 = _ifpu_io_in_bits_req_in1_T_6 ? ifpu_io_in_bits_req_in1_floats_1 : ifpu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _ifpu_io_in_bits_req_in1_T_9 = _ifpu_io_in_bits_req_in1_T_8 ? io_frs1_data_0 : _ifpu_io_in_bits_req_in1_T_7; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in1_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _ifpu_io_in_bits_req_in1_T_11 = _ifpu_io_in_bits_req_in1_T_10 ? io_frs1_data_0 : _ifpu_io_in_bits_req_in1_T_9; // @[FPU.scala:15:7] assign _ifpu_io_in_bits_req_in1_T_12 = _ifpu_io_in_bits_req_in1_T_5 ? _ifpu_io_in_bits_req_in1_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign ifpu_io_in_bits_req_in1 = _ifpu_io_in_bits_req_in1_T_12; // @[FPU.scala:35:19] wire [1:0] ifpu_io_in_bits_req_in2_prev_unswizzled_hi = {_ifpu_io_in_bits_req_in2_prev_unswizzled_T, _ifpu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] ifpu_io_in_bits_req_in2_prev_unswizzled = {ifpu_io_in_bits_req_in2_prev_unswizzled_hi, _ifpu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = ifpu_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = ifpu_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = ifpu_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled = {ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire ifpu_io_in_bits_req_in2_prev_prev_prev_prev_sign = ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = ifpu_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] ifpu_io_in_bits_req_in2_prev_prev_prev_prev_hi = {ifpu_io_in_bits_req_in2_prev_prev_prev_prev_sign, ifpu_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] ifpu_io_in_bits_req_in2_floats_0 = {ifpu_io_in_bits_req_in2_prev_prev_prev_prev_hi, ifpu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _ifpu_io_in_bits_req_in2_prev_prev_prev_isbox_T = ifpu_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire ifpu_io_in_bits_req_in2_prev_prev_prev_isbox = &_ifpu_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire ifpu_io_in_bits_req_in2_prev_prev_0_1 = ifpu_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire ifpu_io_in_bits_req_in2_prev_prev_sign = ifpu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] ifpu_io_in_bits_req_in2_prev_prev_fractIn = ifpu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] ifpu_io_in_bits_req_in2_prev_prev_expIn = ifpu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _ifpu_io_in_bits_req_in2_prev_prev_fractOut_T = {ifpu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] ifpu_io_in_bits_req_in2_prev_prev_fractOut = _ifpu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode = ifpu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, ifpu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_5 = ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _ifpu_io_in_bits_req_in2_prev_prev_expOut_T = ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_1 = ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _ifpu_io_in_bits_req_in2_prev_prev_expOut_T | _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_3 = ifpu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {ifpu_io_in_bits_req_in2_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] ifpu_io_in_bits_req_in2_prev_prev_expOut = _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _ifpu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] ifpu_io_in_bits_req_in2_prev_prev_hi = {ifpu_io_in_bits_req_in2_prev_prev_sign, ifpu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] ifpu_io_in_bits_req_in2_floats_1 = {ifpu_io_in_bits_req_in2_prev_prev_hi, ifpu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire ifpu_io_in_bits_req_in2_prev_isbox = &_ifpu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire ifpu_io_in_bits_req_in2_oks_1 = ifpu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire ifpu_io_in_bits_req_in2_oks_0 = ifpu_io_in_bits_req_in2_prev_isbox & ifpu_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _ifpu_io_in_bits_req_in2_T_1 = _ifpu_io_in_bits_req_in2_T ? ifpu_io_in_bits_req_in2_oks_1 : ifpu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire _ifpu_io_in_bits_req_in2_T_3 = _ifpu_io_in_bits_req_in2_T_2 | _ifpu_io_in_bits_req_in2_T_1; // @[package.scala:39:{76,86}] wire _ifpu_io_in_bits_req_in2_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in2_T_5 = _ifpu_io_in_bits_req_in2_T_4 | _ifpu_io_in_bits_req_in2_T_3; // @[package.scala:39:{76,86}] wire [64:0] _ifpu_io_in_bits_req_in2_T_7 = _ifpu_io_in_bits_req_in2_T_6 ? ifpu_io_in_bits_req_in2_floats_1 : ifpu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _ifpu_io_in_bits_req_in2_T_9 = _ifpu_io_in_bits_req_in2_T_8 ? io_frs2_data_0 : _ifpu_io_in_bits_req_in2_T_7; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in2_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _ifpu_io_in_bits_req_in2_T_11 = _ifpu_io_in_bits_req_in2_T_10 ? io_frs2_data_0 : _ifpu_io_in_bits_req_in2_T_9; // @[FPU.scala:15:7] assign _ifpu_io_in_bits_req_in2_T_12 = _ifpu_io_in_bits_req_in2_T_5 ? _ifpu_io_in_bits_req_in2_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign ifpu_io_in_bits_req_in2 = _ifpu_io_in_bits_req_in2_T_12; // @[FPU.scala:35:19] wire [1:0] ifpu_io_in_bits_req_in3_prev_unswizzled_hi = {_ifpu_io_in_bits_req_in3_prev_unswizzled_T, _ifpu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] ifpu_io_in_bits_req_in3_prev_unswizzled = {ifpu_io_in_bits_req_in3_prev_unswizzled_hi, _ifpu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = ifpu_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = ifpu_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = ifpu_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled = {ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire ifpu_io_in_bits_req_in3_prev_prev_prev_prev_sign = ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = ifpu_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] ifpu_io_in_bits_req_in3_prev_prev_prev_prev_hi = {ifpu_io_in_bits_req_in3_prev_prev_prev_prev_sign, ifpu_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] ifpu_io_in_bits_req_in3_floats_0 = {ifpu_io_in_bits_req_in3_prev_prev_prev_prev_hi, ifpu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _ifpu_io_in_bits_req_in3_prev_prev_prev_isbox_T = ifpu_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire ifpu_io_in_bits_req_in3_prev_prev_prev_isbox = &_ifpu_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire ifpu_io_in_bits_req_in3_prev_prev_0_1 = ifpu_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire ifpu_io_in_bits_req_in3_prev_prev_sign = ifpu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] ifpu_io_in_bits_req_in3_prev_prev_fractIn = ifpu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] ifpu_io_in_bits_req_in3_prev_prev_expIn = ifpu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _ifpu_io_in_bits_req_in3_prev_prev_fractOut_T = {ifpu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] ifpu_io_in_bits_req_in3_prev_prev_fractOut = _ifpu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode = ifpu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, ifpu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_5 = ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _ifpu_io_in_bits_req_in3_prev_prev_expOut_T = ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_1 = ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _ifpu_io_in_bits_req_in3_prev_prev_expOut_T | _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_3 = ifpu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {ifpu_io_in_bits_req_in3_prev_prev_expOut_expCode, _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] ifpu_io_in_bits_req_in3_prev_prev_expOut = _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _ifpu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] ifpu_io_in_bits_req_in3_prev_prev_hi = {ifpu_io_in_bits_req_in3_prev_prev_sign, ifpu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] ifpu_io_in_bits_req_in3_floats_1 = {ifpu_io_in_bits_req_in3_prev_prev_hi, ifpu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire ifpu_io_in_bits_req_in3_prev_isbox = &_ifpu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire ifpu_io_in_bits_req_in3_oks_1 = ifpu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire ifpu_io_in_bits_req_in3_oks_0 = ifpu_io_in_bits_req_in3_prev_isbox & ifpu_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _ifpu_io_in_bits_req_in3_T_1 = _ifpu_io_in_bits_req_in3_T ? ifpu_io_in_bits_req_in3_oks_1 : ifpu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire _ifpu_io_in_bits_req_in3_T_3 = _ifpu_io_in_bits_req_in3_T_2 | _ifpu_io_in_bits_req_in3_T_1; // @[package.scala:39:{76,86}] wire _ifpu_io_in_bits_req_in3_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in3_T_5 = _ifpu_io_in_bits_req_in3_T_4 | _ifpu_io_in_bits_req_in3_T_3; // @[package.scala:39:{76,86}] wire [64:0] _ifpu_io_in_bits_req_in3_T_7 = _ifpu_io_in_bits_req_in3_T_6 ? ifpu_io_in_bits_req_in3_floats_1 : ifpu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _ifpu_io_in_bits_req_in3_T_9 = _ifpu_io_in_bits_req_in3_T_8 ? io_frs3_data_0 : _ifpu_io_in_bits_req_in3_T_7; // @[FPU.scala:15:7] wire _ifpu_io_in_bits_req_in3_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _ifpu_io_in_bits_req_in3_T_11 = _ifpu_io_in_bits_req_in3_T_10 ? io_frs3_data_0 : _ifpu_io_in_bits_req_in3_T_9; // @[FPU.scala:15:7] assign _ifpu_io_in_bits_req_in3_T_12 = _ifpu_io_in_bits_req_in3_T_5 ? _ifpu_io_in_bits_req_in3_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign ifpu_io_in_bits_req_in3 = _ifpu_io_in_bits_req_in3_T_12; // @[FPU.scala:35:19] assign ifpu_io_in_bits_req_typ = _ifpu_io_in_bits_req_typ_T; // @[FPU.scala:35:19, :58:20] assign ifpu_io_in_bits_req_fmt = _ifpu_io_in_bits_req_fmt_T; // @[FPU.scala:35:19, :59:20] wire _ifpu_io_in_bits_req_fmaCmd_T_1 = ~io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :60:32] wire _ifpu_io_in_bits_req_fmaCmd_T_3 = _ifpu_io_in_bits_req_fmaCmd_T_1 & _ifpu_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:60:{32,43,50}] assign _ifpu_io_in_bits_req_fmaCmd_T_4 = {_ifpu_io_in_bits_req_fmaCmd_T[1], _ifpu_io_in_bits_req_fmaCmd_T[0] | _ifpu_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:60:{23,29,43}] assign ifpu_io_in_bits_req_fmaCmd = _ifpu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:35:19, :60:29] wire _fpmu_io_in_valid_T = io_in_valid_0 & io_in_bits_fp_ctrl_fastpipe_0; // @[FPU.scala:15:7, :95:35] wire [1:0] _fpmu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:60:29] wire [64:0] _fpmu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10] wire [64:0] _fpmu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10] wire [64:0] _fpmu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10] wire [1:0] fpmu_io_in_bits_req_fmaCmd; // @[FPU.scala:35:19] wire [1:0] fpmu_io_in_bits_req_typ; // @[FPU.scala:35:19] wire [1:0] fpmu_io_in_bits_req_fmt; // @[FPU.scala:35:19] wire [64:0] fpmu_io_in_bits_req_in1; // @[FPU.scala:35:19] wire [64:0] fpmu_io_in_bits_req_in2; // @[FPU.scala:35:19] wire [64:0] fpmu_io_in_bits_req_in3; // @[FPU.scala:35:19] wire [1:0] fpmu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpmu_io_in_bits_req_in1_prev_unswizzled_T, _fpmu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpmu_io_in_bits_req_in1_prev_unswizzled = {fpmu_io_in_bits_req_in1_prev_unswizzled_hi, _fpmu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = fpmu_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = fpmu_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = fpmu_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled = {fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpmu_io_in_bits_req_in1_prev_prev_prev_prev_sign = fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = fpmu_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpmu_io_in_bits_req_in1_prev_prev_prev_prev_hi = {fpmu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpmu_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpmu_io_in_bits_req_in1_floats_0 = {fpmu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpmu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpmu_io_in_bits_req_in1_prev_prev_prev_isbox_T = fpmu_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpmu_io_in_bits_req_in1_prev_prev_prev_isbox = &_fpmu_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpmu_io_in_bits_req_in1_prev_prev_0_1 = fpmu_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpmu_io_in_bits_req_in1_prev_prev_sign = fpmu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpmu_io_in_bits_req_in1_prev_prev_fractIn = fpmu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpmu_io_in_bits_req_in1_prev_prev_expIn = fpmu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpmu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpmu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpmu_io_in_bits_req_in1_prev_prev_fractOut = _fpmu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpmu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpmu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpmu_io_in_bits_req_in1_prev_prev_expOut_T = fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpmu_io_in_bits_req_in1_prev_prev_expOut_T | _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpmu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpmu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpmu_io_in_bits_req_in1_prev_prev_expOut = _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpmu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpmu_io_in_bits_req_in1_prev_prev_hi = {fpmu_io_in_bits_req_in1_prev_prev_sign, fpmu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpmu_io_in_bits_req_in1_floats_1 = {fpmu_io_in_bits_req_in1_prev_prev_hi, fpmu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpmu_io_in_bits_req_in1_prev_isbox = &_fpmu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpmu_io_in_bits_req_in1_oks_1 = fpmu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpmu_io_in_bits_req_in1_oks_0 = fpmu_io_in_bits_req_in1_prev_isbox & fpmu_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpmu_io_in_bits_req_in1_T_1 = _fpmu_io_in_bits_req_in1_T ? fpmu_io_in_bits_req_in1_oks_1 : fpmu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire _fpmu_io_in_bits_req_in1_T_3 = _fpmu_io_in_bits_req_in1_T_2 | _fpmu_io_in_bits_req_in1_T_1; // @[package.scala:39:{76,86}] wire _fpmu_io_in_bits_req_in1_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in1_T_5 = _fpmu_io_in_bits_req_in1_T_4 | _fpmu_io_in_bits_req_in1_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpmu_io_in_bits_req_in1_T_7 = _fpmu_io_in_bits_req_in1_T_6 ? fpmu_io_in_bits_req_in1_floats_1 : fpmu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpmu_io_in_bits_req_in1_T_9 = _fpmu_io_in_bits_req_in1_T_8 ? io_frs1_data_0 : _fpmu_io_in_bits_req_in1_T_7; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in1_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _fpmu_io_in_bits_req_in1_T_11 = _fpmu_io_in_bits_req_in1_T_10 ? io_frs1_data_0 : _fpmu_io_in_bits_req_in1_T_9; // @[FPU.scala:15:7] assign _fpmu_io_in_bits_req_in1_T_12 = _fpmu_io_in_bits_req_in1_T_5 ? _fpmu_io_in_bits_req_in1_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpmu_io_in_bits_req_in1 = _fpmu_io_in_bits_req_in1_T_12; // @[FPU.scala:35:19] wire [1:0] fpmu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpmu_io_in_bits_req_in2_prev_unswizzled_T, _fpmu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpmu_io_in_bits_req_in2_prev_unswizzled = {fpmu_io_in_bits_req_in2_prev_unswizzled_hi, _fpmu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = fpmu_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = fpmu_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = fpmu_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled = {fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpmu_io_in_bits_req_in2_prev_prev_prev_prev_sign = fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = fpmu_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpmu_io_in_bits_req_in2_prev_prev_prev_prev_hi = {fpmu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpmu_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpmu_io_in_bits_req_in2_floats_0 = {fpmu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpmu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpmu_io_in_bits_req_in2_prev_prev_prev_isbox_T = fpmu_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpmu_io_in_bits_req_in2_prev_prev_prev_isbox = &_fpmu_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpmu_io_in_bits_req_in2_prev_prev_0_1 = fpmu_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpmu_io_in_bits_req_in2_prev_prev_sign = fpmu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpmu_io_in_bits_req_in2_prev_prev_fractIn = fpmu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpmu_io_in_bits_req_in2_prev_prev_expIn = fpmu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpmu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpmu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpmu_io_in_bits_req_in2_prev_prev_fractOut = _fpmu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpmu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpmu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpmu_io_in_bits_req_in2_prev_prev_expOut_T = fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpmu_io_in_bits_req_in2_prev_prev_expOut_T | _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpmu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpmu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpmu_io_in_bits_req_in2_prev_prev_expOut = _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpmu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpmu_io_in_bits_req_in2_prev_prev_hi = {fpmu_io_in_bits_req_in2_prev_prev_sign, fpmu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpmu_io_in_bits_req_in2_floats_1 = {fpmu_io_in_bits_req_in2_prev_prev_hi, fpmu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpmu_io_in_bits_req_in2_prev_isbox = &_fpmu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpmu_io_in_bits_req_in2_oks_1 = fpmu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpmu_io_in_bits_req_in2_oks_0 = fpmu_io_in_bits_req_in2_prev_isbox & fpmu_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpmu_io_in_bits_req_in2_T_1 = _fpmu_io_in_bits_req_in2_T ? fpmu_io_in_bits_req_in2_oks_1 : fpmu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire _fpmu_io_in_bits_req_in2_T_3 = _fpmu_io_in_bits_req_in2_T_2 | _fpmu_io_in_bits_req_in2_T_1; // @[package.scala:39:{76,86}] wire _fpmu_io_in_bits_req_in2_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in2_T_5 = _fpmu_io_in_bits_req_in2_T_4 | _fpmu_io_in_bits_req_in2_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpmu_io_in_bits_req_in2_T_7 = _fpmu_io_in_bits_req_in2_T_6 ? fpmu_io_in_bits_req_in2_floats_1 : fpmu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpmu_io_in_bits_req_in2_T_9 = _fpmu_io_in_bits_req_in2_T_8 ? io_frs2_data_0 : _fpmu_io_in_bits_req_in2_T_7; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in2_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _fpmu_io_in_bits_req_in2_T_11 = _fpmu_io_in_bits_req_in2_T_10 ? io_frs2_data_0 : _fpmu_io_in_bits_req_in2_T_9; // @[FPU.scala:15:7] assign _fpmu_io_in_bits_req_in2_T_12 = _fpmu_io_in_bits_req_in2_T_5 ? _fpmu_io_in_bits_req_in2_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpmu_io_in_bits_req_in2 = _fpmu_io_in_bits_req_in2_T_12; // @[FPU.scala:35:19] wire [1:0] fpmu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpmu_io_in_bits_req_in3_prev_unswizzled_T, _fpmu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpmu_io_in_bits_req_in3_prev_unswizzled = {fpmu_io_in_bits_req_in3_prev_unswizzled_hi, _fpmu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = fpmu_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = fpmu_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = fpmu_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled = {fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpmu_io_in_bits_req_in3_prev_prev_prev_prev_sign = fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = fpmu_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpmu_io_in_bits_req_in3_prev_prev_prev_prev_hi = {fpmu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpmu_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpmu_io_in_bits_req_in3_floats_0 = {fpmu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpmu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpmu_io_in_bits_req_in3_prev_prev_prev_isbox_T = fpmu_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpmu_io_in_bits_req_in3_prev_prev_prev_isbox = &_fpmu_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpmu_io_in_bits_req_in3_prev_prev_0_1 = fpmu_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpmu_io_in_bits_req_in3_prev_prev_sign = fpmu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpmu_io_in_bits_req_in3_prev_prev_fractIn = fpmu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpmu_io_in_bits_req_in3_prev_prev_expIn = fpmu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpmu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpmu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpmu_io_in_bits_req_in3_prev_prev_fractOut = _fpmu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpmu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpmu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpmu_io_in_bits_req_in3_prev_prev_expOut_T = fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpmu_io_in_bits_req_in3_prev_prev_expOut_T | _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpmu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpmu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpmu_io_in_bits_req_in3_prev_prev_expOut = _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpmu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpmu_io_in_bits_req_in3_prev_prev_hi = {fpmu_io_in_bits_req_in3_prev_prev_sign, fpmu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpmu_io_in_bits_req_in3_floats_1 = {fpmu_io_in_bits_req_in3_prev_prev_hi, fpmu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpmu_io_in_bits_req_in3_prev_isbox = &_fpmu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpmu_io_in_bits_req_in3_oks_1 = fpmu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpmu_io_in_bits_req_in3_oks_0 = fpmu_io_in_bits_req_in3_prev_isbox & fpmu_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpmu_io_in_bits_req_in3_T_1 = _fpmu_io_in_bits_req_in3_T ? fpmu_io_in_bits_req_in3_oks_1 : fpmu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire _fpmu_io_in_bits_req_in3_T_3 = _fpmu_io_in_bits_req_in3_T_2 | _fpmu_io_in_bits_req_in3_T_1; // @[package.scala:39:{76,86}] wire _fpmu_io_in_bits_req_in3_T_4 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in3_T_5 = _fpmu_io_in_bits_req_in3_T_4 | _fpmu_io_in_bits_req_in3_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpmu_io_in_bits_req_in3_T_7 = _fpmu_io_in_bits_req_in3_T_6 ? fpmu_io_in_bits_req_in3_floats_1 : fpmu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpmu_io_in_bits_req_in3_T_9 = _fpmu_io_in_bits_req_in3_T_8 ? io_frs3_data_0 : _fpmu_io_in_bits_req_in3_T_7; // @[FPU.scala:15:7] wire _fpmu_io_in_bits_req_in3_T_10 = &io_in_bits_fp_ctrl_typeTagIn_0; // @[FPU.scala:15:7] wire [64:0] _fpmu_io_in_bits_req_in3_T_11 = _fpmu_io_in_bits_req_in3_T_10 ? io_frs3_data_0 : _fpmu_io_in_bits_req_in3_T_9; // @[FPU.scala:15:7] assign _fpmu_io_in_bits_req_in3_T_12 = _fpmu_io_in_bits_req_in3_T_5 ? _fpmu_io_in_bits_req_in3_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpmu_io_in_bits_req_in3 = _fpmu_io_in_bits_req_in3_T_12; // @[FPU.scala:35:19] assign fpmu_io_in_bits_req_typ = _fpmu_io_in_bits_req_typ_T; // @[FPU.scala:35:19, :58:20] assign fpmu_io_in_bits_req_fmt = _fpmu_io_in_bits_req_fmt_T; // @[FPU.scala:35:19, :59:20] wire _fpmu_io_in_bits_req_fmaCmd_T_1 = ~io_in_bits_fp_ctrl_ren3_0; // @[FPU.scala:15:7, :60:32] wire _fpmu_io_in_bits_req_fmaCmd_T_3 = _fpmu_io_in_bits_req_fmaCmd_T_1 & _fpmu_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:60:{32,43,50}] assign _fpmu_io_in_bits_req_fmaCmd_T_4 = {_fpmu_io_in_bits_req_fmaCmd_T[1], _fpmu_io_in_bits_req_fmaCmd_T[0] | _fpmu_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:60:{23,29,43}] assign fpmu_io_in_bits_req_fmaCmd = _fpmu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:35:19, :60:29] wire _io_out_valid_T_1 = _io_out_valid_T | io_in_bits_fp_ctrl_sqrt_0; // @[FPU.scala:15:7, :99:{65,80}] wire _io_out_valid_T_2 = ~_io_out_valid_T_1; // @[FPU.scala:99:{49,80}] wire _io_out_valid_T_3 = io_in_valid_0 & _io_out_valid_T_2; // @[FPU.scala:15:7, :99:{46,49}] reg io_out_valid_r; // @[FPU.scala:99:33] reg io_out_valid_r_1; // @[FPU.scala:99:33] reg io_out_valid_r_2; // @[FPU.scala:99:33] reg io_out_valid_r_3; // @[FPU.scala:99:33] reg io_out_valid_r_4; // @[FPU.scala:100:22] reg io_out_valid_r_5; // @[FPU.scala:100:22] reg io_out_valid_r_6; // @[FPU.scala:100:22] wire _io_out_valid_T_4 = ~io_out_valid_r_6; // @[FPU.scala:100:{8,22}] wire _io_out_valid_T_5 = io_out_valid_r_3 & _io_out_valid_T_4; // @[FPU.scala:99:33, :100:{5,8}] assign _io_out_valid_T_7 = _io_out_valid_T_5; // @[FPU.scala:100:5, :101:5] assign io_out_valid_0 = _io_out_valid_T_7; // @[FPU.scala:15:7, :101:5] wire [64:0] _io_out_bits_WIRE_2; // @[Mux.scala:30:73] assign io_out_bits_data_0 = _io_out_bits_WIRE_data; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_WIRE_1; // @[Mux.scala:30:73] assign io_out_bits_exc_0 = _io_out_bits_WIRE_exc; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T = _dfma_io_out_valid ? _dfma_io_out_bits_exc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_1 = _sfma_io_out_valid ? _sfma_io_out_bits_exc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_2 = _hfma_io_out_valid ? _hfma_io_out_bits_exc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_3 = _ifpu_io_out_valid ? _ifpu_io_out_bits_exc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_4 = _fpmu_io_out_valid ? _fpmu_io_out_bits_exc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_5 = _io_out_bits_T | _io_out_bits_T_1; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_6 = _io_out_bits_T_5 | _io_out_bits_T_2; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_7 = _io_out_bits_T_6 | _io_out_bits_T_3; // @[Mux.scala:30:73] wire [4:0] _io_out_bits_T_8 = _io_out_bits_T_7 | _io_out_bits_T_4; // @[Mux.scala:30:73] assign _io_out_bits_WIRE_1 = _io_out_bits_T_8; // @[Mux.scala:30:73] assign _io_out_bits_WIRE_exc = _io_out_bits_WIRE_1; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_9 = _dfma_io_out_valid ? _dfma_io_out_bits_data : 65'h0; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_10 = _sfma_io_out_valid ? _sfma_io_out_bits_data : 65'h0; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_11 = _hfma_io_out_valid ? _hfma_io_out_bits_data : 65'h0; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_12 = _ifpu_io_out_valid ? _ifpu_io_out_bits_data : 65'h0; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_13 = _fpmu_io_out_valid ? _fpmu_io_out_bits_data : 65'h0; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_14 = _io_out_bits_T_9 | _io_out_bits_T_10; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_15 = _io_out_bits_T_14 | _io_out_bits_T_11; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_16 = _io_out_bits_T_15 | _io_out_bits_T_12; // @[Mux.scala:30:73] wire [64:0] _io_out_bits_T_17 = _io_out_bits_T_16 | _io_out_bits_T_13; // @[Mux.scala:30:73] assign _io_out_bits_WIRE_2 = _io_out_bits_T_17; // @[Mux.scala:30:73] assign _io_out_bits_WIRE_data = _io_out_bits_WIRE_2; // @[Mux.scala:30:73] wire [4:0] _io_out_rd_T = io_in_bits_inst_0[11:7]; // @[FPU.scala:15:7] reg [4:0] io_out_rd_r; // @[FPU.scala:106:29] reg [4:0] io_out_rd_r_1; // @[FPU.scala:106:29] reg [4:0] io_out_rd_r_2; // @[FPU.scala:106:29] reg [4:0] io_out_rd_r_3; // @[FPU.scala:106:29] assign io_out_rd_0 = io_out_rd_r_3; // @[FPU.scala:15:7, :106:29] reg [1:0] io_out_tag_r; // @[FPU.scala:107:30] reg [1:0] io_out_tag_r_1; // @[FPU.scala:107:30] reg [1:0] io_out_tag_r_2; // @[FPU.scala:107:30] reg [1:0] io_out_tag_r_3; // @[FPU.scala:107:30] assign io_out_tag_0 = io_out_tag_r_3; // @[FPU.scala:15:7, :107:30] always @(posedge clock) begin // @[FPU.scala:15:7] io_out_valid_r <= _io_out_valid_T_3; // @[FPU.scala:99:{33,46}] io_out_valid_r_1 <= io_out_valid_r; // @[FPU.scala:99:33] io_out_valid_r_2 <= io_out_valid_r_1; // @[FPU.scala:99:33] io_out_valid_r_3 <= io_out_valid_r_2; // @[FPU.scala:99:33] io_out_valid_r_4 <= io_s1_kill_0; // @[FPU.scala:15:7, :100:22] io_out_valid_r_5 <= io_out_valid_r_4; // @[FPU.scala:100:22] io_out_valid_r_6 <= io_out_valid_r_5; // @[FPU.scala:100:22] io_out_rd_r <= _io_out_rd_T; // @[FPU.scala:106:29] io_out_rd_r_1 <= io_out_rd_r; // @[FPU.scala:106:29] io_out_rd_r_2 <= io_out_rd_r_1; // @[FPU.scala:106:29] io_out_rd_r_3 <= io_out_rd_r_2; // @[FPU.scala:106:29] io_out_tag_r <= io_in_bits_fp_ctrl_typeTagOut_0; // @[FPU.scala:15:7, :107:30] io_out_tag_r_1 <= io_out_tag_r; // @[FPU.scala:107:30] io_out_tag_r_2 <= io_out_tag_r_1; // @[FPU.scala:107:30] io_out_tag_r_3 <= io_out_tag_r_2; // @[FPU.scala:107:30] always @(posedge) FPToInt fpiu ( // @[FPU.scala:71:20] .clock (clock), .reset (reset), .io_in_valid (_fpiu_io_in_valid_T_4), // @[FPU.scala:72:35] .io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[FPU.scala:35:19] .io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[FPU.scala:35:19] .io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[FPU.scala:35:19] .io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[FPU.scala:35:19] .io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[FPU.scala:35:19] .io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[FPU.scala:35:19] .io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[FPU.scala:35:19] .io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[FPU.scala:35:19] .io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[FPU.scala:35:19] .io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[FPU.scala:35:19] .io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[FPU.scala:35:19] .io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[FPU.scala:35:19] .io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[FPU.scala:35:19] .io_in_bits_div (fpiu_io_in_bits_req_div), // @[FPU.scala:35:19] .io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[FPU.scala:35:19] .io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[FPU.scala:35:19] .io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[FPU.scala:35:19] .io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[FPU.scala:35:19] .io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[FPU.scala:35:19] .io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[FPU.scala:35:19] .io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[FPU.scala:35:19] .io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[FPU.scala:35:19] .io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[FPU.scala:35:19] .io_out_bits_in_ldst (io_s1_fpiu_fdiv_ldst_0), .io_out_bits_in_wen (io_s1_fpiu_fdiv_wen_0), .io_out_bits_in_ren1 (io_s1_fpiu_fdiv_ren1_0), .io_out_bits_in_ren2 (io_s1_fpiu_fdiv_ren2_0), .io_out_bits_in_ren3 (io_s1_fpiu_fdiv_ren3_0), .io_out_bits_in_swap12 (io_s1_fpiu_fdiv_swap12_0), .io_out_bits_in_swap23 (io_s1_fpiu_fdiv_swap23_0), .io_out_bits_in_typeTagIn (io_s1_fpiu_fdiv_typeTagIn_0), .io_out_bits_in_typeTagOut (io_s1_fpiu_fdiv_typeTagOut_0), .io_out_bits_in_fromint (io_s1_fpiu_fdiv_fromint_0), .io_out_bits_in_toint (io_s1_fpiu_fdiv_toint_0), .io_out_bits_in_fastpipe (io_s1_fpiu_fdiv_fastpipe_0), .io_out_bits_in_fma (io_s1_fpiu_fdiv_fma_0), .io_out_bits_in_div (io_s1_fpiu_fdiv_div_0), .io_out_bits_in_sqrt (io_s1_fpiu_fdiv_sqrt_0), .io_out_bits_in_wflags (io_s1_fpiu_fdiv_wflags_0), .io_out_bits_in_rm (io_s1_fpiu_fdiv_rm_0), .io_out_bits_in_fmaCmd (io_s1_fpiu_fdiv_fmaCmd_0), .io_out_bits_in_typ (io_s1_fpiu_fdiv_typ_0), .io_out_bits_in_fmt (io_s1_fpiu_fdiv_fmt_0), .io_out_bits_in_in1 (io_s1_fpiu_fdiv_in1_0), .io_out_bits_in_in2 (io_s1_fpiu_fdiv_in2_0), .io_out_bits_in_in3 (io_s1_fpiu_fdiv_in3_0), .io_out_bits_lt (_fpiu_io_out_bits_lt), .io_out_bits_store (io_s1_store_data_0), .io_out_bits_toint (io_s1_fpiu_toint_0), .io_out_bits_exc (io_s1_fpiu_fexc_0) ); // @[FPU.scala:71:20] FPUFMAPipe_l4_f64 dfma ( // @[FPU.scala:79:20] .clock (clock), .reset (reset), .io_in_valid (_dfma_io_in_valid_T_2), // @[FPU.scala:84:82] .io_in_bits_ldst (dfma_io_in_bits_req_ldst), // @[FPU.scala:35:19] .io_in_bits_wen (dfma_io_in_bits_req_wen), // @[FPU.scala:35:19] .io_in_bits_ren1 (dfma_io_in_bits_req_ren1), // @[FPU.scala:35:19] .io_in_bits_ren2 (dfma_io_in_bits_req_ren2), // @[FPU.scala:35:19] .io_in_bits_ren3 (dfma_io_in_bits_req_ren3), // @[FPU.scala:35:19] .io_in_bits_swap12 (dfma_io_in_bits_req_swap12), // @[FPU.scala:35:19] .io_in_bits_swap23 (dfma_io_in_bits_req_swap23), // @[FPU.scala:35:19] .io_in_bits_typeTagIn (dfma_io_in_bits_req_typeTagIn), // @[FPU.scala:35:19] .io_in_bits_typeTagOut (dfma_io_in_bits_req_typeTagOut), // @[FPU.scala:35:19] .io_in_bits_fromint (dfma_io_in_bits_req_fromint), // @[FPU.scala:35:19] .io_in_bits_toint (dfma_io_in_bits_req_toint), // @[FPU.scala:35:19] .io_in_bits_fastpipe (dfma_io_in_bits_req_fastpipe), // @[FPU.scala:35:19] .io_in_bits_fma (dfma_io_in_bits_req_fma), // @[FPU.scala:35:19] .io_in_bits_div (dfma_io_in_bits_req_div), // @[FPU.scala:35:19] .io_in_bits_sqrt (dfma_io_in_bits_req_sqrt), // @[FPU.scala:35:19] .io_in_bits_wflags (dfma_io_in_bits_req_wflags), // @[FPU.scala:35:19] .io_in_bits_rm (dfma_io_in_bits_req_rm), // @[FPU.scala:35:19] .io_in_bits_fmaCmd (dfma_io_in_bits_req_fmaCmd), // @[FPU.scala:35:19] .io_in_bits_typ (dfma_io_in_bits_req_typ), // @[FPU.scala:35:19] .io_in_bits_fmt (dfma_io_in_bits_req_fmt), // @[FPU.scala:35:19] .io_in_bits_in1 (dfma_io_in_bits_req_in1), // @[FPU.scala:35:19] .io_in_bits_in2 (dfma_io_in_bits_req_in2), // @[FPU.scala:35:19] .io_in_bits_in3 (dfma_io_in_bits_req_in3), // @[FPU.scala:35:19] .io_out_valid (_dfma_io_out_valid), .io_out_bits_data (_dfma_io_out_bits_data), .io_out_bits_exc (_dfma_io_out_bits_exc) ); // @[FPU.scala:79:20] FPUFMAPipe_l4_f32 sfma ( // @[FPU.scala:80:20] .clock (clock), .reset (reset), .io_in_valid (_sfma_io_in_valid_T_2), // @[FPU.scala:84:82] .io_in_bits_ldst (sfma_io_in_bits_req_ldst), // @[FPU.scala:35:19] .io_in_bits_wen (sfma_io_in_bits_req_wen), // @[FPU.scala:35:19] .io_in_bits_ren1 (sfma_io_in_bits_req_ren1), // @[FPU.scala:35:19] .io_in_bits_ren2 (sfma_io_in_bits_req_ren2), // @[FPU.scala:35:19] .io_in_bits_ren3 (sfma_io_in_bits_req_ren3), // @[FPU.scala:35:19] .io_in_bits_swap12 (sfma_io_in_bits_req_swap12), // @[FPU.scala:35:19] .io_in_bits_swap23 (sfma_io_in_bits_req_swap23), // @[FPU.scala:35:19] .io_in_bits_typeTagIn (sfma_io_in_bits_req_typeTagIn), // @[FPU.scala:35:19] .io_in_bits_typeTagOut (sfma_io_in_bits_req_typeTagOut), // @[FPU.scala:35:19] .io_in_bits_fromint (sfma_io_in_bits_req_fromint), // @[FPU.scala:35:19] .io_in_bits_toint (sfma_io_in_bits_req_toint), // @[FPU.scala:35:19] .io_in_bits_fastpipe (sfma_io_in_bits_req_fastpipe), // @[FPU.scala:35:19] .io_in_bits_fma (sfma_io_in_bits_req_fma), // @[FPU.scala:35:19] .io_in_bits_div (sfma_io_in_bits_req_div), // @[FPU.scala:35:19] .io_in_bits_sqrt (sfma_io_in_bits_req_sqrt), // @[FPU.scala:35:19] .io_in_bits_wflags (sfma_io_in_bits_req_wflags), // @[FPU.scala:35:19] .io_in_bits_rm (sfma_io_in_bits_req_rm), // @[FPU.scala:35:19] .io_in_bits_fmaCmd (sfma_io_in_bits_req_fmaCmd), // @[FPU.scala:35:19] .io_in_bits_typ (sfma_io_in_bits_req_typ), // @[FPU.scala:35:19] .io_in_bits_fmt (sfma_io_in_bits_req_fmt), // @[FPU.scala:35:19] .io_in_bits_in1 (sfma_io_in_bits_req_in1), // @[FPU.scala:35:19] .io_in_bits_in2 (sfma_io_in_bits_req_in2), // @[FPU.scala:35:19] .io_in_bits_in3 (sfma_io_in_bits_req_in3), // @[FPU.scala:35:19] .io_out_valid (_sfma_io_out_valid), .io_out_bits_data (_sfma_io_out_bits_data), .io_out_bits_exc (_sfma_io_out_bits_exc) ); // @[FPU.scala:80:20] FPUFMAPipe_l4_f16 hfma ( // @[FPU.scala:81:20] .clock (clock), .reset (reset), .io_in_valid (_hfma_io_in_valid_T_2), // @[FPU.scala:84:82] .io_in_bits_ldst (hfma_io_in_bits_req_ldst), // @[FPU.scala:35:19] .io_in_bits_wen (hfma_io_in_bits_req_wen), // @[FPU.scala:35:19] .io_in_bits_ren1 (hfma_io_in_bits_req_ren1), // @[FPU.scala:35:19] .io_in_bits_ren2 (hfma_io_in_bits_req_ren2), // @[FPU.scala:35:19] .io_in_bits_ren3 (hfma_io_in_bits_req_ren3), // @[FPU.scala:35:19] .io_in_bits_swap12 (hfma_io_in_bits_req_swap12), // @[FPU.scala:35:19] .io_in_bits_swap23 (hfma_io_in_bits_req_swap23), // @[FPU.scala:35:19] .io_in_bits_typeTagIn (hfma_io_in_bits_req_typeTagIn), // @[FPU.scala:35:19] .io_in_bits_typeTagOut (hfma_io_in_bits_req_typeTagOut), // @[FPU.scala:35:19] .io_in_bits_fromint (hfma_io_in_bits_req_fromint), // @[FPU.scala:35:19] .io_in_bits_toint (hfma_io_in_bits_req_toint), // @[FPU.scala:35:19] .io_in_bits_fastpipe (hfma_io_in_bits_req_fastpipe), // @[FPU.scala:35:19] .io_in_bits_fma (hfma_io_in_bits_req_fma), // @[FPU.scala:35:19] .io_in_bits_div (hfma_io_in_bits_req_div), // @[FPU.scala:35:19] .io_in_bits_sqrt (hfma_io_in_bits_req_sqrt), // @[FPU.scala:35:19] .io_in_bits_wflags (hfma_io_in_bits_req_wflags), // @[FPU.scala:35:19] .io_in_bits_rm (hfma_io_in_bits_req_rm), // @[FPU.scala:35:19] .io_in_bits_fmaCmd (hfma_io_in_bits_req_fmaCmd), // @[FPU.scala:35:19] .io_in_bits_typ (hfma_io_in_bits_req_typ), // @[FPU.scala:35:19] .io_in_bits_fmt (hfma_io_in_bits_req_fmt), // @[FPU.scala:35:19] .io_in_bits_in1 (hfma_io_in_bits_req_in1), // @[FPU.scala:35:19] .io_in_bits_in2 (hfma_io_in_bits_req_in2), // @[FPU.scala:35:19] .io_in_bits_in3 (hfma_io_in_bits_req_in3), // @[FPU.scala:35:19] .io_out_valid (_hfma_io_out_valid), .io_out_bits_data (_hfma_io_out_bits_data), .io_out_bits_exc (_hfma_io_out_bits_exc) ); // @[FPU.scala:81:20] IntToFP ifpu ( // @[FPU.scala:88:20] .clock (clock), .reset (reset), .io_in_valid (_ifpu_io_in_valid_T), // @[FPU.scala:89:35] .io_in_bits_ldst (ifpu_io_in_bits_req_ldst), // @[FPU.scala:35:19] .io_in_bits_wen (ifpu_io_in_bits_req_wen), // @[FPU.scala:35:19] .io_in_bits_ren1 (ifpu_io_in_bits_req_ren1), // @[FPU.scala:35:19] .io_in_bits_ren2 (ifpu_io_in_bits_req_ren2), // @[FPU.scala:35:19] .io_in_bits_ren3 (ifpu_io_in_bits_req_ren3), // @[FPU.scala:35:19] .io_in_bits_swap12 (ifpu_io_in_bits_req_swap12), // @[FPU.scala:35:19] .io_in_bits_swap23 (ifpu_io_in_bits_req_swap23), // @[FPU.scala:35:19] .io_in_bits_typeTagIn (ifpu_io_in_bits_req_typeTagIn), // @[FPU.scala:35:19] .io_in_bits_typeTagOut (ifpu_io_in_bits_req_typeTagOut), // @[FPU.scala:35:19] .io_in_bits_fromint (ifpu_io_in_bits_req_fromint), // @[FPU.scala:35:19] .io_in_bits_toint (ifpu_io_in_bits_req_toint), // @[FPU.scala:35:19] .io_in_bits_fastpipe (ifpu_io_in_bits_req_fastpipe), // @[FPU.scala:35:19] .io_in_bits_fma (ifpu_io_in_bits_req_fma), // @[FPU.scala:35:19] .io_in_bits_div (ifpu_io_in_bits_req_div), // @[FPU.scala:35:19] .io_in_bits_sqrt (ifpu_io_in_bits_req_sqrt), // @[FPU.scala:35:19] .io_in_bits_wflags (ifpu_io_in_bits_req_wflags), // @[FPU.scala:35:19] .io_in_bits_rm (ifpu_io_in_bits_req_rm), // @[FPU.scala:35:19] .io_in_bits_typ (ifpu_io_in_bits_req_typ), // @[FPU.scala:35:19] .io_in_bits_in1 (io_in_bits_rs1_data_0), // @[FPU.scala:15:7] .io_out_valid (_ifpu_io_out_valid), .io_out_bits_data (_ifpu_io_out_bits_data), .io_out_bits_exc (_ifpu_io_out_bits_exc) ); // @[FPU.scala:88:20] FPToFP fpmu ( // @[FPU.scala:93:20] .clock (clock), .reset (reset), .io_in_valid (_fpmu_io_in_valid_T), // @[FPU.scala:95:35] .io_in_bits_ldst (fpmu_io_in_bits_req_ldst), // @[FPU.scala:35:19] .io_in_bits_wen (fpmu_io_in_bits_req_wen), // @[FPU.scala:35:19] .io_in_bits_ren1 (fpmu_io_in_bits_req_ren1), // @[FPU.scala:35:19] .io_in_bits_ren2 (fpmu_io_in_bits_req_ren2), // @[FPU.scala:35:19] .io_in_bits_ren3 (fpmu_io_in_bits_req_ren3), // @[FPU.scala:35:19] .io_in_bits_swap12 (fpmu_io_in_bits_req_swap12), // @[FPU.scala:35:19] .io_in_bits_swap23 (fpmu_io_in_bits_req_swap23), // @[FPU.scala:35:19] .io_in_bits_typeTagIn (fpmu_io_in_bits_req_typeTagIn), // @[FPU.scala:35:19] .io_in_bits_typeTagOut (fpmu_io_in_bits_req_typeTagOut), // @[FPU.scala:35:19] .io_in_bits_fromint (fpmu_io_in_bits_req_fromint), // @[FPU.scala:35:19] .io_in_bits_toint (fpmu_io_in_bits_req_toint), // @[FPU.scala:35:19] .io_in_bits_fastpipe (fpmu_io_in_bits_req_fastpipe), // @[FPU.scala:35:19] .io_in_bits_fma (fpmu_io_in_bits_req_fma), // @[FPU.scala:35:19] .io_in_bits_div (fpmu_io_in_bits_req_div), // @[FPU.scala:35:19] .io_in_bits_sqrt (fpmu_io_in_bits_req_sqrt), // @[FPU.scala:35:19] .io_in_bits_wflags (fpmu_io_in_bits_req_wflags), // @[FPU.scala:35:19] .io_in_bits_rm (fpmu_io_in_bits_req_rm), // @[FPU.scala:35:19] .io_in_bits_fmaCmd (fpmu_io_in_bits_req_fmaCmd), // @[FPU.scala:35:19] .io_in_bits_typ (fpmu_io_in_bits_req_typ), // @[FPU.scala:35:19] .io_in_bits_fmt (fpmu_io_in_bits_req_fmt), // @[FPU.scala:35:19] .io_in_bits_in1 (fpmu_io_in_bits_req_in1), // @[FPU.scala:35:19] .io_in_bits_in2 (fpmu_io_in_bits_req_in2), // @[FPU.scala:35:19] .io_in_bits_in3 (fpmu_io_in_bits_req_in3), // @[FPU.scala:35:19] .io_out_valid (_fpmu_io_out_valid), .io_out_bits_data (_fpmu_io_out_bits_data), .io_out_bits_exc (_fpmu_io_out_bits_exc), .io_lt (_fpiu_io_out_bits_lt) // @[FPU.scala:71:20] ); // @[FPU.scala:93:20] assign io_s1_store_data = io_s1_store_data_0; // @[FPU.scala:15:7] assign io_s1_fpiu_toint = io_s1_fpiu_toint_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fexc = io_s1_fpiu_fexc_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_ldst = io_s1_fpiu_fdiv_ldst_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_wen = io_s1_fpiu_fdiv_wen_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_ren1 = io_s1_fpiu_fdiv_ren1_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_ren2 = io_s1_fpiu_fdiv_ren2_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_ren3 = io_s1_fpiu_fdiv_ren3_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_swap12 = io_s1_fpiu_fdiv_swap12_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_swap23 = io_s1_fpiu_fdiv_swap23_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_typeTagIn = io_s1_fpiu_fdiv_typeTagIn_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_typeTagOut = io_s1_fpiu_fdiv_typeTagOut_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_fromint = io_s1_fpiu_fdiv_fromint_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_toint = io_s1_fpiu_fdiv_toint_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_fastpipe = io_s1_fpiu_fdiv_fastpipe_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_fma = io_s1_fpiu_fdiv_fma_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_div = io_s1_fpiu_fdiv_div_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_sqrt = io_s1_fpiu_fdiv_sqrt_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_wflags = io_s1_fpiu_fdiv_wflags_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_rm = io_s1_fpiu_fdiv_rm_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_fmaCmd = io_s1_fpiu_fdiv_fmaCmd_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_typ = io_s1_fpiu_fdiv_typ_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_fmt = io_s1_fpiu_fdiv_fmt_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_in1 = io_s1_fpiu_fdiv_in1_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_in2 = io_s1_fpiu_fdiv_in2_0; // @[FPU.scala:15:7] assign io_s1_fpiu_fdiv_in3 = io_s1_fpiu_fdiv_in3_0; // @[FPU.scala:15:7] assign io_out_valid = io_out_valid_0; // @[FPU.scala:15:7] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:15:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:15:7] assign io_out_rd = io_out_rd_0; // @[FPU.scala:15:7] assign io_out_tag = io_out_tag_0; // @[FPU.scala:15:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_68 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_138 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_139 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_140 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 1 parameter FORMAT = "uart_tx=%d" parameter WIDTH = 32 extmodule plusarg_reader_141 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "uart_tx_printf=%d" parameter WIDTH = 32
module TLMonitor_68( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_383 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_383( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_nvdla_cfg_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<15>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<15>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s10k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o3_a29d64s10k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s10k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s10k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset inst coupler_to_nvdla_cfg of TLInterconnectCoupler_pbus_to_nvdla_cfg connect coupler_to_nvdla_cfg.clock, childClock connect coupler_to_nvdla_cfg.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.user.amba_prot.fetch invalidate bus_xingOut.a.bits.user.amba_prot.secure invalidate bus_xingOut.a.bits.user.amba_prot.privileged invalidate bus_xingOut.a.bits.user.amba_prot.writealloc invalidate bus_xingOut.a.bits.user.amba_prot.readalloc invalidate bus_xingOut.a.bits.user.amba_prot.modifiable invalidate bus_xingOut.a.bits.user.amba_prot.bufferable invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.user.amba_prot.fetch invalidate bus_xingIn.a.bits.user.amba_prot.secure invalidate bus_xingIn.a.bits.user.amba_prot.privileged invalidate bus_xingIn.a.bits.user.amba_prot.writealloc invalidate bus_xingIn.a.bits.user.amba_prot.readalloc invalidate bus_xingIn.a.bits.user.amba_prot.modifiable invalidate bus_xingIn.a.bits.user.amba_prot.bufferable invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_15 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect coupler_to_nvdla_cfg.auto.tl_in, out_xbar.auto.anon_out_2 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready connect coupler_to_nvdla_cfg.auto.fragmenter_anon_out.d, auto.coupler_to_nvdla_cfg_fragmenter_anon_out.d connect auto.coupler_to_nvdla_cfg_fragmenter_anon_out.a.bits, coupler_to_nvdla_cfg.auto.fragmenter_anon_out.a.bits connect auto.coupler_to_nvdla_cfg_fragmenter_anon_out.a.valid, coupler_to_nvdla_cfg.auto.fragmenter_anon_out.a.valid connect coupler_to_nvdla_cfg.auto.fragmenter_anon_out.a.ready, auto.coupler_to_nvdla_cfg_fragmenter_anon_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset
module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [14:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [14:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_nvdla_cfg_fragmenter_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _coupler_to_nvdla_cfg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_nvdla_cfg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_nvdla_cfg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_nvdla_cfg_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_nvdla_cfg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [9:0] _coupler_to_nvdla_cfg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_nvdla_cfg_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_nvdla_cfg_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_nvdla_cfg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_nvdla_cfg_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [9:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_param; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_size; // @[LazyScope.scala:98:27] wire [13:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_source; // @[LazyScope.scala:98:27] wire [12:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [9:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _buffer_1_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [9:0] _buffer_1_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_1_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_user_amba_prot_bufferable; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_user_amba_prot_modifiable; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_user_amba_prot_readalloc; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_user_amba_prot_writealloc; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_user_amba_prot_privileged; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_user_amba_prot_secure; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_user_amba_prot_fetch; // @[Buffer.scala:75:28] wire [7:0] _buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_1_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_d_ready; // @[Buffer.scala:75:28] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [9:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [9:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_bufferable; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_modifiable; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_readalloc; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_writealloc; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_privileged; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_secure; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_fetch; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [9:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [9:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_bufferable; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_modifiable; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_readalloc; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_writealloc; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_privileged; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_secure; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_fetch; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_in_a_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:57:30] wire [1:0] _out_xbar_auto_anon_in_d_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:57:30] wire [9:0] _out_xbar_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_sink; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_denied; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_2_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_2_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_2_a_bits_size; // @[PeripheryBus.scala:57:30] wire [9:0] _out_xbar_auto_anon_out_2_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_2_a_bits_address; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_user_amba_prot_bufferable; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_user_amba_prot_modifiable; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_user_amba_prot_readalloc; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_user_amba_prot_writealloc; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_user_amba_prot_privileged; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_user_amba_prot_secure; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_user_amba_prot_fetch; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_2_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_2_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_2_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [9:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [9:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _fixer_auto_anon_in_a_ready; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_valid; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:54:33] wire [1:0] _fixer_auto_anon_in_d_bits_param; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:54:33] wire [9:0] _fixer_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_sink; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_denied; // @[PeripheryBus.scala:54:33] wire [63:0] _fixer_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_corrupt; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_valid; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:54:33] wire [9:0] _fixer_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:54:33] wire [28:0] _fixer_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_user_amba_prot_bufferable; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_user_amba_prot_modifiable; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_user_amba_prot_readalloc; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_user_amba_prot_writealloc; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_user_amba_prot_privileged; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_user_amba_prot_secure; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_user_amba_prot_fetch; // @[PeripheryBus.scala:54:33] wire [7:0] _fixer_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:54:33] wire [63:0] _fixer_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_d_ready; // @[PeripheryBus.scala:54:33] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] reg [63:0] pad; // @[BootAddrReg.scala:27:34] wire in_bits_read = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_1 = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_address[11:3] == 9'h0; // @[RegisterRouter.scala:75:19, :87:24] wire valids_0 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire valids_1 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire valids_2 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire valids_3 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire valids_4 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire valids_5 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire valids_6 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire valids_7 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[7]; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_valid & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_d_ready & ~in_bits_read & _out_T_1; // @[RegisterRouter.scala:74:36, :87:24] wire [2:0] nodeIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] always @(posedge _fixedClockNode_auto_anon_out_0_clock) begin // @[ClockGroup.scala:115:114] if (_fixedClockNode_auto_anon_out_0_reset) // @[ClockGroup.scala:115:114] pad <= 64'h80000000; // @[BootAddrReg.scala:27:34] else if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegisterRouter.scala:87:24] pad <= {valids_7 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[63:56] : pad[63:56], valids_6 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[55:48] : pad[55:48], valids_5 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[47:40] : pad[47:40], valids_4 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[39:32] : pad[39:32], valids_3 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[31:24] : pad[31:24], valids_2 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[23:16] : pad[23:16], valids_1 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[15:8] : pad[15:8], valids_0 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[7:0] : pad[7:0]}; // @[BootAddrReg.scala:27:34] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_28 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_28( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_68 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = or(_T_12, _T_19) node _T_49 = or(_T_48, _T_26) node _T_50 = or(_T_49, _T_33) node _T_51 = or(_T_50, _T_40) node _T_52 = or(_T_51, _T_47) node _T_53 = or(_T_5, _T_52) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_53, UInt<1>(0h1), "") : assert_1 node _T_57 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_71 = and(_T_69, _T_70) node _T_72 = or(_T_64, _T_71) node _T_73 = or(_T_57, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2
module NoCMonitor_68( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x5_1 : output auto : { flip in : { sync : UInt<1>[5]}, out : UInt<1>[5]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[5]} invalidate nodeIn.sync[0] invalidate nodeIn.sync[1] invalidate nodeIn.sync[2] invalidate nodeIn.sync[3] invalidate nodeIn.sync[4] wire nodeOut : UInt<1>[5] invalidate nodeOut[0] invalidate nodeOut[1] invalidate nodeOut[2] invalidate nodeOut[3] invalidate nodeOut[4] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync
module IntSyncSyncCrossingSink_n1x5_1( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] input auto_in_sync_2, // @[LazyModuleImp.scala:107:25] input auto_in_sync_3, // @[LazyModuleImp.scala:107:25] input auto_in_sync_4, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1, // @[LazyModuleImp.scala:107:25] output auto_out_2, // @[LazyModuleImp.scala:107:25] output auto_out_3, // @[LazyModuleImp.scala:107:25] output auto_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire auto_in_sync_2_0 = auto_in_sync_2; // @[Crossing.scala:96:9] wire auto_in_sync_3_0 = auto_in_sync_3; // @[Crossing.scala:96:9] wire auto_in_sync_4_0 = auto_in_sync_4; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeIn_sync_2 = auto_in_sync_2_0; // @[Crossing.scala:96:9] wire nodeIn_sync_3 = auto_in_sync_3_0; // @[Crossing.scala:96:9] wire nodeIn_sync_4 = auto_in_sync_4_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire nodeOut_2; // @[MixedNode.scala:542:17] wire nodeOut_3; // @[MixedNode.scala:542:17] wire nodeOut_4; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] wire auto_out_2_0; // @[Crossing.scala:96:9] wire auto_out_3_0; // @[Crossing.scala:96:9] wire auto_out_4_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_2 = nodeIn_sync_2; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_3 = nodeIn_sync_3; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_4 = nodeIn_sync_4; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_2_0 = nodeOut_2; // @[Crossing.scala:96:9] assign auto_out_3_0 = nodeOut_3; // @[Crossing.scala:96:9] assign auto_out_4_0 = nodeOut_4; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] assign auto_out_2 = auto_out_2_0; // @[Crossing.scala:96:9] assign auto_out_3 = auto_out_3_0; // @[Crossing.scala:96:9] assign auto_out_4 = auto_out_4_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_25 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_25( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_57 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_57( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_SlaveXbar_Cluster_i0_o0_a1d8s1k1z1u_1 : input clock : Clock input reset : Reset output auto : { } wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0]
module TLXbar_SlaveXbar_Cluster_i0_o0_a1d8s1k1z1u_1( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset // @[Xbar.scala:74:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_164 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_179 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_164( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_179 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_1_router_17ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_46 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLNoC_1_router_17ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_46 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_106 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_106( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_16 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_32 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_16 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<3>(0h4), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<2>(0h2), io.in.bits.egress_id) node _T_4 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _T_5 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _T_6 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _T_7 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _T_8 = or(_T, _T_1) node _T_9 = or(_T_8, _T_2) node _T_10 = or(_T_9, _T_3) node _T_11 = or(_T_10, _T_4) node _T_12 = or(_T_11, _T_5) node _T_13 = or(_T_12, _T_6) node _T_14 = or(_T_13, _T_7) node _T_15 = eq(_T_14, UInt<1>(0h0)) node _T_16 = and(io.in.valid, _T_15) node _T_17 = eq(_T_16, UInt<1>(0h0)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_17, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h6) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h3) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0hd), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0he), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h4), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_5, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_6, UInt<3>(0h7), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_7, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_9) node _route_buffer_io_enq_bits_flow_egress_node_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_T_16, _route_buffer_io_enq_bits_flow_egress_node_T_10) node _route_buffer_io_enq_bits_flow_egress_node_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_T_17, _route_buffer_io_enq_bits_flow_egress_node_T_11) node _route_buffer_io_enq_bits_flow_egress_node_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_T_18, _route_buffer_io_enq_bits_flow_egress_node_T_12) node _route_buffer_io_enq_bits_flow_egress_node_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_T_19, _route_buffer_io_enq_bits_flow_egress_node_T_13) node _route_buffer_io_enq_bits_flow_egress_node_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_T_20, _route_buffer_io_enq_bits_flow_egress_node_T_14) node _route_buffer_io_enq_bits_flow_egress_node_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_T_21, _route_buffer_io_enq_bits_flow_egress_node_T_15) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_22 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_6, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_7, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) node _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_16, _route_buffer_io_enq_bits_flow_egress_node_id_T_10) node _route_buffer_io_enq_bits_flow_egress_node_id_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_17, _route_buffer_io_enq_bits_flow_egress_node_id_T_11) node _route_buffer_io_enq_bits_flow_egress_node_id_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_18, _route_buffer_io_enq_bits_flow_egress_node_id_T_12) node _route_buffer_io_enq_bits_flow_egress_node_id_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_19, _route_buffer_io_enq_bits_flow_egress_node_id_T_13) node _route_buffer_io_enq_bits_flow_egress_node_id_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_20, _route_buffer_io_enq_bits_flow_egress_node_id_T_14) node _route_buffer_io_enq_bits_flow_egress_node_id_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_21, _route_buffer_io_enq_bits_flow_egress_node_id_T_15) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_22 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h6)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_21 = and(io.in.ready, io.in.valid) node _T_22 = and(_T_21, io.in.bits.head) node _T_23 = and(_T_22, at_dest) when _T_23 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_24 = eq(UInt<5>(0h18), io.in.bits.egress_id) when _T_24 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_25 = eq(UInt<5>(0h19), io.in.bits.egress_id) when _T_25 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_26 = eq(UInt<5>(0h1a), io.in.bits.egress_id) when _T_26 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_27 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_28 = and(route_q.io.enq.valid, _T_27) node _T_29 = eq(_T_28, UInt<1>(0h0)) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_33 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_16 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_33 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_34 = and(vcalloc_q.io.enq.valid, _T_33) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1
module IngressUnit_16( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h4; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h2; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h6; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'hA; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h8; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'hC; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_17 = {2'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T, 1'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'hD : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hE : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_22 = {_route_buffer_io_enq_bits_flow_egress_node_T_17[3] | _route_buffer_io_enq_bits_flow_egress_node_id_T_5, {_route_buffer_io_enq_bits_flow_egress_node_T_17[2] | _route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_17[1], _route_buffer_io_enq_bits_flow_egress_node_T_17[0] | _route_buffer_io_enq_bits_flow_egress_node_id_T_3} | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_6}}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hB : 4'h0); // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_22 == 4'h6; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_22 != 4'h6; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_28 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_269 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_270 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_271 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_272 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_28( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_269 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_270 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_271 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_272 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_sbus_to_sport_named_rerocc_0 : input clock : Clock input reset : Reset output auto : { } inst buffer of TLBuffer connect buffer.clock, clock connect buffer.reset, reset inst widget of TLWidthWidget8_3 connect widget.clock, clock connect widget.reset, reset inst buffer_1 of TLBuffer_1 connect buffer_1.clock, clock connect buffer_1.reset, reset extmodule plusarg_reader_16 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_17 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLInterconnectCoupler_sbus_to_sport_named_rerocc_0( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset // @[LazyModuleImp.scala:138:7] ); TLBuffer buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset) ); // @[Buffer.scala:75:28] TLBuffer_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset) ); // @[Buffer.scala:75:28] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_13 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<1>(0h0)) node mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<1>(0h0)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(UInt<1>(0h1)) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<1>(0h0)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<1>(0h0)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<1>(0h0)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 0) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<12>, clock, reset, UInt<12>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 0) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 0) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<12>, clock, reset, UInt<12>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 0) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_26 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<8>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<8>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 0) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<12>, clock, reset, UInt<12>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 0) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<8>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<8>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<8>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<8>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<8>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<8>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<8>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<8>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<8>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_27 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_13( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_a_bits_mask = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] c_first_beats1_decode = 12'h0; // @[Edges.scala:220:59] wire [11:0] c_first_beats1 = 12'h0; // @[Edges.scala:221:14] wire [11:0] _c_first_count_T = 12'h0; // @[Edges.scala:234:27] wire [11:0] c_first_count = 12'h0; // @[Edges.scala:234:25] wire [11:0] _c_first_counter_T = 12'h0; // @[Edges.scala:236:21] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] c_first_counter1 = 12'hFFF; // @[Edges.scala:230:28] wire [12:0] _c_first_counter1_T = 13'h1FFF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] _c_set_wo_ready_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode = _a_first_beats1_decode_T_2; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T = {1'h0, a_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1 = _a_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode = _d_first_beats1_decode_T_2; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [11:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T = {1'h0, d_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1 = _d_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1_1 = _a_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5; // @[package.scala:243:46] wire [11:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_1 = _d_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8; // @[package.scala:243:46] wire [11:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_2; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_2 = _d_first_counter1_T_2[11:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_384 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_128 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_384( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_128 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TestHarness : input clock : Clock input reset : UInt<1> output io : { success : UInt<1>} wire harnessBinderClock : Clock wire harnessBinderReset : Reset wire success : UInt<1> connect success, UInt<1>(0h0) connect io.success, success inst chiptop0 of ChipTop inst uart_sim_0_uartno0 of UARTAdapter connect uart_sim_0_uartno0.clock, harnessBinderClock connect uart_sim_0_uartno0.reset, harnessBinderReset connect uart_sim_0_uartno0.io.uart.txd, chiptop0.uart_0.txd connect chiptop0.uart_0.rxd, uart_sim_0_uartno0.io.uart.rxd inst simdram of SimDRAM connect simdram.clock, chiptop0.axi4_mem_0.clock node _simdram_io_reset_T = asAsyncReset(harnessBinderReset) connect simdram.reset, _simdram_io_reset_T connect chiptop0.axi4_mem_0.bits.r.bits.last, simdram.axi.r.bits.last connect chiptop0.axi4_mem_0.bits.r.bits.resp, simdram.axi.r.bits.resp connect chiptop0.axi4_mem_0.bits.r.bits.data, simdram.axi.r.bits.data connect chiptop0.axi4_mem_0.bits.r.bits.id, simdram.axi.r.bits.id connect chiptop0.axi4_mem_0.bits.r.valid, simdram.axi.r.valid connect simdram.axi.r.ready, chiptop0.axi4_mem_0.bits.r.ready connect simdram.axi.ar.bits.qos, chiptop0.axi4_mem_0.bits.ar.bits.qos connect simdram.axi.ar.bits.prot, chiptop0.axi4_mem_0.bits.ar.bits.prot connect simdram.axi.ar.bits.cache, chiptop0.axi4_mem_0.bits.ar.bits.cache connect simdram.axi.ar.bits.lock, chiptop0.axi4_mem_0.bits.ar.bits.lock connect simdram.axi.ar.bits.burst, chiptop0.axi4_mem_0.bits.ar.bits.burst connect simdram.axi.ar.bits.size, chiptop0.axi4_mem_0.bits.ar.bits.size connect simdram.axi.ar.bits.len, chiptop0.axi4_mem_0.bits.ar.bits.len connect simdram.axi.ar.bits.addr, chiptop0.axi4_mem_0.bits.ar.bits.addr connect simdram.axi.ar.bits.id, chiptop0.axi4_mem_0.bits.ar.bits.id connect simdram.axi.ar.valid, chiptop0.axi4_mem_0.bits.ar.valid connect chiptop0.axi4_mem_0.bits.ar.ready, simdram.axi.ar.ready connect chiptop0.axi4_mem_0.bits.b.bits.resp, simdram.axi.b.bits.resp connect chiptop0.axi4_mem_0.bits.b.bits.id, simdram.axi.b.bits.id connect chiptop0.axi4_mem_0.bits.b.valid, simdram.axi.b.valid connect simdram.axi.b.ready, chiptop0.axi4_mem_0.bits.b.ready connect simdram.axi.w.bits.last, chiptop0.axi4_mem_0.bits.w.bits.last connect simdram.axi.w.bits.strb, chiptop0.axi4_mem_0.bits.w.bits.strb connect simdram.axi.w.bits.data, chiptop0.axi4_mem_0.bits.w.bits.data connect simdram.axi.w.valid, chiptop0.axi4_mem_0.bits.w.valid connect chiptop0.axi4_mem_0.bits.w.ready, simdram.axi.w.ready connect simdram.axi.aw.bits.qos, chiptop0.axi4_mem_0.bits.aw.bits.qos connect simdram.axi.aw.bits.prot, chiptop0.axi4_mem_0.bits.aw.bits.prot connect simdram.axi.aw.bits.cache, chiptop0.axi4_mem_0.bits.aw.bits.cache connect simdram.axi.aw.bits.lock, chiptop0.axi4_mem_0.bits.aw.bits.lock connect simdram.axi.aw.bits.burst, chiptop0.axi4_mem_0.bits.aw.bits.burst connect simdram.axi.aw.bits.size, chiptop0.axi4_mem_0.bits.aw.bits.size connect simdram.axi.aw.bits.len, chiptop0.axi4_mem_0.bits.aw.bits.len connect simdram.axi.aw.bits.addr, chiptop0.axi4_mem_0.bits.aw.bits.addr connect simdram.axi.aw.bits.id, chiptop0.axi4_mem_0.bits.aw.bits.id connect simdram.axi.aw.valid, chiptop0.axi4_mem_0.bits.aw.valid connect chiptop0.axi4_mem_0.bits.aw.ready, simdram.axi.aw.ready inst plusarg_reader of plusarg_reader_151 connect chiptop0.custom_boot, plusarg_reader.out wire dtm_success : UInt<1> connect dtm_success, UInt<1>(0h0) when dtm_success : connect success, UInt<1>(0h1) wire jtag_wire : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}} connect jtag_wire.TDO.data, chiptop0.jtag.TDO connect jtag_wire.TDO.driven, UInt<1>(0h1) connect chiptop0.jtag.TCK, jtag_wire.TCK connect chiptop0.jtag.TMS, jtag_wire.TMS connect chiptop0.jtag.TDI, jtag_wire.TDI inst jtag of SimJTAG node _T = asUInt(harnessBinderReset) node _T_1 = asUInt(harnessBinderReset) node _T_2 = not(_T_1) connect jtag_wire.TCK, jtag.jtag.TCK connect jtag_wire.TMS, jtag.jtag.TMS connect jtag_wire.TDI, jtag.jtag.TDI connect jtag.jtag.TDO.driven, jtag_wire.TDO.driven connect jtag.jtag.TDO.data, jtag_wire.TDO.data connect jtag.clock, harnessBinderClock connect jtag.reset, _T inst plusarg_reader_1 of plusarg_reader_152 connect jtag.enable, plusarg_reader_1.out connect jtag.init_done, _T_2 node _dtm_success_T = eq(jtag.exit, UInt<1>(0h1)) connect dtm_success, _dtm_success_T node _T_3 = lt(jtag.exit, UInt<2>(0h2)) node _T_4 = dshr(jtag.exit, UInt<1>(0h1)) node _T_5 = asUInt(harnessBinderReset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_3, UInt<1>(0h0)) when _T_7 : printf(harnessBinderClock, UInt<1>(0h1), "Assertion failed: *** FAILED *** (exit code = %d)\n\n at Periphery.scala:236 assert(io.exit < 2.U, \"*** FAILED *** (exit code = %%%%d)\\n\", io.exit >> 1.U)\n", _T_4) : printf assert(harnessBinderClock, _T_3, UInt<1>(0h1), "") : assert wire chiptop0_clock_uncore_clock : Clock connect chiptop0.clock_uncore, chiptop0_clock_uncore_clock node _chiptop0_reset_io_T = asAsyncReset(reset) connect chiptop0.reset_io, _chiptop0_reset_io_T connect chiptop0.serial_tl_0.clock_in, harnessBinderClock inst ram of SerialRAM connect ram.clock, harnessBinderClock connect ram.reset, harnessBinderReset connect ram.io.ser.in, chiptop0.serial_tl_0.out connect chiptop0.serial_tl_0.in, ram.io.ser.out inst success_exit_sim of SimTSI connect success_exit_sim.clock, harnessBinderClock connect success_exit_sim.reset, harnessBinderReset connect success_exit_sim.tsi.out.bits, ram.io.tsi.out.bits connect success_exit_sim.tsi.out.valid, ram.io.tsi.out.valid connect ram.io.tsi.out.ready, success_exit_sim.tsi.out.ready connect ram.io.tsi.in.bits, success_exit_sim.tsi.in.bits connect ram.io.tsi.in.valid, success_exit_sim.tsi.in.valid connect success_exit_sim.tsi.in.ready, ram.io.tsi.in.ready node success_1 = eq(success_exit_sim.exit, UInt<1>(0h1)) node success_error = geq(success_exit_sim.exit, UInt<2>(0h2)) node _success_T = eq(success_error, UInt<1>(0h0)) node _success_T_1 = dshr(success_exit_sim.exit, UInt<1>(0h1)) node _success_T_2 = asUInt(harnessBinderReset) node _success_T_3 = eq(_success_T_2, UInt<1>(0h0)) when _success_T_3 : node _success_T_4 = eq(_success_T, UInt<1>(0h0)) when _success_T_4 : printf(harnessBinderClock, UInt<1>(0h1), "Assertion failed: *** FAILED *** (exit code = %d)\n\n at SimTSI.scala:21 assert(!error, \"*** FAILED *** (exit code = %%%%d)\\n\", exit >> 1.U)\n", _success_T_1) : success_printf assert(harnessBinderClock, _success_T, UInt<1>(0h1), "") : success_assert when success_1 : connect success, UInt<1>(0h1) wire harnessBinderClk : Clock connect harnessBinderClock, harnessBinderClk inst harnessBinderReset_catcher of ResetCatchAndSync_d3_4 connect harnessBinderReset_catcher.clock, harnessBinderClk connect harnessBinderReset_catcher.reset, reset wire _harnessBinderReset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _harnessBinderReset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) connect _harnessBinderReset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0) wire _harnessBinderReset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _harnessBinderReset_catcher_io_psd_WIRE_1, _harnessBinderReset_catcher_io_psd_WIRE connect harnessBinderReset_catcher.io.psd, _harnessBinderReset_catcher_io_psd_WIRE_1 connect harnessBinderReset, harnessBinderReset_catcher.io.sync_reset inst source of ClockSourceAtFreqMHz connect source.power, UInt<1>(0h1) connect source.gate, UInt<1>(0h0) connect chiptop0_clock_uncore_clock, source.clk inst source_1 of ClockSourceAtFreqMHz_1 connect source_1.power, UInt<1>(0h1) connect source_1.gate, UInt<1>(0h0) connect harnessBinderClk, source_1.clk
module TestHarness( // @[TestHarness.scala:19:7] input clock, // @[TestHarness.scala:19:7] input reset, // @[TestHarness.scala:19:7] output io_success // @[TestHarness.scala:20:14] ); wire _source_1_clk; // @[HarnessClocks.scala:70:26] wire _source_clk; // @[HarnessClocks.scala:70:26] wire _harnessBinderReset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28] wire _success_exit_sim_tsi_in_valid; // @[SimTSI.scala:12:23] wire [31:0] _success_exit_sim_tsi_in_bits; // @[SimTSI.scala:12:23] wire _success_exit_sim_tsi_out_ready; // @[SimTSI.scala:12:23] wire [31:0] _success_exit_sim_exit; // @[SimTSI.scala:12:23] wire _ram_io_ser_in_ready; // @[HarnessBinders.scala:253:27] wire _ram_io_ser_out_valid; // @[HarnessBinders.scala:253:27] wire [31:0] _ram_io_ser_out_bits_phit; // @[HarnessBinders.scala:253:27] wire _ram_io_tsi_in_ready; // @[HarnessBinders.scala:253:27] wire _ram_io_tsi_out_valid; // @[HarnessBinders.scala:253:27] wire [31:0] _ram_io_tsi_out_bits; // @[HarnessBinders.scala:253:27] wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire _jtag_jtag_TCK; // @[HarnessBinders.scala:184:22] wire _jtag_jtag_TMS; // @[HarnessBinders.scala:184:22] wire _jtag_jtag_TDI; // @[HarnessBinders.scala:184:22] wire [31:0] _jtag_exit; // @[HarnessBinders.scala:184:22] wire _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _simdram_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [3:0] _simdram_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [3:0] _simdram_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _uart_sim_0_uartno0_io_uart_rxd; // @[SimUART.scala:76:28] wire _chiptop0_uart_0_txd; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_0_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_0_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_0_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_0_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_0_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_jtag_TDO; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_serial_tl_0_in_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_serial_tl_0_out_valid; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_serial_tl_0_out_bits_phit; // @[HasHarnessInstantiators.scala:87:40]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_7 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T
module MulAddRecFNToRaw_preMul_e8_s24_7( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule